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High density phase change memory array requires both minimized critical dimension (CD) and maximized process window for the phase change material layer. High in-wafer uniformity of the nanoscale patterning of chalcogenides material is challenging given the optical proximity effect (OPE) in the lithography process and the micro-loading effect in the etching process. In this study, we demonstrate an approach to fabricate high density phase change material arrays with half-pitch down to around 70 nm by the co-optimization of lithography and plasma etching process. The focused-energy matrix was performed to improve the pattern process window of phase change material on a 12-inch wafer. A variety of patternings from an isolated line to a dense pitch line were investigated using immersion lithography system. The collapse of the edge line is observed due to the OPE induced shrinkage in linewidth, which is deteriorative as the patterning density increases. The sub-resolution assist feature (SRAF) was placed to increase the width of the lines at both edges of each patterning by taking advantage of the optical interference between the main features and the assistant features. The survival of the line at the edges is confirmed with around a 70 nm half-pitch feature in various arrays. A uniform etching profile across the pitch line pattern of phase change material was demonstrated in which the micro-loading effect and the plasma etching damage were significantly suppressed by co-optimizing the etching parameters. The results pave the way to achieve high density device arrays with improved uniformity and reliability for mass storage applications. [ABSTRACT FROM AUTHOR]

This paper presents the Step-by-Step Design of memory hierarchy for heterogeneously-integrated SCM/NAND flash storage. The heterogeneously-integrated storages utilize multiple types of non-volatile memories such as storage class memories (SCMs) and NAND flash memories. SCMs are further classified to memory-type and storage-type. NAND flash memories are also characterized by the number of stored bits per cell. These non-volatile memories show complex trade-off of various latency, power, capacity and cost. What's worse, in NAND flash, garbage collection seriously degrades the performance. Thus, the intelligent mix & match of these memories is required, depending on each workload. For various storage applications, this paper shows that optimal SCM/NAND flash hierarchies are determined by considering system performance, energy consumption, endurance, and cost for each workload. The recommended non-volatile memory combinations with SCMs and NAND flash memories are proposed for representative 7 storage application workloads with diverse characteristics. The proposed Step-by-Step Design is the useful solution for the heterogeneously-integrated storage with multiple types of non-volatile memories and for various applications. [ABSTRACT FROM AUTHOR]

Recent developments in storage class memory (SCM) such as PCM, MRAM, resistive RAM (RRAM), and spin-transfer torque (STT)-RAM have strengthened their leadership as storage media for memory-based file systems. Traditional Linux memory-based file systems such as Ramfs and Tmpfs utilize the Linux page cache as a file system. These file systems have unnecessary overheads when adopted for SCM file system. Therefore, we propose a new memory-based file system using Memory Zone Partitioning called ZonFS, by extending the Linux Ramfs. In particular, we define a storage zone for SCM, modify the Ramfs to allocate a file system page from SCM. ZonFS avoids running Linux VM kernel codes such as (i) inserting pages allocated from SCM into the LRU list for VM page replacement and (ii) checking dirty pages for write-back to disk. Our extensive evaluations indicate that ZonFS has up to 9.1 and 14.1% higher I/O throughputs than native Ramfs and Tmpfs. Moreover, we also analyze performance behavior of ZonFS under the non-uniform memory access architecture of SCMs on a 40 manycore machine with various configurations such as file sharing level and file stripping level. Our evaluations show that memory controller contention and inter-node link congestion significantly affect the file system's performance and scalability. [ABSTRACT FROM AUTHOR]

The cross-point architecture for memory arrays is widely considered as one of the most attractive solutions for storage and memory circuits thanks to simplicity, scalability, small cell size, and consequently high density and low cost. Cost-scalable vertical 3-D cross-point architectures, in particular, offer the opportunity to challenge Flash memory with comparable density and cost. To develop scalable cross-point arrays, however, select devices with sufficient ON–OFF ratio, current capability, and endurance must be available. This paper presents a select device technology based on volatile resistive switching with Cu and Ag top electrode and silicon oxide (SiOx) switching materials. The select device displays ultrahigh resistance window and good current capability exceeding 2 MAcm−2. Retention study shows a stochastic voltage-dependent ON–OFF transition time in the 10~\mu \texts –1 ms range, which needs to be further optimized for fast memory operation in storage class memory arrays. [ABSTRACT FROM PUBLISHER]

Hybrid memory comprised of a big SCM and a little DRAM (BSLD) is widely studied to address the growing power consumption challenge of pure DRAM. However, the performance degradation, limited endurance and immature mass production of ultra-high-density SCM are still the painful points of BSLD. Here we propose a Retention-Aware Hybrid Main Memory (RAHMM) architecture with a big DRAM and a little SCM (BDLS) for the first time. DRAM is refreshed at a much longer interval by using SCM to store the small quantity of leaky tail bits in DRAM. A two-step search technology combined with outcome forecasting is put forward to get ultra-fast read access, as well as to diminish the power and performance overheads. A hidden buffer strategy (HBS) is proposed to optimize write performance and endurance hurt. The experimental results show 45 percent reduction of power consumption and 30 percent performance optimization, which are significantly improved compared to that of both serial and parallel BSLD with a counterpart capacity [ABSTRACT FROM AUTHOR]

New storage class memory (SCM) technologies, such as phase change memory (PCM) and memristors, are not only byte-addressable like DRAM but also non-volatile like traditional hard disk drives. SCM modules can be placed side-by-side with DRAM on the memory bus, available to memory instructions issued by the CPU. This shift thus engenders a new “DRAM-SCM” storage architecture, which promises near-DRAM secondary storage access speed at several orders of magnitude faster than magnetic disk or flash memory. Utilizing SCM as a secondary storage device will have a profound impact on memory hierarchy design, requiring new architectural and operating system support. In this paper, we adopt PCM in the DRAM-SCM storage architecture and present BSS to provide file system-independent B lock device S upport for S torage class memory. To ensure backward compatibility and high performance, BSS provides a block device interface found in traditional hard disk drives and allows existing file systems to be built on top of itself without any modifications. BSS is designed to directly access the PCM through memory instructions and bypass traditional disk caches that are intended to reduce seek time. The DRAM-SCM architecture and BSS are prototyped in QEMU and the Linux kernel, respectively. Validation using benchmarks reveals that both work together well to exploit significant advantages of SCM. Compared to traditional hard disk drives, our approach boosts the write/read performance by up to 204x for large files and achieves comparable performance for small ones. [ABSTRACT FROM AUTHOR]

Solid-state drives (SSDs), composed of NAND flash memories, are replacing hard disk drives (HDDs) rapidly. In addition, storage class memories (SCMs) bridge the bandwidth gap between DRAM and NAND flash, thus introducing SCM to SSD further improves the solid storage performance. Different from schemes that use SCM to store file system metadata or logical to physical mapping tables, two architectures 1) use SCM as a write-back non-volatile memory (NVM) based cache, 2) use SCM as a storage device are presented in this paper. Since SCM chip latency varies due to memory device and circuit design, three SSD data management algorithms are evaluated under five SCM chip design scenarios to provide useful design guidelines of SCM/NAND flash hybrid SSD. SCM interface and capacity requirement are also analyzed. From the experimental results, less than 10% of the SCM/NAND flash capacity ratio is enough for SCM chips with 500 ns read and 5 μs write latency to boost NAND flash-only SSD speed by over 10 times when workloads own high IO skew1. [ABSTRACT FROM PUBLISHER]

Various emerging resistive memory technologies, such as phase change memory, have drawn attention in recent decades because they provide persistency, byte-addressability, low latency near that of DRAM, and high density.Storage-class memory(SCM) is the class of these memory technologies that have the best memory and storage properties. SCM can be accessed directly via load and store instructions because it is placed on a memory bus. In this paper, we introduce SCM in the context of emerging non-volatile memory technologies and review the efforts that have been made to utilize SCM in computer systems and exploit it for performance or reliability purposes. We also discuss the challenges and opportunities that accompany adopting SCM in computer systems. We focus more on issues of exploiting SCM because its potential for computer systems and applications is substantial, and accordingly, many more studies are expected. [ABSTRACT FROM PUBLISHER]

After decades of a cache, DRAM, and disk data storage hierarchy, new memory technologies are promising nonvolatility, high endurance, and fine-grained data access--all of which could, with some preparation, enable a new storage paradigm in server systems. [ABSTRACT FROM PUBLISHER]

Phase-change memory (PCM) is the best candidate for the storage device of next-generation mobile consumer electronics. PCM has the potential to replace NAND flash memory, due to its non-volatility, in-place programmability, and low power consumption. Even though the lifetime of PCM is longer than that of flash memory, wear leveling is still required to cope with the non-uniformity of storage workload or malicious attack. In this paper, a novel wear-leveling algorithm for PCM storage is proposed, where more physical pages are allocated to frequently updated logical pages, to balance the wear counts of PCM cells. In comparison with the previous techniques, the proposed algorithm improved the lifetime of PCM by at maximum 14 times and on average 8 times. [ABSTRACT FROM AUTHOR]

Phase change memory (PCM) has opportunities of various applications on the premise of its high performance operations, which are still to develop with innovations such as change of a memory material. In respects of high-speed and high-scalability memory characteristics, δ-phase Ge-doped SbTe (GeST) materials stand as highly promising candidates. An overview of the material and device characteristics of these materials is presented primarily based on our recent experimental and computational studies and with a particular regard to their Sb-to-Te ratio (STR) dependence. TEM images of the δ-phase GeST microstructures of varying STR and a highly scaled PCM cell with a δ-phase GeST of high STR. [ABSTRACT FROM AUTHOR]

We explore the possibility of deploying storage class memory (SCM) into the I/O path as a file system metadata store and examine what effects it has on the performance of portable computing systems. In this regard, we develop a new flash memory-based file system that stores all metadata in SCM, while storing all file data in flash memory. In so doing, we make two contributions in this work. First, we present a model that analyzes the amount of SCM that is needed for specific flash memory storage capacity. Second, we present quantitative experimental results that show how much performance gains are possible by exploiting SCM in terms of I/O performance, energy efficiency and lifetime of the underlying flash memory. Compared to YAFFS, a popular flash memory-based file system, we show that system performance is improved by a maximum of around 320, 260, and 180% in terms of I/O performance, energy efficiency and lifetime of the Flash memory, respectively, for the realistic workloads that we considered. [ABSTRACT FROM AUTHOR]

• Transition of local environment of Indium triggers bond-interchange of Antimony. • Local environment of Indium changes from tetrahedron to octahedron. • Metavalent bonding in Sb matrix largely varies on the local environment of Indium. Reversible phase-change is one of the most promising bases to store data for universal electronic memory. Rapid and energy efficient crystallization of Ag-In-Sb-Te, owing to miniscule atomic displacements, has dragged large interest. However, crystallization mechanism at atomic scale and role of element in Ag-In-Sb-Te remain inconclusive. We studied evolution of chemical bonding on crystallization of Ag-In-Sb-Te, i.e., chemical bonding of element In dramatically changes on crystallization from Sb-bonds (In-Sb) to Te-bonds (In-Te). The local environments of In corresponding to In-Sb and In-Te bonds are characterized as InSb-like and AgInTe 2 -like site, respectively. Further, In largely modulates the degree of atomic ordering and activation energy for crystallization despite of low composition. The overall results suggest that crystallization of Ag-In-Sb-Te is deployed by the transition of local environment of In from InSb-like to AgInTe 2 -like site. It suggests role of Ag, In, and Te on crystallization, i.e., Ag provides structural flexibility for transition in local environment of In, In disrupts crystallization, and Te assists the other elements to play their respective roles. The present work on the unique crystallization mechanism of Ag-In-Sb-Te successfully accounts for the memory properties depending on composition and can be applied to development of future memory device. [ABSTRACT FROM AUTHOR]

Koo, S.M.; Seo, J.M.; Song. Y.J., and Baek, S.J., 2020. Storage class memory based hybrid memory system for practical remote sensing. In: Jung, H.-S.; Lee, S., and Ryu, J.-H. (eds.), In: Jung, H.-S.; Lee, S.; Ryu, J.-H., and Cui, T. (eds.), Advances in Geospatial Research of Coastal Environments. Journal of Coastal Research, Special Issue No. 102, pp. 254-260. Coconut Creek (Florida), ISSN 0749-0208. In the remote sensing domain, large-sized, files such as high-resolution satellite images or sonar video clips from unmanned underwater vehicles are very common. For processing big files, a large main memory is necessary. The main memory capacity highly influences the performance of computer systems. The demand for DRAM capacity has never been satisfied, and more importantly, large DRAM systems suffer from significant power consumption. To ease the problem, a promising solution is to build a hybrid main memory (HMM) system composed of a small number of fast DRAMs and many inexpensive devices. By mimicking large and fast main memory capacity, HMM allows computer systems to run applications that require more DRAM than is installed on the system. In this paper, a novel HMM management scheme for a storage class memory (SCM)-based HMM was introduced. As all the data stored on SCM are already non-volatile, the overall performance of the computer system is enhanced further by not flushing them periodically. The proposed idea was implemented on Linux and its performance was measured using an SCM emulation system. It was shown that HMM efficiently improves performance by up to 77.9 %, compared with a conventional operating system. Additionally, it was demonstrated that the proposed idea's fault recovery mechanisms could restore dirty data that are not yet synchronized with storage, within 91 % of the test time. [ABSTRACT FROM AUTHOR]

This installment of Computer's series highlighting the work published in IEEE Computer Society journals comes from Computer Architecture Letters. [ABSTRACT FROM AUTHOR]