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In-memory computing is an attractive solution for reducing power consumption and memory access latency cost by performing certain computations directly in memory without reading operands and sending them to arithmetic logic units. Content-addressable memory (CAM) is an ideal way to smooth out the distinction between storage and processing, since each memory cell is a processing unit. CAM compares the search input with a table of stored data and returns the matched data address. The issues of constructing binary and ternary content-addressable memory (CAM and TCAM) based on ferroelectric devices are considered. A review of ferroelectric materials and devices is carried out, including on ferroelectric transistors (FeFET), ferroelectric tunnel diodes (FTJ), and ferroelectric memristors. [ABSTRACT FROM AUTHOR]

The brain has computational capabilities that surpass those of modern systems, being able to solve complex problems efficiently in a simple way. Neuromorphic engineering aims to mimic biology in order to develop new systems capable of incorporating such capabilities. Bio-inspired learning systems continue to be a challenge that must be solved, and much work needs to be done in this regard. Among all brain regions, the hippocampus stands out as an autoassociative short-term memory with the capacity to learn and recall memories from any fragment of them. These characteristics make the hippocampus an ideal candidate for developing bio-inspired learning systems that, in addition, resemble content-addressable memories. Therefore, in this work we propose a bio-inspired spiking content-addressable memory model based on the CA3 region of the hippocampus with the ability to learn, forget and recall memories, both orthogonal and non-orthogonal, from any fragment of them. The model was implemented on the SpiNNaker hardware platform using Spiking Neural Networks. A set of experiments based on functional, stress and applicability tests were performed to demonstrate its correct functioning. This work presents the first hardware implementation of a fully-functional bio-inspired spiking hippocampal content-addressable memory model, paving the way for the development of future more complex neuromorphic systems. [ABSTRACT FROM AUTHOR]

Content-addressable memories (CAMs) allow searching a pattern, processing in parallel all the data stored. Beyond-CMOS technologies can provide new opportunities to improve CAM memories implementations both at the device and architectural level. In this article, we propose a ternary content-addressable memory cell based on skyrmion technology. The proposed memory cell is based on skyrmion racetrack memory. The cell is able to signal if the bit contained in the cell in form of skyrmion corresponds to an electrical input, the target of the search operation. The proposed design, verified by means of micromagnetic simulations, has an area of 0.054 ÎĽ m2 and can perform a search operation in 3.3 ns with an energy of 10.5 fJ. The operation performed is non-destructive and does not require conversion between the magnetic and the electronic domains. For this reason, the designed cell has the potential to be used as a basic block for non-volatile CAM memories. Here, we propose also a layout structure to implement a CAM memory employing the proposed cell. This structure allows to achieve memory density comparable to traditional racetrack memories and execute at the same time CAM operations. [ABSTRACT FROM AUTHOR]

Highlights • A single set of Memristor crossbar array is extended for bidirectional synaptic weighting operation, which is convenient and cost-effective in hardware implementation of artificial neural networks. • The on-chip learning circuits and related learning algorithm for memristive BAM are considered to train the system to memorize pattern pairs, together with a novel programming strategy to ease the process of tuning memristance. • We have implemented and demonstrated meaningful pattern can be trained and recalled by the proposed memristive BAM system. • BAM neuron activation function is realized by digital circuit element JK flip-flop. • The Verilog-AMS design methodolgy adopted in this study can be a good candidate for system level design of memristor-based large scale ANN circuit when both digital circuit element and analog memristors are employed. Abstract Recently, memristor as an emerging device has been used as the basic synapse realization component for the circuit implementation of artificial neural networks. Following this trend, this paper studies the circuit realization of a memristor-based bidirectional associative memory (BAM) system that extends the memristor crossbar array structure for bidirectional synaptic weighting operation. The neuron cell in BAM is represented by digital circuit element JK flip-flop for hardware cost-saving. Meanwhile a novel memristor programming strategy is also considered and examined to ease the on-chip learning. The design of such memristive BAM circuit system is conducted by hardware description language Verilog-AMS and has been validated in a commercial circuit simulation environment via a case study. Test results show that a set of binary character patterns can be memorized and recalled successfully by the trained memristive BAM system. [ABSTRACT FROM AUTHOR]

Abstract: The growing complexity of Field Programmable Gate Arrays (FPGA’s) is leading to architectures with high input cardinality look-up tables (LUT’s). This paper describes a methodology for area-optimal combinational technology mapping, specifically designed for such FPGA architectures. This methodology, called LURU, leverages the parallel search capabilities of Content-Addressable Memories (CAM’s) to outperform traditional mapping algorithms in both execution time and quality of results. The LURU algorithm is fundamentally different from other techniques for technology mapping in that LURU uses textual representations of circuit topology in order to efficiently store and search for circuit patterns in a CAM. A circuit is mapped to the target LUT technology using exact, inexact, or hybrid matching techniques. Common subcircuit expressions (CSE’s) are also identified and used for architectural optimization—a small set of CSE’s is shown to effectively cover an average of 96% of the test circuits. LURU was tested with the ISCAS ’85 suite of combinational benchmark circuits and compared with the mapping algorithms FlowMap and CutMap. The area requirement of LURU’s mapping is, on average, 20% less than FlowMap or CutMap. The asymptotic runtime complexity of LURU is shown to be better than that of both FlowMap and CutMap. [Copyright &y& Elsevier]

The primacy of memristors for the realization of the synaptic circuit makes this element a promising component for implementing Artificial Neural Networks (ANN). However, integrating memristors with other ANN components is still an open area of research. Therefore, a circuit-level hybrid CMOS/Memristor architecture for implementing Bidirectional Associative Memory (BAM) is proposed in this paper. A passive bi-directional pre-differentiation crossbar architecture has been utilized and applied for the realization of synaptic weights. A compact, low voltage CMOS neuron that consumes a low amount of power is also designed. The noise tolerance of the proposed hardware is evaluated for typical networks with different sizes and a number of stored patterns. It is demonstrated that the hardware pattern retrieval rate is similar to its software-based counterpart. The influence of memristor non-idealities on BAM is also investigated for the first time, and a practical method has been introduced to deal with this issue. In comparison to the available circuit-level hardware implementation of memristive associative memories, the proposed circuit consumes significantly less power and retrieves the stored patterns notably faster. [ABSTRACT FROM AUTHOR]