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In this paper, a very low spur 5.9-GHz integer-N frequency synthesizer designed for a Cellular Vehicle-to-Everything (C-V2X) receiver is presented. The PLL is referenced to a 10-MHz crystal oscillator and the design is implemented in a 65-nm CMOS process. The output of the synthesizer has differential quadrature topology and provides the local oscillator signal to a downconverter mixer of C-V2X receiver. Post-layout simulations show that the reference spurs are better than −88 dBc through loop sampling technique which was implemented in a 11.8-GHz VCO design for the first time to the best of our knowledge. The best spur level without the loop sampling technique applied is limited to −55 dBc. Using the loop sampling technique provides a spur reduction of 33 dB which is a significant improvement at this frequency. Based on post-layout simulations, the design has a phase noise of −97/−99/−114 dBc for 10 kHz/100 kHz/1 MHz frequency offsets, respectively, which presents competitive numbers with the designs in the literature. The design has 1.2-V nominal supply voltage for the analog and digital blocks. The total power dissipation of the synthesizer core is 6 mW from a 1.2-V supply while the output buffers driving a 100-fF load consumes 18 mW. [ABSTRACT FROM AUTHOR]

An 11.8-GHz low-power, low phase noise, 65-nm CMOS LC-VCO for V2X communication standards is presented in this work. To achieve low-phase noise performance to fulfill the 5G NR C-V2X standards, several adjustments are made to the conventional LC-VCO topologies. These adjustments are briefly explained in this work. Presented VCO consumes 3.046 mA current from a 1.2-V power supply. It has − 116.13 dBc/Hz phase noise at 1 MHz offset and tuning range between 11.64 GHz and 11.94 GHz. A frequency divider circuit is designed and implemented to the presented VCO to satisfy the frequency spectrum of V2X radio access technologies. To the best of authors' knowledge, this work is the first VCO implemented at 11.8 GHz in a 65-nm CMOS process with the reported phase noise number for 5G NR C-V2X applications. [ABSTRACT FROM AUTHOR]

A gain and bandwidth tunable active-RC multiple-feedback (MFB) fourth-order low-pass filter is presented, which exhibits four different bandwidths of 10, 20, 30 and 40 MHz and four different gain settings of 0, 4, 8 and 12 dB to meet the requirements of the cellular vehicle-to-everything (C-V2X) standards. The filter uses the cascade of two biquad MFB cells. Gain and bandwidth programmability is achieved by using programmable capacitor and resistor arrays. A logic block is implemented in the filter to adjust the gain transfer function for every tuning option. Also, two-stage miller op-amp topology is chosen to implement biquad MFB cells for minimum complexity and maximum efficiency in low voltage operation. The filter is designed in 65-nm CMOS technology and occupies a 0.181 mm2 area and it totally consumes 13.41 mW from the 1.2 V supply voltage. To the best of the author's knowledge, this work is the first CMOS baseband filter design that includes both gain and bandwidth programmability implemented for C-V2X applications. [ABSTRACT FROM AUTHOR]

Estimation of signal power levels at the output of integrated receiver building blocks is a vital function as the block voltage or power gains are set based on sensed power levels to maintain constant levels at block outputs in the receiver chain. RF and IF level real-time gain settings are determined with Automatic Gain Control (AGC) loops. AGC loop circuit topologies are usually based on analog detection circuits. These analog power detection circuits are based on techniques such as envelope detection, and logarithmic amplification usually accompanied by severe accuracy issues such as Process, Voltage and Temperature (PVT) spreads preventing correct gain adjustments. Adopting a dominantly digital approach to detect the signal power would ensure a significant reduction in PVT spreads. This work presents a review of the subsampling digital power estimation to create low power digital power estimations alternative to analog methods. The simulations of the method are applied to an AM and a 64-QAM signal. Simulation results show that the power estimation error is within the acceptable level of ± 1 dB. [ABSTRACT FROM AUTHOR]

In this paper, an ultra-wideband fully differential two-stage telescopic 65-nm CMOS op-amp is presented, which uses low-voltage design techniques such as level shifter circuits and low-voltage cascode current mirrors. The designed op-amp consists of two stages. While the telescopic first stage provides high speed and low swing, the second stage provides high gain and large swing. Common-mode feedback circuits (CMFB), which contain five transistors OTA and sensing resistors, are used to set the first-stage output to a known value. The designed two-stage telescopic operational amplifier has 41.04 dB lower frequency gain, 1.81 GHz gain-bandwidth product (GBW) and 51.9∘ phase margin under 5 pF load capacitance. The design consumes a total current of 11.9 mA from a 1.2-V supply voltage. Presented fully differential two-stage telescopic op-amp by using low-voltage design techniques is suitable for active filter in vehicle-to-everything (V2X) applications with 120 μ m × 5 5 μ m layout area. [ABSTRACT FROM AUTHOR]

This study describes a new method to compensate bias heating effects for microbolometer readout circuits using a finely adjustable CMOS resistance as a reference. The proposed self calibrated cooler-less structure dynamically modifies CMOS resistance during integration time. This compensation structure also includes a feedback loop, which forces the oscillators to work in the linear region. The proposed self calibration circuit is designed and simulated using a 65-nm process node, and achieves 40 mK NETD (Noise Equivalent Temperature Difference) value for one percent resistance non-uniformity of pixel resistance values across one row. The layout area of this circuit occupies approximately one third of the layout area used by classical readout circuits. The circuit dissipates one third of power compared with classical microbolometer readout approaches. • Automatic Self-Heating Calibration Method. • Row-based Self-heating calibration to eliminate substrate temperature drift of classical microbolometer readout. • Low Supply Voltage and Low Area Microbolometer Readout Architecture. • VCO-based microbolometer Readout Circuit. [ABSTRACT FROM AUTHOR]

An ultra-wide bandwidth fully differential two-stage 65 nm CMOS operational amplifier (Opamp) is presented, which uses a novel bandwidth extension technique called "pole duplication". This technique is based on relocating the dominant pole with the same location with a non-dominant pole and adjusting 3-dB frequency and stability with a compensation network. Simulation results show that the proposed Opamp has 103 MHz 3-dB bandwidth with a 2 pF load capacitor. It consumes 9 mA current from 1.2-V supply. Transition frequency of 2.4 GHz and a gain of 29 dB is accomplished. A 2 pF load capacitance can be driven at a phase margin of 5 5 ∘ . The suggested pole duplication technique is used to achieve higher 3-dB cut-off frequencies by adjusting the load capacitor. Fully differential two-stage Opamp is presented, which uses a novel bandwidth extension technique, is suitable for SoC active filter applications with 40 μ m × 6 0 μ m layout area and ultra-wide 3-dB bandwidth. [ABSTRACT FROM AUTHOR]

In this paper, an RF front-end (RFFE) circuit consisting of a low noise amplifier (LNA) and a down-conversion mixer for vehicle-to-everything (V2X) applications in a 65-nm CMOS process is presented. V2X standard has a carrier frequency of 5.9 GHz with 10 and 20 MHz bandwidth options. The LNA topology of the RFFE is based on an inductively degenerated cascode common source differential approach. The mixer design uses a double-balanced topology with a charge injection method to enhance the linearity and noise figure performance. The RFFE design shows a single sideband integrated noise figure of 4.47 dB with a total conversion gain of 28 dB. The IIP3 is obtained as − 17 dBm with charge injection in the mixer which is an improvement of 5 dB as compared to no charge injection. The design consumes a total current of 10.24 mA from a 1.2-V supply. This work is the first CMOS RFFE design implemented for V2X applications. [ABSTRACT FROM AUTHOR]

In this paper, we present a novel, almost-digital approach for bolometer readout circuits to overcome the area and power dissipation bottlenecks of analog-based classical microbolometer circuits. A current-controlled oscillator (CCO)-based analog-to-digital converter (ADC) is utilized instead of a capacitive transimpedance amplifier (CTIA) in the classical readout circuits. This approach, which has not been reported before, both produces the required gain in the bolometer input circuit and directly digitizes the bolometer signal. With the proposed architecture, the need for large capacitances (of the order of 10–15 pF for each column) at which the current is accumulated in the bolometer circuits and the voltage headroom limitation of classical microbolometer circuits are eliminated. Therefore, the proposed architecture permits to design readout circuits with reduced pixel pitch and lower power supply, both of which in turn lead to higher-resolution Focal Plane Arrays (FPAs) with lower power dissipation. The new architecture is modeled and simulated using a 180-nm CMOS process for sensitivity, noise performance, and power dissipation. Unlike the 3.3-V power supply usage of classical readout circuits, the proposed design utilizes 1.2-V analog and 0.9-V digital supply voltages with a power dissipation of almost half of the classical approach. [ABSTRACT FROM AUTHOR]

In this paper, a fast automatic cutoff frequency calibrating, CMOS lowpass filter with linear-in-dB tunable gain and constant in-band group delay is presented. The automatic frequency tuning (AFT) circuit can successfully tune the cutoff frequency to 120 MHz with less than 4.7% error. In-band group delay variation is handled using a capacitor process variation detection circuit (CPVD), and the overall tuning time is less than 700 ns. The design is done using STM PD-SOI 130 nm CMOS process, and the supply voltage is 1.2 V with a total power consumption of 21.7 mW. The overall filter provides a programmable linear-in-dB gain of 0.5 dB to 17.6 dB range with a cutoff tuning range of 80 to 180 MHz. The in-band group delay variation is below 500 ps with an adjacent channel ratio (ACR) of 85 dB. The spurious free dynamic range (SFDR) is over 66.6 dBc. The active area of the filter with tuning is 0.171 mm 2. [ABSTRACT FROM AUTHOR]

This article indicates a thus far unexplored area of applied research and development to the application and system engineers and researchers from broad engineering backgrounds. Results of a study are presented for measurement of calibrated Radar Cross Section (RCS) of a 9‐mm bullet (projectile) model by using a commercial‐of‐the‐shelf (COTS) millimeter wave Frequency Modulated Continuous Wave (FMCW) radar system operating in 77 to 81 GHz frequency range. The calibrated RCS variation against the aspect angle is measured experimentally, analyzed, and compared with the simulation results which shows fair matching between the two. The opportunities and challenges attached with the use of such COTS systems for development of Hostile Fire Indication (HFI) systems are discussed. This bullet type and this mmwave frequency has not been thus far studied and reported in literature. This may motivate interested individuals/entities to try to measure (at acceptable accuracy before anechoic chamber measurements) RCS of similar low‐size objects by using such low‐cost COTS platforms. [ABSTRACT FROM AUTHOR]

An embedded CMOS digital dual tuner for DOCSIS 3.0 and set-top box applications is presented. The dual tuner down-converts a total of ten 6 MHz Annex B channels or eight 8 MHz Annex A channels, for a maximum data rate of 320 Mb/s in Annex B and 400 Mb/s in Annex A mode. The dual tuner exceeds all the stringent SCTE 40 specifications over the 48-1004 MHz bandwidth, without using any external components or SAW filters. Enabling technologies are a harmonic rejection front-end, a low-noise highfrequency resolution PLL, and digital image rejection. To our knowledge this is the first reported multichannel broadband tuner embedded in a DOCSIS 3.0 System on a chip implemented in 65 nm pure digital CMOS technology. [ABSTRACT FROM AUTHOR]