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In evolutionary biology and ecology, ontological and epistemological perspectives based on the replicator and the interactor have become the background that makes it possible to transcend traditional biological levels of organization and to achieve a unified view of evolution in which replication and interaction are fundamental operating processes. Using the transactional perspective proposed originally by John Dewey and Arthur Fisher Bentley, a new ontological and methodological category is proposed here: the transactor. The transactional perspective, based on the concept of the transactor, bridges the dichotomy between organisms and environment that characterizes the interactional perspective on evolution and provides epistemological support for the emergentist, systemic view of evolutionary and developmental processes. [ABSTRACT FROM AUTHOR]

Abstract: This paper proposes a hardware–software (HW-SW) co-simulation framework that provides a unified system-level power estimation platform for analyzing efficiently both the total power consumption of the target SoC and the power profiles of its individual components. The proposed approach employs the trace-based technique that reflects the real-time behavior of the target SoC by applying various operation scenarios to the high-level model of target SoC. The trace data together with corresponding look-up table (LUT) is utilized for the power analysis. The trace data is also used to reduce the number of input vectors required to analyze the power consumption of large H/W designs through the trade-offs between the signal probability in the trace results and its effect on the power consumption. The effect of cache miss on power, occurring in the S/W program execution, is also considered in the proposed framework. The performance of the proposed approach was evaluated through the case study using the SoC design example of IEEE 802.11a wireless LAN modem. The case study illustrated that, by providing fast and accurate power analysis results, the proposed approach can enable SoC designers to manage the power consumption effectively through the reconstruction of the target SoC. The proposed framework maps all hardware IPs into FPGA. The trace based approach gets input vectors at transactor of the each IP and gets power consumption indexing a LUT. This hardware oriented technique reports the power estimation result faster than the conventional ones doing it at S/W level. [Copyright &y& Elsevier]

Transaction-level models promise to be the basis of the verification environment for the whole design process. Realizing this promise requires connecting transaction-level and register-transfer-level (RTL) blocks through a transactor, which translates back and forth between RTL signal-based communication and transaction-level function-call-based communication. Each transactor is associated with a pair of interfaces, one at RTL and one at transaction level. Typically, however, a pair of interfaces is associated with more than one transactor, each assuming a different role in the verification process. In this paper, we propose a methodology in which both the interfaces and their relation are captured by a single formal specification. By using the specification, we show how the code for all the transactors associated with a pair of interfaces can be automatically generated. Our synthesis algorithm avoids the state-explosion problems associated with certain features of the specification formalism, at the expense of a more sophisticated simulation algorithm. We describe three different code-generation techniques targeted at different verification languages: 1) C++; 2) Verilog; and 3) the combination of the two that is compliant with the Standard Co-Emulation Modeling Interface protocol. In addition, we present several case studies demonstrating that automatically generated transactors can indeed replace handcrafted ones in realistic designs. [ABSTRACT FROM AUTHOR]