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In this article, the high-k gate dielectric effect on the operation of complementary metal oxide semiconductor (CMOS) inverter build using conventional (CL) double-gate (DG) metal oxide semiconductor field effect transistor (MOSFET) and junctionless (JL) double-gate (DG) MOSFET has been explored. It is found that the improvement in inverter performance is more pronounced in CL-DG-MOSFET based CMOS inverter in comparison to JL-DG-MOSFET based CMOS inverter when SiO2 is replaced by the high-k dielectric at gate oxide. The improvement in low noise margin (ΔNML), high noise margin (ΔNMH), gain (ΔA) & propagation delay (ΔPd ) is 3.19%, 1.64%, 5.2% & 0.9% respectively when SiO2 is replaced by TiO2 at gate oxide in case of CL-DG-MOSFET based CMOS inverter whereas it is 1.96%, 1.24%, 3.4% & 1.71% respectively in case of JLDG-MOSFET based CMOS inverter. Consequently, the utilization of high-k dielectric as gate oxide is more advantageous in CL-DG-MOSFET devices for improved stability and gain of CMOS inverter. [ABSTRACT FROM AUTHOR]

This work investigates the channel thickness dependency of high-k gate dielectric-based complementary metal-oxide-semiconductor (CMOS) inverter circuit built using a conventional double-gate metal gate oxide semiconductor field-effect transistor (DG-MOSFET). It is espied that the use of high-k dielectric as a gate oxide in n/p DG-MOSFET based CMOS inverter results in a high noise margin as well as gain. It is also found that delay performance of the inverter circuit also gets upgraded slightly by using high-k gate dielectric materials. Further, it is observed that the scaling down of channel thickness (TSi) improves the noise margin (NM), and gain (A) at the cost of propagation delay (Pd ). Moreover, it is also observed that the changes in noise margin (ΔNM = NM(K=40) – NM(K=3.9)), propagation delay (ΔPd = Pd (K=40) – Pd (K=3.9)), and gain (ΔA = A(K=40) – A(K=3.9)) gets hinder at lower TSi. Therefore, it is apposite to look at lower channel thickness (~6 nm) while designing high-k gate dielectric-based DG-MOSFET for CMOS inverter cell. [ABSTRACT FROM AUTHOR]

In this work, gate-stack based junctionless Si-nanotube (JLSiNT) FET is studied to investigate the effect of high- K gate dielectric material in-conjunction with interfacial layer thickness (T I ) and outer gate length (L g ) on analog/RF figures of merit (FOM) of the device. With the use of high- K gate dielectric intrinsic dc gain (A V ), cut-off frequency (f T ), and maximum oscillation frequency (f MAX ) degrades. It is observed that the degradation in analog/RF performance when high- K gate dielectrics are used, can be improved by taking higher T I . Furthermore, it is also observed that by using optimal T I (0.7 nm), the variation in ΔA V (A V( K =3.9) - A V( K =40) ), Δf T (f T( K =3.9) – f T( K =40) ), and Δf MAX (f MAX( K =3.9) – f MAX( K =40) ) FOMs are almost invariant when outer gate length (L g ) is scaled down from 30 nm to 15 nm. Therefore, it is pertinent to consider higher interfacial layer thickness (~0.7 nm) and lower outer gate length (~ 15 nm) while designing gate-stack based JLSiNT-FET for analog/RF applications. [ABSTRACT FROM AUTHOR]

This paper for the first time investigates the effect of temperature variation on analog/RF performance of SiO 2 as well as high- K gate dielectric based junctionless silicon nanotube FET (JL-SiNTFET). It is observed that the change in temperature does not variate the analog/RF performance of junctionless silicon nanotube FET by substantial amount. By increasing the temperature from 77 K to 400 K, the deterioration in intrinsic dc gain (A V ) is marginal that is only ∼3 dB. Furthermore, the variation in cut-off frequency (f T ), maximum oscillation frequency (f MAX ), and gain-frequency product (GFP) with temperature is also minimal in JLSiNT-FET. More so, the same trend is observed even at scaled gate length (L g  = 15 nm). Furthermore, we have observed that the use of high- K gate dielectric deteriorates the analog/RF performance of JLSiNT-FET. However, the use of high- K gate dielectric negligibly changes the effect of temperature variation on analog/RF performance of JLSINT-FET device. [ABSTRACT FROM AUTHOR]

This paper investigates the performance of 6 T SRAM cell using high- K gate dielectric based junctionless silicon nanotube FET (JLSiNTFET). It is observed that the use of high- K gate dielectric enhances the delay performance of the JLSiNTFET based 6 T SRAM cell. Read access time (RAT) and write access time (WAT) improves by ∼18% and ∼20% when TiO 2 is used as gate dielectric instead of SiO 2 . The hold, read, and write SNMs (static noise margin) of the 6 T SRAM cell also improves marginally by the use of high- K gate dielectric. Furthermore, it is also observed that the improvement in hold SNM (HSNM), read SNM (RSNM), and write SNM (WSNM) can be boosted by using higher interfacial layer thickness (T I ). However, the improvement in read access times (RAT) & write access time (WAT) degrades at higher T I . Thus, high- K gate dielectrics with high interfacial layer thickness are more suitable for JLSiNT-FET based 6 T SRAM cell. [ABSTRACT FROM AUTHOR]

In this paper, the effect of channel parameters like channel thickness (T Si ) and channel length (L g ) on the analog/RF performance of high- K gate-stack based junctionless Trigate-FinFET (JLT-FinFET) have been studied using TCAD mixed-mode Sentaurus device simulator. It is observed that use of high- K gate dielectric deteriorates the analog/RF performance of the gate-stack based JLT-FinFET. The variation of change in analog/RF FOMs (ΔFOM = FOM K =3.9 - FOM K =40 ) with respect to channel parameters have been focused throughout this study. It is observed that the deterioration in intrinsic dc gain (ΔA V = (A V( K =3.9) - A V( K =40) )) with high- K gate dielectrics aggravates with scaling down of T Si (from 2.31 dB at T Si = 12 nm to 5.2 dB at T Si = 6 nm) but increases marginally with scaling down of L g (ΔA V = 7.6 dB at L g = 30 nm and ΔA V = 8.7 dB at L g = 15 nm). However, the deterioration in maximum oscillation frequency (Δf MAX ) and cut-off frequency (Δf T ) are almost negligible. Moreover, it is also observed that the deterioration in analog/RF FOMs due to high- K gate dielectrics can be reduced by upscaling of interfacial layer thickness (T I ). Consequently, higher T I value can be convenient in designing of high -K gate-stack based junctionless Trigate-FinFET at lower T Si for analog/RF applications. [ABSTRACT FROM AUTHOR]

This paper investigates the analog/RF performance of inner gate engineered junctionless silicon nanotube (JLSiNT) FETs. We demonstrate that the RF performance of symmetric drain/source DS-JLSiNT-FETs (inner gate extended from one end of nanotube to other end covering both drain and source region) gets improved when the inner gate of nanotube (NT) covers only either drain and channel regions (D-JLSiNT-FETs) or source and channel regions (S-JLSiNT-FETs) because of reduced total gate capacitance. The improvement in cut-off frequency (f T ) in D-JLSiNT-FETs is ∼45% whereas in S-JLSiNT-FETs is ∼23% as compare to DS-JLSiNT-FETs. However, the percentage improvement in maximum oscillation frequency (f MAX ) is more in S-JLSiNT-FETs. Furthermore, due to partial covering of inner gate, the gate electrostatic integrity ( EI ) is reduced resulting in degraded intrinsic gain (A V ). However, the deterioration in A V is almost minimal (∼0.4 dB) for D-JLSiNT-FETs as compared to DS-JLSiNT-FETs but the deterioration in A V is aggravated to ∼22 dB for S-JLSiNT-FETs. The up scaling of Source/Drain extension length improves the performance of D-JLSiNT-FETs but degrade the performance of S-JLSiNT-FETs when compared to DS-JLSiNT-FETs. The improvement in f T and f MAX in D-JLSiNT-FETs as well as in S-JLSiNT-FETs are pronounced with outer gate length scaling when compared to DS-JLSiNT-FETs. [ABSTRACT FROM AUTHOR]

In this paper, the effect of fringe induced barrier lowering (FIBL) in-conjunction with channel parameters that includes channel thickness (T Si ), channel length (L g ) and lateral straggle ( σ L ) on analog and RF performance of FinFET, have been studied using TCAD mixed-mode Sentaurus device simulator. We focused on the variation in analog (intrinsic dc gain) and RF (cut-off frequency) figure of merit (FOM) of high- K gate dielectric based FinFET with respect to channel parameters. It is observed that the variation in intrinsic dc gain (ΔA V ) aggravates with T Si scaling. We also observe a mixed response to the ΔA V with respect to variation in L g and σ L , where ΔA V follows an inverse parabolic behavior peaking at an intermediate value of L g and σ L . Variation in cut-off frequency (Δf T ) on the other hand, is negligible (slightly increases with T Si and decreases with L g and σ L ). These properties of channel parameters can be handy in designing of high -K gate dielectric based FinFET for analog circuits. [ABSTRACT FROM AUTHOR]

This manuscript for the first time investigates the effect of Dual Metal on Gate Junctionless Nanosheet FET (DMG-JL-NSFET) for analog/RF applications. The entire analysis is performed for gate length (L g) = 16 nm at 10μA/μm to focus the weak/moderate inversion region of operation. The results show a whooping amount of reduction in terms of output conductance (g ds) (∼88.8%) due to the screening effect thereby enhancing the intrinsic gain (A V) (∼28.97%) of the DMG-JL-NSFET as compared to SMG-JL-NSFET. It is also found that the cut-off frequency (f T) and maximum oscillation frequency (f MAX) are increased by an amount of ∼11.82% and ∼2.91% respectively for DMG-JL-NSFET. Furthermore, it is elucidated that increasing the metal gate work function work difference (ΔW = φ ms -φ md) reduces the analog/RF performance of the DMG-JL-NSFET. The analysis revealed that increasing the ΔW from 0.3eV to 0.7eV deteriorates A V , f T , f MAX by an amount of ∼17.35%, ∼19.21%, and ∼37.57% respectively. Moreover, the implementation of HfO 2 as high-k gate dielectric as a replacement for SiO 2 degrades the analog/RF efficiency of DMG-JL-NSFET. Moreover, the DMG-JL-NSFET has provided a greater f T (∼224 GHz)/f MAX (∼342 GHz) indicating a promising candidature for future beyond 5G (B5G) applications. • First time investigates the effect of Dual Metal on Gate Junctionless Nanosheet FET (DMG-JL-NSFET) for analog/RF applications. • The entire analysis is performed for gate length (L g) = 16 nm at 10μA/μm to focus the weak/moderate inversion region of operation. • A whooping amount of reduction in terms of output conductance (g ds) (∼88.8%) due to the screening effect thereby enhancing the intrinsic gain (A V) (∼28.97%) of the DMG-JL-NSFET as compared to SMG-JL-NSFET. • The implementation of HfO 2 as high-k gate dielectric as a replacement for SiO 2 degrades the analog/RF performance of DMG-JL-NSFET. • DMG-JL-NSFET has provided a greater f T (∼224 GHz)/f MAX (∼342 GHz) indicating a promising candidature for future beyond 5G (B5G) applications. [ABSTRACT FROM AUTHOR]

We live in a digital world surrounded by digital content in the form of images, videos, and much more which consume extensive power. With the extensive use of digital content in portable gadgets power consumption has been critical issue to act upon. The multiplier is the core component used in image processors and digital signal processors and by altering the properties of the multiplier system provides superior performance. In this work, we analyse the combined effect of the Self-Bias Transistor (SBT) Technique and Vedic multiplication algorithm on a multiplier unit realised using reduced transistor technique on conventional adders and CMOS array Multiplier units. Simulation results display the 76.5%, 80.15% and 84.21% drop in power consumption of 4-bit, 8-bit and 16-bit SBT based Vedic multiplier at 45 nm technology node respectively. The effectiveness of the proposed technique is also presented at 100 nm and 65 nm technology nodes. Further, the effect of the SBT-based Vedic multiplier on the delay and power-delay product is explored at 100 nm, 65 nm and 45 nm technology. It is found that SBT-based multipliers are power efficient on Gate Diffusion Input-based multipliers [ABSTRACT FROM AUTHOR]

Power consumption is the major concern for conventional CMOS based integrated circuit and systems. Since there is a scope of lowering supply voltage with steep-subthreshold swing field effect transistor (FET) devices, it has been advocated as a suitable candidate for future highly energy-efficient circuits and systems. Among all the developed and proposed low power FET devices, that possess subthreshold swing (SS) lesser than 60 mV/decade, the negative-capacitance FETs (NCFETs) have gained the major attention of scientific and academic communities. The concept of negative capacitance (NC) in FET is basically belongs to the amplify the internal potential without modification of transport phenomena. With this capability, the NCFET have achieved similar switching at lower supply voltage, V D D as compared to conventional MOSFETs. Property of achieving similar on-current (I O N) lower off-current (I O F F) at lower supply voltage indicates that NCFETs help to reduce the power consumption and switching voltage. This can be achieved by slight modification of conventional CMOS devices by adding thin layer of ferroelectric (FE) layer in gate stack. This slight modification in conventional MOSFET is for the NC, which is a special feature of FE materials. FE materials having nonlinear dielectric behavior. This material has preexisting, which is switched in reverse direction when an external electric field is applied. In this paper, a detailed review of NCFET device has discussed and also compared with the Tunnel FET (TFET) and conventional MOSFET. [ABSTRACT FROM AUTHOR]

This work proposes a mathematical delay models for global VLSI interconnects using normalized asymptotic value of characteristic impedance of RLC interconnected line. In the proposed Model (R 0 C 0) the delay of RLC interconnects line is formulated by incorporating the line inductance in terms of effective impedance. The earlier simple RC interconnect models results in a significant error in delay estimation in long interconnects. Due to this analogy the non-ideal effect of inductive behaviour at high frequencies and scaled technologies such as ringing, spikes overshoot and undershoot can be suppressed. The dominance of inductance effect is optimized by Simulative Sweep Analysis Techniques (SSAT). Accuracy is verified by analytical and SPICE simulation results. Step response analysis of the proposed model is validated with the existing literature and found to be superior. Using this approach the results for both the signaling technique i.e. voltage and current mode signaling are found in close agreement between analytical and simulation for long interconnect lines. [ABSTRACT FROM AUTHOR]

• The temperature sensitivity on analog/RF FOMs of JL-SiNT-FET has been checked. • The temperature drop improves the analog/RF FOMs of all the configurations of JL-SiNT-FET by substantial amount. • ΔF = F T=100 - F T=400 , where F is the analog/RF FOMs is almost same in all the configurations. • The D-JL-SiNT-FET configuration is best among all three configurations at all temperatures. This paper explores the temperature sensitivity of Inner-gate engineered junctionless silicon nanotube FET (JL-SiNT-FET) on analog/RF performance. It is found that the reduction in the operating temperature from 400 K to 100 K improves the various analog/RF figure of merits (FOMs) of all the three configurations (DS-JL-SiNT-FET, D-JL-SiNT-FET, and S-JL-SiNT-FET) of JL-SiNT-FET by considerable expanse. The improvement in intrinsic dc gain (A V) is found to be ~1.8 dB, 2.2 dB, and 1.6 dB respectively for DS-JL-SiNT-FET, D-JL-SiNT-FET, and S-JL-SiNT-FET when the working temperature is reduced from 400 K to 100 K. Additionally, the improvement in cut-off frequency (f T), maximum oscillation frequency (f MAX), and gain-frequency product (GFP) caused by temperature variation are correspondingly significant in all the three configurations of JLSiNT-FET. It is also observed that the improvement (ΔF = F T=100 - F T=400 , where F is the analog/RF FOM) caused by the reduction in temperature is almost similar in all the configurations. [ABSTRACT FROM AUTHOR]

The voyage of semiconductor industry to decrease the size of transistors to achieve superior device performance seems to near its physical dimensional limitations. The quest is on to explore emerging material systems that offer dimensional scaling to match the silicon- based technologies. The discovery of atomic flat two-dimensional materials has opened up a completely new avenue to fabricate transistors at sub-10 nanometer level which has the potential to compete with modern silicon-based semiconductor devices. Molybdenum disulfide (MoS2) is a two-dimensional layered material with novel semiconducting properties at atomic level seems like a promising candidate that can possibly meet the expectation of Moore's law. This review discusses the various ' fabrication challenges ' in making MoS2 based electronic devices from start to finish. The review outlines the intricate challenges of substrate selection and various synthesis methods of mono layer and few-layer MoS2. The review focuses on the various techniques and methods to minimize interface defect density at substrate/MoS2 interface for optimum MoS2-based device performance. The tunable band-gap of MoS2 with varying thickness presents a unique opportunity for contact engineering to mitigate the contact resistance issue using different elemental metals. In this work, we present a comprehensive overview of different types of contact materials with myriad geometries that show a profound impact on device performance. The choice of different insulating/dielectric gate oxides on MoS2 in co-planar and vertical geometry is critically reviewed and the physical feasibility of the same is discussed. The experimental constraints of different encapsulation techniques on MoS2 and its effect on structural and electronic properties are extensively discussed. [ABSTRACT FROM AUTHOR]

In the present-day scenario of low-power electronics, there is a steady and increasing need for an adequate device that can counteract the power dissipation issue due to the consistent scaling of device dimensions. For this purpose, the evolution of low subthreshold swing (SS) based devices, especially with the negative capacitance (NC) techniques, has presented a well-favored solution. The NC of ferroelectrics (FE) materials could be widely utilized to provide the gate voltage (V G) amplification under specific conditions to boost the performance of the MOS device, by addressing the ultimate fundamental limitation of Boltzmann Tyranny and offering the SS much lower than 60 m V / d e c. Along with the advent of this state-of-art NC technology, tunnel field-effect transistor (TFET) also emerges for accomplishing low SS and becomes one of the promising techniques for low-power applications. Incorporating these two principles (NC and tunneling) into a single device architecture enables the super-steep SS and remarkably low OFF current (I O F F). This cutting-edge combination, negative capacitance tunnel FET (NC-TFET) device has opened up the possibility of an ultra-low-power and high-performance device. This review paper mainly focuses on the theoretical background and recent progress in the field of NC-TFET with abundant quantum-mechanical models and various perspectives such as transistor perspective, analog circuit perspective, and future road map perspective. [ABSTRACT FROM AUTHOR]

In this paper, we proposed a side-contact reduced graphene nano-ribbon (SC-RGNR) interconnect model to reduce crosstalk noise and delay for next generation high performance integrated circuit (IC) design. The SC-RGNR interconnect structure is designed with latest 11 nm ITRS (International Technological Road Map for Semiconductor) technology node. A comparative crosstalk noise, delay and power consumption analysis has been performed with side-contact graphene nano-ribbon (SC-GNR) interconnect model. The SC-RGNR and SC-GNR interconnect both model parameters are applied in standard (STD) bus and staggered (STAGG) bus model with different interconnect lengths (10 μm–500 μm) and four standard mean free paths (MFP) (i.e., 300 nm, 419 nm, 1000 nm and 1200 nm) values. Five different switching conditions (i.e., SP1 to SP5) are applied on tri-interconnect driver-load circuit to check the performance of SC-RGNR and SC-GNR interconnect in-terms of crosstalk noise and delay. In our analysis, it is shown that, the higher MFP based SC-RGNR interconnect shows less dynamic delay compared with SC-GNR interconnect for both STD and STAGG interconnect model with worst-case switching condition (SP5) and best-case switching condition (SP2). For STD interconnect model with worst-case switching condition (SP5) the dynamic delay of SC-RGNR interconnect is ∼1.33–2.62 × lesser than SC-GNR interconnect. Similarly, for STAGG model with worst-case switching condition (SP5) the dynamic delay of SC-RGNR interconnect is ∼1.26–2.16 × lesser than SC-GNR interconnect. Although, the STAGG interconnect model performs ∼1.5–2 × faster than STD interconnect model in terms of delay. In our analysis, it is also observed that, the output noise peak is ∼2.91–17.5 × less in SC-RGNR compared with SC-GNR at 500 μm interconnect length and higher MFP. Our analysis also shows that, the switching power consumption in SC-RGNR is ∼1.66–2.2 × less than SC-GNR for both STD and STAGG model for both best and worst-case switching condition (SP2 and SP5). [ABSTRACT FROM AUTHOR]

• Cylindrical gate GAA MOSFET is designed and simulated to get improved electrostatic controllability. • A temperature variation between 70 K and 800 K has been taken and the corresponding effect on device performance is observed. • The transfer characteristics and output characteristics were observed in order to get perfect switching ratio. • Further the threshold voltage is extracted using transconductance method and the effect due to temperature variation is analyzed. A 60 nm gate length, n-type Gate all around (GAA) metal oxide semiconductor field effect transistor (MOSFET) is simulated at different temperature. The temperature dependent electrical characteristics for various temperature are investigated extensively. The improved gate controllability in lower technology node as well as immunity against short channel effects are thoroughly examined. This paper also includes the analog performance analysis of GAA MOSFET along with the DC performances. The performance matrix of the device for different temperature ranging from 70 K to 800 K were illustrated clearly. Results exhibit that the drain current, transconductance, device gain and transconductance to drain current ratio (gm/Ids) improves when temperature is decreased. [ABSTRACT FROM AUTHOR]

Incessant downscaling of feature size of multi-gate devices such as FinFETs and gate-all-around (GAA) nanowire (NW)-FETs leads to unadorned effects like short channel effects (SCEs) and self-heating effects (SHEs) which limits their performance and causes reliability issues. FinFET technology has resulted in a remarkable performance up to a feature size of 7 nm. The research community is expecting that GAA NW-FETs will take over FinFET technology from 7 nm to 5 nm. However, further shrinking of feature size to 3 nm will impose severe challenges to the performance of these aforesaid multi-gate devices. Subsequently, the electron device designer community needs to look for alternative device designs like nanosheet FETs (NS-FETs) to overcome the limitations of the FinFET and GAA NW-FETs technologies. The driving force behind the emergence of these NS-FETs is their ability to scale down even below a feature size of 5 nm with negligible short channel effects. Therefore, in this review article we have intensively investigated the NS-FETs in terms of impact of geometrical scaling, substrate material effects, parasitic channel effects, thermal effects, compatibility with different metal gates, and source/drain (S/D) metal depth effect. Consequently, it can be concluded that vertically stacked NS-FET is the most promising solution for future digital/analog integrated circuit applications due to their outstanding capability to keep Moore's Law alive. [ABSTRACT FROM AUTHOR]

In recent years, the significance of biosensors has increased rapidly due to the growing demand for rapid detection of various biomarkers with high selectivity and sensitivity. Among different biosensors, Graphene Field Effect Transistor (Gr-FET) based biosensors has emerged as a promising device and exhibited wide range of application prospects. Gr-FET biosensors are ideal for ultra-sensitive immunological diagnosis applications as it can sense surrounding changes on their surface with low noise. Recently Gr-FET based biosensors have gained profound research interest among scientific community because of its ability in detection of SARS-CoV-2 (corona virus-2). This review article highlights the sensing performance and characteristics of different Gr-FET biosensors like DNA sensor, RNA sensor, glucose sensor, lactose sensor, protein sensor, pH sensor, various bacteria and virus detecting sensors etc.This article also critically reviews the recent progress in Gr-FET based SARS- CoV-2 covid-19 virus detection bio-sensors. [ABSTRACT FROM AUTHOR]

In order to handle high power with good thermal stability at RF & microwave frequencies wider bandgap semiconductor based transistors are highly desirable and GaN & AlGaN channel HEMTs (High electron mobility transistors) have become most promising devices for RF power and switching electronic applications due to their unique features such as high 2DEG density, excellent breakdown field, good 2DEG mobility & saturation drift velocity and extremely low ON-resistance. GaN & AlGaN channel HEMTs are widely fabricated on SiC or sapphire wafers, but their low wafer size & high fabrication cost hinder the commercialization of these devices. In recent years, Si-wafers have emerged as a pathway for the commercialization of GaN & AlGaN channel HEMTs due to their large wafer size, low cost fabrication & capability to integrate GaN or AlGaN channel power HEMTs on advanced Si-technology. Therefore, in this article, we critically reviewed the issues that need to be addressed while transferring GaN or AlGaN channel HEMTs on Si-wafers. This article also highlights the popular architectures of GaN & AlGaN channel HEMTs on Si-wafers, techniques for enhancing their breakdown performance such as buffer layer engineering, drain contact technologies & surface passivation, challenges in fabrication and reliability issues such as irradiation & thermal degradations. [ABSTRACT FROM AUTHOR]

Hydrogen (H 2) has been widely used in H 2 fuelled vehicles, semiconductor fabrication, medical treatments, chemical industry and industrial aerospace applications. However, H 2 is a highly explosive gas (if H 2 concentration exceeds 4.65 vol% in air) and therefore, the risk is very high when it is used in applications. This increases the demand for the development of high performance H 2 sensors. The unique properties of AlGaN and GaN such as wide band gap, outstanding physical, chemical and thermal stability, optical transparency, environmental friendliness, low sensing response time, non-toxicity and surface sensitivity makes them one of the most promising material systems for the development of H 2 sensors. An ultra high sensitivity of 1.24 × 107 and an ultra low response time of 7 s and recovery time of 6 s have been reported for AlGaN/GaN Schottky Diode (SD) H 2 sensors. On the other hand, an outstanding sensitivity of 1.6 × 107 and an extremely low response time of 2.5 to 3 s have been reported for AlGaN/GaN HEMT (High Electron Mobility Transistor) H 2 sensors. Moreover, AlGaN/GaN heterostructure-based H 2 sensors can be operated over 800 °C temperature. This article critically reviews the structures, fabrication and factors influencing the sensing performance of AlGaN/GaN SD/HEMT H 2 sensors for future aerospace and industrial applications. [ABSTRACT FROM AUTHOR]