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Abstract: This paper gives some insights in the applications where PECVD nitrides can be introduced to replace the LPCVD layers and how the process parameters need to be varied to obtain the desired properties. Film properties like stress, hydrogen content, wet etch rate and deposition rate are reported. The nitrides are optimized for specific applications and examples on the influence of nitride properties on device performance are given. It is important to investigate that the advantage of the high film integrity of nitride layers used in the past is not lost due to the strong demand for developing new process schemes with low thermal budget layers. We show that PECVD films are a valid alternative for LPCVD and that the majority of the film properties satisfy the criteria to use PECVD films as contact-etch-stop layers, silicidation blocking films and spacer materials. [Copyright &y& Elsevier]

Abstract: This work presents a process to fabricate Bulk FinFETs with advancements in critical fabrication steps such as the shallow trench oxide recess and the adjustment of the fin height. These steps are accomplished with the adoption of Siconi™ Selective Material Removal (SMR™) in the fabrication flow. FinFETs obtained with this new integration scheme were tested in a co-fabrication process flow proposed to integrate planar CMOS and Bulk FinFETs on the same wafer. Morphological and electrical results indicate perfectly filled trenches, a better fin height control and a Bulk FinFET static performance similar to planar CMOS. The 20nm wide fins are fabricated using 193nm illumination lithography followed by a series of trimming steps during the trench etching, the filling and a fin re-oxidation during the steam densification of the trench filling oxide. Trench depth is 300nm and the electrically active fin height is 40nm. [Copyright &y& Elsevier]

Abstract: Thin (<4nm) Physical Vapor Deposited (PVD) Ru-10at.% Ta films were evaluated as diffusion barriers and seed enhancement layers for Cu metallization in sub 25nm trenches. The ratio of Ru/Ta on blanket wafers could be influenced by changing the process conditions. However, a difference in Ru/Ta ratio did not influence the thermal stability of the layers during High Temperature X-ray Diffraction (HT-XRD) measurements as all RuTa films exhibited good thermal properties since no Cu-silicide formation was observed for temperatures below 500°C. The RuTa films also passed an 85°C/85% relative humidity (RH) test of one week of storage in order to test the H2O barrier integrity of the films. Furthermore no difference was found when testing the O2 barrier integrity during 300s anneals at various temperatures between 250°C and 500°C. Good Cu fill of 20nm trenches (AR 4:1) patterned in oxide was achieved when combining the RuTa films with PVD Cu seed layers with thicknesses ranging from 7 to 20nm and Cu plating. When compared to a Ta(N)/Ta barrier, relatively high electrical yields (60–80%) were obtained for structures with CDs <30nm when combining RuTa films with PVD Cu seed layers as thin as 7nm (on field), hence evidencing the seed enhancement ability of these layers. [Copyright &y& Elsevier]

Abstract: In this paper we will highlight key integration issues that were encountered during the development of the 3D-stacked IC Through Silicon Via (TSV) module and present solutions to achieve a robust copper TSV. Electrical performance of the obtained TSV module is discussed based on a lumped RC model for 3D ring oscillators containing TSVs between bottom and top tiers. [Copyright &y& Elsevier]

The importance of interface quality in the single damascene integration process of LKD5109™ porous low-k films is investigated. A strong correlation is observed between chemical mechanical planarization (CMP) performance and LKD/cap layer interfacial fracture energies. The use of FF02™ as cap layer material (an on-purpose developed spin-on organic hard-mask) on LKD leads to superior interfacial adhesion and metal continuity yield as compared to the use of chemical vapour deposition SiC:H cap films. The adhesion quality of LKD/liner films appears less critical than LKD/cap layer adhesion as far as CMP performance is concerned. Electrical line-to-line performance is not always directly correlated with adhesion but rather, more generally speaking, with interface quality (i.e., presence of defects/dangling bonds or moisture). The introduction of surface pre-treatments to enhance interfacial adhesion leads to degradation in both leakage current and breakdown field behaviour because of damage induced at the interface. [Copyright &y& Elsevier]

Increasing the circuit density is driving the need for lower permittivity interlayer dielectrics (ILD) to reduce the capacitance between long parallel lines. JSR’s LKD-5109, an MSQ-based material, is one of such low-k materials for the 65-nm node. The feasibility of integrating LKD-5109 in a single inlaid structure has been investigated. Thermal stability, chemical compatibility to stripping agents and CMP slurries are verified. A single damascene structure incorporating a dual CVD hard mask has been attempted and electrical results have been evaluated. [Copyright &y& Elsevier]