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Cloud service providers employ virtualization technologies in order to deliver energy efficiency and optimize resource utilization in cloud datacenters. In this way, Virtual Machine (VM) consolidation is an efficient technique for reducing energy related costs and environmental concerns. This technique consists of placing as much as possible VMs on as less as possible Physical Machines (PM)s by means of live VM migration. However, VM consolidation approaches bring advantages, they cannot efficiently guarantee performance isolation of co-located VMs resulting in operational interference issues. Therefore, it is necessary to be aware of workload performance degradation issues during VMs consolidation in a datacenter. In this paper, we propose a novel joint profit and interference-aware scheduling scheme (PIAS) to efficiently consolidate VMs that host multi-tier application workloads in Infrastructure-as-a-Service (IaaS) cloud datacenter. The PIAS scheme considers profit and cost of power consumption, operational interference of VMs, resource utilization, and service level agreements (SLA)s as well as amount of transferred memory pages during live VM migration for consolidating VMs. In this regard, a stochastic dynamic programming is introduced to model the operational behavior of VM. Also, an optimization problem is introduced to maximize provider's profit and minimize the overall execution cost of application workloads. We simulate a series of experiments based on real workloads traces for different IaaS cloud datacenter configurations. The PIAS scheme on average provides better results than other competitors and the results demonstrate how our approach at least improves profit, energy efficiency, and service down time by 40%, 29%, and 35%, respectively. [ABSTRACT FROM AUTHOR]

A majority of traffic engineering techniques aims to minimize network congestion in SDN, but they commonly have considered some aspects of the flows and their demands for evaluating applications in SDN. This paper focuses on a scalable traffic engineering scheme for efficiently mapping traffic demands to paths in SDN datacenters. In this regard, an optimal solution is introduced to schedule elephant flows across paths to mitigate network congestion and increase load balancing in SDN. Nevertheless, optimal flows scheduling mechanism is still not applicable because the required time to calculate the optimal paths is not tolerable in SDN. We present a new decomposition technique for limiting the search space based on the linear programming method to solve the problem in a reasonable time. Since the mice flows have the sensitive time requirements, some paths are reserved for immediately forwarding these flows. The proposed method achieves reasonable performance regarding computation time compared with state-of-the-art solutions devoted to this topic. The results also show that the proposed traffic engineering method is effective to control network congestion and provide load balancing in SDN datacenters. [ABSTRACT FROM AUTHOR]

In this paper, a novel evolutionary optimization algorithm, named Partial Reinforcement Optimizer (PRO), is introduced. The major idea behind the PRO comes from a psychological theory in evolutionary learning and training called the partial reinforcement effect (PRE) theory. According to the PRE theory, a learner is intermittently reinforced to learn or strengthen a specific behavior during the learning and training process. The reinforcement patterns significantly impact the response rate and strength of the learner during a reinforcement schedule, achieved by appropriately selecting a reinforcement behavior and the time of applying reinforcement process. In the PRO algorithm, the PRE theory is mathematically modeled to an evolutionary optimization algorithm for solving global optimization problems. The efficiency of the proposed PRO algorithm is compared to well-known Meta-heuristic Algorithms (MAs) using Wilcoxon and Friedman statistical tests to analyze results from 75 benchmarks of the CEC2005, CEC2014, and CEC-BC-2017 test suits, which include unimodal, multimodal, hybrid, and composition functions. Additionally, the proposed PRO algorithm is applied to optimize a Federated Deep Learning Electrocardiography (ECG) classifier, as a real case study, to investigate the robustness and applicability of the proposed PRO. The experimental results demonstrate that the PRO algorithm outperforms existing meta-heuristic optimization algorithms by providing a more accurate and robust solution. [ABSTRACT FROM AUTHOR]

Face recognition is used in many applications such as access control, automobile security, criminal identification, immigration, healthcare, cyber security, and so on. Each person has his/her own unique face, so the face can help distinguish people from each other. Feature extraction process plays a fundamental role in accuracy of face recognition, and many algorithms have been presented to extract more informative features from the face image. In this paper, an efficient texture descriptor is proposed based on local information of the face image. In the proposed method, at first, face image is split into several sub-images in such a way that each sub-image includes one of the facial parts such as eyes, nose, and lips. Second, texture features are extracted from each sub-image using a new local pattern descriptor, and then features of sub-images are concatenated to construct feature vector. Finally, the face image is compared to images in a dataset based on a similarity measure. In addition, particle swarm optimization algorithm is used to assign weight to the features of different parts of the face image. To evaluate the proposed algorithm, four face datasets, Yale, ORL, GT and KDEF, are used. Implementation results show that the proposed method outperforms recent methods in terms of accuracy, receiver operating characteristic (ROC) curve, and area under ROC curve. [ABSTRACT FROM AUTHOR]

Abstract Hybrid Wireless Network on Chip (WNoC) architecture has been proposed as a promising solution for addressing on-chip communication problems in many multicore systems. The choice of infrastructure topology directly affects the performance gain of the architecture. For exploiting the benefits offered by both mesh and tree topologies, we employ Mesh-of-Tree (MoT) topology as a new communication infrastructure for hybrid WNoC architectures. Moreover, long-distance links are effectively added to the MoT topology to form wireless MoT architecture and an appropriate communication routing scheme is presented to employ this paradigm. The performance and the system cost of the proposed WNoC architecture have been evaluated and compared with other notable WNoC architectures through comprehensive network-level simulations. Experimental results demonstrate the effectiveness of this wireless MoT architecture under both synthetic and realistic traffic patterns in terms of network throughput, latency, and power consumption. The results demonstrate that the proposed architecture can approximately achieve 35% improvement in saturation throughput, 58% reduction in transmission latency, and 43% improvement in power consumption over a wireline MoT-NoC, on average. Highlights • We propose a novel Mesh-of-Tree WNoC architecture for multicore systems. • We introduce an effective wireless MAC and routing mechanisms for the proposed architecture. • We conduct a series of experiments to evaluate the MoT topology for WNoC architectures. • The proposed MoT-WNoC architecture provides an efficient backbone for multicore systems. [ABSTRACT FROM AUTHOR]

Virtualization as one of the leading technologies has assisted datacenters to cloudify their products and provide versatile platforms and variety of Internet services. This technology also has facilitated agile deployment of complex Internet services such as Cloud-based multi-tier applications. However implementing multi-tier applications assists providers to set up flexible and scalable services, deploying such applications in virtualized environments faces challenges, which harden collocation of disparate multi-tier applications in a shared environment. In this article, we propose a placement strategy to consolidate multi-tier applications' tiers in a virtualized datacenter regarding workload demands of individual tiers, utilization of physical hosts' resources and operational status of virtual machines. The placement strategy identifies over-utilized hosts based on the birth--death stochastic process and ranks tiers based on Data Envelopment Analysis-Analytic Hierarchy Process modeling to be placed on target hosts. A prioritized tier will be placed on an appropriate host though least operational interference with hosted tiers incurred. The efficiency of the proposed model is evaluated using a series of in-depth experiments. We introduce results derived from quantitative and qualitative analyses that are useful for multi-tier applications placement in virtualized datacenters. Simulation results reveal that the proposed solution excels in terms of both load distribution and energy consumption in the datacenter, while the number of unnecessary migrations and consecutive Service Level Agreement violations is considerably reduced. [ABSTRACT FROM AUTHOR]

Two-dimensional convolution plays a fundamental role in different image processing applications. Image convolving with different kernel sizes enriches the overall performance of image processing applications. In this regard, it is necessary to design of reconfigurable convolver with respect to desired kernel sizes list. In this paper, a novel approach is presented for implementation of an area-efficient reconfigurable convolver with appropriate throughput and convolution computational time for an arbitrary kernel size list. This approach is based on the adjustment of logical blocks arrangement in the conventional convolvers. The feasibility and benefits of the proposed approach are demonstrated through a case study of the design implementation on an FPGA platform using the XILINX ISE software. Compared to the well-known reconfigurable convolvers, the proposed design significantly reduces convolution computational time and improves throughput with a reasonable number of hardware resources. For instance, the proposed reconfigurable convolver only requires 0.38 ms to perform a 3 × 3 convolution on a 268 × 460 image with 8-bit pixels and only occupies 455 slices resource of Xilinx Virtex-4 (XC4VLX25) FPGA, in which the throughput of 324 million outputs per second (MOPS) is provided with 81 MHz clock frequency for kernel size of 3 × 3. On average, the MPOS of the proposed approach is approximately improved by 43.13% in relation to the other considered alternatives. Experimental results confirm that the proposed reconfigurable convolver is a very competitive design among the alternative reconfigurable convolvers. [ABSTRACT FROM AUTHOR]