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Analog & digital circuits implemented in a dual threshold voltage (VT) p-channel organic technology are presented. The dual VT organic technology is compatible with large-area and mechanically flexible substrates due to its low processing temperature (\leq \95\ ^\circ\C) and scalable patterning techniques. We demonstrate the first analog & digital organic integrated circuits produced by a dual-gate metal process. The analog circuits are powered by a 5-V supply and include a differential amplifier and a two-stage uncompensated operational amplifier (op-amp). A dynamic comparator is measured to have an input offset voltage of 200 mV and latching time of 119 ms. Both the comparator and the op-amp dissipate 5 nW or less. Area-minimized digital logic is presented. Inverters powered by a 3-V supply were measured to have positive noise margins and consumed picowatts of power. An 11-stage ring oscillator, also powered by a 3-V supply, swings near rail to rail at 1.7 Hz. These results demonstrate dual threshold voltage process feasibility for large-area flexible mixed-signal organic integrated circuits. [ABSTRACT FROM PUBLISHER]

A fully photolithographic dual threshold voltage (VT) organic thin-film transistor (OTFT) process suitable for flexible large-area integrated circuits is presented. The near-room-temperature (\leq \95\ ^\circ\C) process produces integrated dual VT pentacene-based p-channel transistors. The two VT's are enabled by using two gate metals of low (aluminum) and high (platinum) work function. The Al and Pt gate OTFTs exhibit nominally identical current–voltage transfer curves shifted by an amount \Delta VT. The availability of a high-VT device enables area-efficient zero-VGS high-output-resistance current sources, enabling high-gain inverters. We present positive noise margin inverters and rail-to-rail ring oscillators powered by a 3-V supply—one of the lowest supply voltages reported for OTFT circuits. These results show that integrating n- and p-channel organic devices is not mandatory to achieve functional area-efficient low-power organic integrated circuits. [ABSTRACT FROM PUBLISHER]

The effects of bias stress in integrated pentacene organic transistors are studied and modeled for different stress conditions. It is found that the effects of bias stress can be expressed in terms of the shift in applied gate voltage ΔV for a given current. An empirical equation describing ΔV in terms of different gate and drain bias stress measurements and stress times is presented and verified. In the measured devices, ΔV saturates at 14 V, independent of the gate bias-stress condition. A model based on carrier trapping rate equation that accounts for this ΔV saturation is developed. The model suggests that the ΔV saturation is due to the small density of traps compared to the channel carrier density. [ABSTRACT FROM AUTHOR]

In this paper, a proof of concept 4 x 4 active-matrix imager fabricated at near room temperature (<95 °C) is presented. Conventional photolithography and inkjet printing were used to pattern integrated organic FETs and photoconductors. The design and characterization of a pixel circuit is described. A simple first-order calibration technique is used to partially compensate for fixed pattern noise. Following the calibration, the imager is shown to correctly image a "T" pattern. [ABSTRACT FROM AUTHOR]