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The development vector of modern central processing units, which increasingly involves using a more significant number of cores and prioritizing parallelism over the high power of a single computational unit, presents new challenges for the existing software design. This work investigates and addresses the problem of access to shared memory in multithreaded environments, such as operating systems, interactive distributed computing systems, and high-performance simulation systems. Thus, the object of study is a non-blocking approach to organizing access to memory and performing basic operations with it through non-blocking synchronization. The research methods include developing an approach to organizing access to shared memory using the doubleword compare-and-swap algorithm, followed by a theoretical and practical comparison of the resulting outcome with the standard blocking access algorithm to shared memory for different configurations of the number of threads and the number of simultaneous memory access attempts. Additionally, testing was conducted within the framework of an unnamed closed-source project by integrating the solution into it, followed by A/B testing. The results showed that using non-blocking approaches is advisable, especially in comparison with locking approaches, which demonstrated a performance degradation relative to the standard allocation algorithm by more than 300 %, while non-blocking approaches provided an improvement of 40–90 %. It was also found that using hybrid approaches to the organization of shared memory systems at the software level can lead to more stable results and mitigate application performance degradation compared to classical approaches such as buddy algorithms or free lists. Despite the results obtained, the author remains cautious about the idea of memory management and pool organization at the software level and does not recommend using specialized allocation algorithms without an urgent need to speed up memory allocation itself. The purpose of these structures is still not to improve software performance directly but to enhance and speed up access to the data stored in them. [ABSTRACT FROM AUTHOR]

Simultaneous Multi-Threading (SMT) processors provide improvement over the traditional out-of-order superscalar architecture by allowing instructions from several independent threads to execute out-of-order concurrently. Maintaining the accuracy of values read from and written to memory is a great bottleneck for processor performance, as loads must stall execution until all prior store addresses are known or risk reading invalid data. Prior research in this area has mainly focused on superscalar architecture, as such, it is only natural to extend memory dependence speculation techniques to an SMT architecture. In this paper, we allow for loads among threads to execute as soon as their addresses are resolved without checking for prior memory address conflicts. Stores also perform a check on all later loads to see if any read was too early due to an address match, if so, the processor state is recovered, and the load re-issued. This aggressive technique allows for the greatest potential instructions per clock cycle gains over predictive techniques as the pipeline is never stalled for loads. Our simulations show that an overall IPC gain up to 12% and 10% is possible for both 4-threaded and 8-threaded workloads respectively. Conversely, a maximum overall IPC loss of at least 2.3% and 2% for 4-threaded and 8-threaded workloads respectively was also observed. [ABSTRACT FROM AUTHOR]

In recent times, there has been a noticeable surge in the inclination towards the implementation of network automation solutions. This trend is driven by the objective of optimizing network availability within the context of hybrid data center networks, which are becoming increasingly prevalent. Reliability, performance, scalability, and minimal resource overhead are crucial solution design characteristics that significantly impact the decisionmaking process regarding adoption. Recent research has shown that 90% of network outages happen because of human factors and 69% of respondents manage their network with manual method. That high human error of up to 90%, occurs when configuring network devices using manual method. These problems had a negative impact on the functioning of the organization and were harmful to the user. In this research, we investigate solutions to reduce network outage that caused human error using network automation using the Python programming language and multi-threading method. This network automation will reduce configuration time, eliminate human error, and significantly increase efficiency. The aim of this research is to investigate the efficacy of network automation using Python and multi-threading to reduce network outages.The method used in this research is a parallel or multi-tread execution process method using GNS3 as network simulator. Based on experimental results, the multithread automation approach is significantly faster than both the serial automation method (67 seconds) and the manual method (248 seconds), this method requiring only 41 seconds to configure all Cisco router devices. If you're looking for speed, look no farther than the multithread automation approach, which is 6 times quicker than the manual method and 3.7 times quicker than the serial automation approach. The findings of this study have substantial and immediate implications for the ability of network engineers to speed up the configuration of networks and lower the rate of human error in doing so. [ABSTRACT FROM AUTHOR]

In the ship information big data system, aiming at the problems such as long time consuming, distortion of thermal map effect and poor tracking or lag in the roaming of map software when the client requests a large amount of historical data from the server and draws heat map in real time, this paper proposes an improved real-time generation strategy of map map of ship history activity. Based on the thermal map generation method with the idea of pixel clustering, this strategy uses the image enhancement algorithm based on nonlinear transformation and pixel complement method to correct and optimize the display distortion problems existing in the head map. On this basis, the dynamic loading and drawing strategy and multi-thread real-time mapping strategy are proposed to generate the heat map of the ship’s historical activities. Experiments show that the strategy proposed in this paper has been improved in the efficiency of heat map drawing, mapping effect and interactive experience of map software. [ABSTRACT FROM AUTHOR]

The rapid development of information technology has made the amount of information in massive texts far exceed human intuitive cognition, and dependency parsing can effectively deal with information overload. In the background of domain specialization, the migration and application of syntactic treebanks and the speed improvement in syntactic analysis models become the key to the efficiency of syntactic analysis. To realize domain migration of syntactic tree library and improve the speed of text parsing, this paper proposes a novel approach—the Double-Array Trie and Multi-threading (DAT-MT) accelerated graph fusion dependency parsing model. It effectively combines the specialized syntactic features from small-scale professional field corpus with the generalized syntactic features from large-scale news corpus, which improves the accuracy of syntactic relation recognition. Aiming at the problem of high space and time complexity brought by the graph fusion model, the DAT-MT method is proposed. It realizes the rapid mapping of massive Chinese character features to the model's prior parameters and the parallel processing of calculation, thereby improving the parsing speed. The experimental results show that the unlabeled attachment score (UAS) and the labeled attachment score (LAS) of the model are improved by 13.34% and 14.82% compared with the model with only the professional field corpus and improved by 3.14% and 3.40% compared with the model only with news corpus; both indicators are better than DDParser and LTP 4 methods based on deep learning. Additionally, the method in this paper achieves a speedup of about 3.7 times compared to the method with a red-black tree index and a single thread. Efficient and accurate syntactic analysis methods will benefit the real-time processing of massive texts in professional fields, such as multi-dimensional semantic correlation, professional feature extraction, and domain knowledge graph construction. [ABSTRACT FROM AUTHOR]

In detection-free tracking, after users freely designate the location of the object to be tracked in the first frame of the video sequence, the location of the object is continuously found in the following video frame sequence. Recently, technologies using a Siamese network and transformer based on DNN modules have been evaluated as very excellent in terms of tracking accuracy. The high computational complexity due to the usage of the DNN module is not a preferred feature in terms of execution speed, and when tracking two or more objects, a bottleneck effect occurs in the DNN accelerator such as the GPU, which inevitably results in a larger delay. To address this problem, we propose a tracker scheduling framework. First, the computation structures of representative trackers are analyzed, and the scheduling unit suitable for the execution characteristics of each tracker is derived. Based on this analysis, the decomposed workloads of trackers are multi-threaded under the control of the scheduling framework. CPU-side multi-threading leads the GPU to a work-conserving state while enabling parallel processing as much as possible even within a single GPU depending on the resource availability of the internal hardware. The proposed framework is a general-purpose system-level software solution that can be applied not only to GPUs but also to other hardware accelerators. As a result of confirmation through various experiments, when tracking two objects, the execution speed was improved by up to 55% while maintaining almost the same accuracy as the existing method. [ABSTRACT FROM AUTHOR]

This paper introduces an event‐based computing paradigm, where workers only perform computation in response to external stimuli (events). This approach is best employed on hardware with many thousands of smaller compute cores with a fast, low‐latency interconnect, as opposed to traditional computers with fewer and faster cores. Event‐based computing is timely because it provides an alternative to traditional big computing, which suffers from immense infrastructural and power costs. This paper presents four case study applications, where an event‐based computing approach finds solutions to orders of magnitude more quickly than the equivalent traditional big compute approach, including problems in computational chemistry and condensed matter physics. [ABSTRACT FROM AUTHOR]

In this work, we have prepared and analyzed three case studies comparing CPU and GPGPU calculations. After briefly introducing the topic of parallel programming by means of contemporary CPU and GPGPU technologies, we provide an overview of selected existing works closely related to the topic of the paper. For each of the case studies, a set of programs has been implemented using the following technologies: pure CPU, CPU SIMD, CPU multi-threaded, CPU multi-threaded with SIMD instructions, and GPU - Cuda. We also illustrate the basic idea of the operation of selected algorithms using code snippets. Subsequently, the particular implementations are compared, and obtained results are evaluated and discussed. [ABSTRACT FROM AUTHOR]

As technology scales, transistors become smaller and aggressive power optimization techniques combined with high operation frequencies and performance-enhancing microarchitectural techniques are employed to achieve increasingly higher performance and power efficiencies. Unfortunately, these developments make the modern systems more vulnerable to soft errors, which are becoming a critical issues in both hardware and software domains. Motivated by this observation, in this work, we propose, implement, and evaluate two error propagation metrics in order to characterize error propagation at both software and hardware levels. The first metric aims to measure error propagation on program data structures, whereas the second one measures the fraction of corrupted locations in the cache memory structure for a given period of time. We evaluate our proposed metrics by performing an empirical study of two application programs using both single-threaded and multi-threaded executions, and varying various experimental parameters such as thread count, error rate, location of errors, and architectural parameters. Our extensive experimental analysis reveals that error propagation over program data structures is highly dependent on application behavior.Further, depending on the cache parameters used, propagation of errors on cache can exhibit different patterns. This paper also discusses how our observed error propagation trends in program data structures and data caches are correlated with each other, focusing in particular on the differences in error propagation speeds in application data structures and data caches. [ABSTRACT FROM AUTHOR]

The numerical simulation of dendritic crystal growth with melt convection in complex domains is of great significance in academic research and industrial application. However, the processing of complex boundaries, huge computational costs of three-dimensional problems and strong nonlinear coupling of multiple equations make the numerical simulation of dendritic crystal growth face great challenges. In this study, a new dendritic crystal growth phase field model with melt convection in complex domains is firstly established. The new model avoids the difficulty of dealing with complex boundaries and can be computed on the rectangle or parallelepiped. The modeling process adopts the idea of the multi-component Allen–Cahn equation modeling idea, weight factor and Lagrange multiplier. Secondly, for the efficient computation, a second-order dimension splitting numerical scheme is developed for the new model. It decomposes the high-dimensional problem into a series of one-dimensional problems which can be computed by multi-threading. Finally, to achieve decoupling, the nonlinear and coupled terms are explicitly computed, and stabilization terms are added to enhance the long-time computational stability. The accuracy and efficiency of the dimension splitting method are verified by numerical experiments. The numerical simulations of fourfold, fivefold and sixfold anisotropic single dendritic crystal growth and multiple dendritic crystal growth show that complex domains and melt convection greatly affect the normal growth pattern of dendritic crystal growth. In addition, the numerical experiments also show that when the dendritic crystal growth rate is slow, the melt convection can promote the growth rate under the same conditions. • A new dendritic crystal growth model with melt convection in complex domains is established for multi-threading simulation. • A dimension splitting scheme is proposed for the new model which can be computed by multi-threading. • A large number of dendritic crystal growth in complex domains is numerically simulated. [ABSTRACT FROM AUTHOR]

The evolution of simulation and implementation of P systems has been intense since the theoretical model of computation was created. In the field of software simulation of P systems, the proposals made so far have taken advantage mainly of the parallelism of GPUs, but not of the parallelism of existing multi-core processors. This paper proposes a new model for simulating P systems using a multi-threaded approach in a multi-core processor. This simulation approach establishes a new paradigm that is entirely in line with the philosophy of P-systems: since objects must react in parallel, asynchronously and autonomously with other objects, simulation using multiple synchronized threads completely mimics the behavior of objects within a membrane. This proposal has been implemented and tested using a simulator programmed in C#, and its correct operation has been tested for confluent and non-confluent systems. The experimental results confirm that the simulator scales well with the number of hardware threads of a multiprocessor. The obtained results show that the new model is correct and that it can be extended to other more complex types of P systems, in order to discover which are the limit of this multi-threaded approach when running it in multi-core processors. • A pioneering approach for membrane simulation based on CPU multi-threading. • The approach can be straightforwardly used to simulate generic transitive P systems. • A multi-threaded implementation of the P system simulator has been tested. • Performance speedup results directly proportional to the number of hardware threads. [ABSTRACT FROM AUTHOR]

Modern-day graph workloads operate on huge graphs through pointer chasing which leads to high last-level cache (LLC) miss rates and limited memory-level parallelism (MLP). Simultaneous Multi-Threading (SMT) effectively hides the memory access latencies for multi-threaded graph workloads provided that sufficient threads are supported in hardware. Unfortunately, providing a sufficiently large number of physical threads incurs an unjustifiably high hardware cost for commodity SMT processors which typically implement only two physical hardware threads. Ideally, we would like to achieve aggressive-SMT performance when running graph workloads on modest commodity processors. In this paper, we propose Virtualized Multi-Threading (VMT), a low-overhead multi-threading paradigm for accelerating graph workloads on commodity processors. Unlike prior multi-threading paradigms, VMT virtualizes both the physical hardware threads and the architecture state: VMT maps a large number of logical software threads to a small number of physical hardware threads, while maintaining the architecture state of the logical threads in the processor's cache hierarchy. Implemented on top of a quad-core 2-way SMT processor, VMT achieves an average speedup of 1.74× for a set of representative graph workloads, while incurring minimal hardware cost (195 bytes per core to support up to 32 logical threads). VMT's low hardware cost paves the way for implementation in commodity processors. [ABSTRACT FROM AUTHOR]

The internet of things (IoT) concept has been extremely investigated in many modern smart applications, which enable a set of sensors to either process the collected data locally or send them to the cloud for remote processing. Unfortunately, cloud datacenters are located far away from IoT devices, and consequently, the transmission of IoT data may be delayed. In this paper, we investigate fog computing, which is a new paradigm that overcomes many issues of cloud computing. More importantly, dynamic task offloading in fog computing is a challenging problem that requires an optimal decision for processing the tasks that are generated in each time slot. Thus, exact optimization methods based on Lyapunov function have been widely used for solving dynamic offloading which represents an NP hard problem. To overcome the scalability issue of exact optimization techniques, we have explored famous population based meta-heuristics for optimizing the offloading process of a set of dynamic tasks using Orthogonal Frequency Division Multiplexing (OFDM) communication. Hence, a parallel multi-threading framework is proposed for generating the optimal offloading solution while selecting the best sub-carrier for each offloaded task. More importantly, our contribution associates a thread for each IoT device and generates a population of random solutions. Next, each population is updated and evaluated according to the proposed fitness function that considers a tradeoff between the delay and energy consumption. Upon the arrival of new tasks at each time slot, an evaluation is performed for maintaining some individuals of the previous population while generating new individuals based on some criteria. Our results have been compared to the results achieved using Lyapunov optimization. They demonstrate the convergence of the fitness function, the scalability of the parallel Particle Swarm Optimization (PSO) approach, and the performance in terms of the offline error and the execution cost. [ABSTRACT FROM AUTHOR]

Graph analytics are an emerging class of irregular applications. Operating on very large datasets, they present unique behaviors, such as fine-grained, unpredictable memory accesses, and highly unbalanced task level parallelism, that make existing high-performance general-purpose processors or accelerators (e.g., GPUs) suboptimal. To address these issues, research and industry are developing a variety of custom accelerator designs for this application area, including solutions based on reconfigurable devices (Field Programmable Gate Arrays). These new approaches often employ High-Level Synthesis (HLS) to Speed up the development of the accelerators. In this paper, we propose a novel architecture template for the automatic generation of accelerators for graph analytics and irregular applications. The architecture template includes a dynamic task scheduling mechanism, a parallel array of accelerators that enables supporting task-level parallelism with context switching, and a related multi-channel memory interface that decouples communication from computation and provides support for fine-grained atomic memory operations. We discuss the integration of the architectural template in an HLS flow, presenting the necessary modifications to enable automatic generation of the custom architectures starting from OpenMP annotated code. We evaluate our approach first by synthesizing and exploring triangle counting, a common graph algorithm, and then by synthesizing custom designs for a set of graph database benchmark queries, representing series of graph pattern matching routines. We compare the synthesized accelerators with previous state-of-the-art methodologies for the synthesis of parallel architectures, showing that the proposed approach allows reducing resource usage by optimizing the number of accelerators replicas without any performance penalty. [ABSTRACT FROM AUTHOR]

The multiplication of computing cores in modern processor units permits revisiting the design of classical algorithms to improve computational performance in complex application domains. Artificial Intelligence planning is one of those applications where large search spaces require intelligent and more exhaustive search control. In this paper, parallel planning algorithms, derived from best-first search, are proposed for shared memory architectures. The parallel algorithms, based on the asynchronous work pool paradigm, maintain good thread occupancy in multi-core CPUs. All algorithms use one ordered global list of states stored in shared memory from where they select nodes for expansion. A parallel best-first search algorithm that develops new states with depth equal to one is proposed first. Then, we propose an extension of this parallel algorithm that features a diversification strategy in order to escape local minima. We study and analyse a set of computational experiments for problems that come from the International Planning Competition and real-world industry applications. The empirical evaluation shows that the parallel algorithms solve most of the domains efficiently without incurring higher solutions costs. In those problems with partial results, we highlight the potential shortcomings of the proposed approaches for promising future directions. [ABSTRACT FROM AUTHOR]

This letter investigates parallelism approaches for equation and Jacobian evaluations in large-scale power flow calculation. Two levels of parallelism are proposed and analyzed: inter-model parallelism, which evaluates models in parallel, and intra-model parallelism, which evaluates calculations within each model in parallel. Parallelism techniques such as multi-threading and single instruction multiple data (SIMD) vectorization are discussed, implemented, and benchmarked as six calculation workflows. Case studies on the 70 000-bus synthetic grid show that equation evaluations can be accelerated by ten times, and the overall Newton power flow advances the state of the art by 20%. [ABSTRACT FROM AUTHOR]

We investigated improvements to further speed up the multi-threaded scaling of the distributed hydrological model wflow_sbm. To gain insight in the speed improvements for operational applications, we connected the improved code to ECMWF's Fields Database to allow for on-the-fly pre-processing of the forcing, which accelerated the entire forecasting chain. In the original wflow_sbm implementation, run times increased when more than eight threads were used due to Julia's native threading overhead. Now, run times are 2 to 11 times faster, depending on the chosen routing scheme, number of threads and catchment size. We show the advantages of the improvements in a test setup where ECMWF forecasts and 35 years of ERA5 reanalysis data were used to force wflow_sbm models at 1x1 km spatial resolution for Europe. The attained speedup allows for using distributed hydrological models in large-scale hydrological forecasting and climate-change applications, which is currently often limited to lumped models. • Improved multi-threaded scaling of the distributed hydrological model wflow_sbm. • Two to eleven times faster run times on high-performance computing clusters. • Distributed hydrological model application for large-scale hydrological forecasting. [ABSTRACT FROM AUTHOR]

In the preceding Part I, a combined experimental-numerical study to characterize fine spray-dried powder used in the ceramic tile pressing process was presented. In the present Part II, the algorithm proposed by (Mazhar, 2011) to solve the numerical simulation of powder dynamics through the Discrete Element Method (DEM) was extended. In this paper, the original algorithm was adapted for efficient use on multi-core CPUs and a single GPU. In both cases, history-dependent contact models were considered. The efficiency of the algorithms was compared among them and with LIGGGHTS, a reference software package for particle simulation using DEM. The results demonstrated a higher performance of the codes developed compared to LIGGGHTS, particularly in demanding scenarios with a large number of particles (more than 1 million) of small size (median diameter in volume less than 1 mm). In particular, the CPU-based algorithm was suitable for simulating the mould filling in ceramic tiles industry. Unlabelled Image • A novel GPU and CPU-based DEM algorithm is developed. • Any general-purpose contact model can be used without restrictions in the contact searching. • The developed algorithms are fairly compared with LIGGGHTS. • Developed CPU-based DEM algorithm outperforms LIGGGHTS in demanding filling scenarios. • GPU-based DEM algorithm executed on a single GPU does not enhance the CPU-based algorithm. [ABSTRACT FROM AUTHOR]

The categorisation of network packets according to multiple parameters such as sender and receiver addresses is called packet classification. Packet classification lies at the core of Software‐Defined Networking (SDN)‐based network applications. Due to the increasing speed of network traffic, there is an urgent need for packet classification at higher speeds. Although it is possible to accelerate packet classification algorithms through hardware implementation, this solution imposes high costs and offers limited development capacity. On the other hand, current software methods to solve this problem are relatively slow. A practical solution to this problem is to parallelise packet classification using multi‐core processors. In this study, the Thread, parallel patterns library (PPL), open multi‐processing (OpenMP), and threading building blocks (TBB) libraries are examined and implemented to parallelise three packet classification algorithms, i.e. tuple space search, tuple pruning search, and hierarchical tree. According to the results, the type of algorithm and rulesets may influence the performance of parallelisation libraries. In general, the TBB‐based method shows the best performance among parallelisation libraries due to using a theft mechanism and can accelerate the classification process up to 8.3 times on a system with a quad‐core processor. [ABSTRACT FROM AUTHOR]

Nowadays, advanced smart mobile devices equipped with multi-core central processing units for handling multithreaded (MT) applications. However, existing research mainly uses single-thread (ST) computing to deal with applications, which limits the performance of mobile computing. To make full use of multi-core resources, this study proposes a fine-grained MT offloading strategy to solve the offloading problem of MT application. The strategy jointly schedules cloud computing resources, as well as local multi-core computing and communication resources. Precisely, the authors first formulate the minimum energy consumption problem for ST offloading. Then, they prove that the problem is convex and solve it by standard convex optimisation technique. Thirdly, they extend the optimisation goals from ST applications to MT applications, and design calculation rules for MT applications to reduce computing costs. Finally, based on these calculation rules and the optimal solution for ST offloading, they develop a MT offloading strategy to solve the computation offloading problem of MT applications. Simulation results show that the proposed fine-grained MT offloading strategy effectively reduces the minimum delay requirement of mobile computing. [ABSTRACT FROM AUTHOR]

Frequent dynamic memory allocations (DyMAs) can significantly hinder the scalability of parallel multi-threaded programs. As the number of threads grows, DyMAs can even become the main performance bottleneck. We introduce modern tools and methods for evaluating the impact of DyMAs and present techniques for its reduction, which include scalable heap implementations, small buffer optimization, and memory pooling. Additionally, we provide a survey of state-of-the-art implementations of these techniques and study them experimentally by using a benchmark program, server simulator software, and a real-world high-performance computing application. As a result, we show that relatively small modifications in parallel program's source code or a way of its execution may substantially reduce the runtime overhead associated with the use of dynamic data structures. [ABSTRACT FROM AUTHOR]

We investigate a parallelization strategy for dense matrix factorization (DMF) algorithms, using OpenMP, that departs from the legacy (or conventional) solution, which simply extracts concurrency from a multi-threaded version of basic linear algebra subroutines (BLAS). The proposed approach is also different from the more sophisticated runtime-based implementations, which decompose the operation into tasks and identify dependencies via directives and runtime support. Instead, our strategy attains high performance by explicitly embedding a static look-ahead technique into the DMF code, in order to overcome the performance bottleneck of the panel factorization, and realizing the trailing update via a cache-aware multi-threaded implementation of the BLAS. Although the parallel algorithms are specified with a high level of abstraction, the actual implementation can be easily derived from them, paving the road to deriving a high performance implementation of a considerable fraction of linear algebra package (LAPACK) functionality on any multicore platform with an OpenMP-like runtime. [ABSTRACT FROM AUTHOR]

Large-scale modeling and simulation (M&S) applications that do not require run-time inter-process communications can exhibit scaling problems when migrated to high-performance computing (HPC) clusters if traditional software parallelization techniques, such as POSIX multi-threading and the message passing interface, are used. A comprehensive approach for scaling M&S applications on HPC clusters has been developed and is called "computation segmentation." The computation segmentation is based on the built-in array job facility of job schedulers. If used correctly for appropriate applications, the array job approach provides significant benefits that are not obtainable using other methods. The parallelization illustrated in this paper becomes quite complex in its own right when applied to extremely large M&S tasks, particularly due to the need for nested loops. At the United States Food and Drug Administration, the approach has provided unsurpassed efficiency, flexibility, and scalability for work that can be performed using embarrassingly parallel algorithms. [ABSTRACT FROM AUTHOR]

Sequentialization has been shown to be an effective symbolic verification technique for safety properties in multi-threaded C programs using POSIX threads. The tool Lazy-CSeq, which applies a lazy sequentialization scheme, demonstrated its efficiency by ranking top places within the concurrency division of the Competitions on Software Verification in recent years. This lazy sequentialization scheme encodes all thread schedules up to a given exploration bound into a single non-deterministic sequential C program. Another particularly effective technique to tackle the state explosion of multi-threaded programs is Partial Order Reduction (POR). It works by limiting the exploration of redundant thread execution orders (i.e., schedules) by exploiting independence. Integrating POR into lazy sequentialization can further significantly improve its scalability. However, a combination of both techniques can lead to unsoundness, i.e., reachability of states is not preserved within the exploration bound. The reason is that POR is not aware of the exploration bound; therefore, POR can prune a schedule which will reach a bug within the exploration bound and instead keep another (functionally) equivalent schedule which requires a larger exploration bound to reach the bug. This paper presents a novel implementation of lazy sequentialization, which integrates symbolic POR into the encoding to prune redundant schedules. An efficient pruning check is employed to make the POR technique aware of the exploration bound and thus avoid unsoundness, while still providing significant state space reductions. On the other hand, the integration of POR entails some additional encoding overhead that can also result in a performance slowdown. Such a case is avoided by a practical heuristic that only employs POR if the encoding overhead of POR is reasonable (i.e., less than 50%). Experimental evaluation shows that our proposed approach can provide considerable speed-ups. [ABSTRACT FROM AUTHOR]

• A practical technique to achieve load-balancing for linear pipelines is presented. • Hybrid mapping and concurrent data structure together enable efficient execution. • Simple configuration of the runtime system for performance and stability. • Evaluation on 44 cores shows high performance for widely-used programs. • Efficiency makes the technique suitable for fine-grained workloads. Pipelining is a well-known technique to overlap loop iterations by partitioning the loop body into a sequence of stages. A large class of programs can be expressed as linear pipelines if data dependences only flow from earlier to later stages. Various pipelining techniques have been explored but reconciling load-balancing and efficient execution is still a challenge for two main reasons. First, partitioning of the loop body into stages that lead to load-balancing may depend on the data set as well as system properties, e.g., number of cores. Second, the configuration of the runtime system is far from obvious. In this article, we present Pipelight , a technique that achieves load-balancing for linear pipelines. Pipelight relies on a way of mapping stages onto threads that simplifies partitioning and enables the design of a lightweight algorithm for dynamic scheduling. Furthermore, Pipelight introduces a concurrent data structure that exploits the properties of data dependences presented in linear pipelines to provide efficient communication and synchronization. This data structure simplifies the configuration of the runtime system and makes Pipelight a practical solution. The evaluation on a 44-core system shows the efficiency of Pipelight for a set of programs selected from widely-used collections. Although Pipelight simplifies parallelization of linear pipelines, it performs similarly to the most efficient properly configured state-of-the-art technique. The price paid for the benefits of Pipelight is additional overhead for fine-grained loops. However, this overhead can be amortized successfully with chunking. To make Pipelight a promising solution, we propose a directive-based transformation for Pipelight , which is developed in a prototype source-to-source compiler. Consequently, Pipelight is an efficient and practical solution to achieve load-balancing for fine-grained linear pipelines. [ABSTRACT FROM AUTHOR]

With the advent of multi-core era and people′s need for data security, it has become even more important to design a parallel encryption algorithm based on a multi-core platform. By combining hyperelliptic curve encryption with a multi-core multithreading framework, a hyper-elliptic curve parallel encryption scheme based on a multi-core and multi-threaded platform is designed, and the performance of the encryption scheme is theoretically analyzed. In the experimental test, the files with the file size of 100~600 Kare encrypted in parallel. The time spent on encryption is summarized by changing the number of threads, the number of CPU cores, and the size of the encrypted data. The experimental results show that the data is processed in an 8-core 8-threaded framework. Parallel encryption processing, parallel speed up to 7. 87. [ABSTRACT FROM AUTHOR]

We investigate how to leverage the heterogeneous resources of an Asymmetric Multicore Processor (AMP) in order to deliver high performance in the reduction to condensed forms for the solution of dense eigenvalue and singular-value problems. The routines that realize this type of two-sided orthogonal reductions (TSOR) in LAPACK are especially challenging, since a significant fraction of their floating-point operations are cast in terms of memory-bound kernels while the remaining part corresponds to efficient compute-bound kernels. To deal with this scenario: (1) we leverage implementations of memory-bound and compute-bound kernels specifically tuned for AMPs; (2) we select the algorithmic block size for the TSOR routines via a practical model; and (3) we adjust the type and number of cores to use at each step of the reduction. Our experiments validate the model and assess the performance of our asymmetry-aware TSOR routines, using an ARMv7 big.LITTLE AMP, for three key operations: the reduction to tridiagonal form for symmetric eigenvalue problems, the reduction to Hessenberg form for non-symmetric eigenvalue problems, and the reduction to bidiagonal form for singular-value problems. [ABSTRACT FROM AUTHOR]

Sequential pattern mining (SPM) plays an important role in data mining, with broad applications such as in financial markets, education, medicine, and prediction. Although there are many efficient algorithms for SPM, the mining time is still high, especially for mining sequential patterns from huge databases, which require the use of a parallel technique. In this paper, we propose a parallel approach named MCM-SPADE (Multiple threads CM-SPADE), for use on a multi-core processor system as a multi-threading technique for SPM with very large database, to enhance the performance of the previous methods SPADE and CM-SPADE. The proposed algorithm uses the vertical data format and a data structure named CMAP (Co-occurrence MAP) for storing co-occurrence information. Based on the data structure CMAP, the proposed algorithm performs early pruning of the candidates to reduce the search space and it partitions the related tasks to each processor core by using the divide-and-conquer property. The proposed algorithm also uses dynamic scheduling to avoid task idling and achieve load balancing between processor cores. The experimental results show that MCM-SPADE attains good parallelization efficiency on various input databases. [ABSTRACT FROM AUTHOR]

We analyze the benefits of look-ahead in the parallel execution of the LU factorization with partial pivoting (LUpp) in two distinct “asymmetric” multicore scenarios. The first one corresponds to an actual hardware-asymmetric architecture such as the Samsung Exynos 5422 system-on-chip (SoC), equipped with an ARM big.LITTLE processor consisting of a quad-core Cortex-A15 cluster plus a quad-core Cortex-A7 cluster. For this scenario, we propose a careful mapping of the different types of tasks appearing in LUpp to the computational resources, in order to produce an efficient architecture-aware exploitation of the computational resources integrated in this SoC. The second asymmetric configuration appears in a hardware-symmetric multicore architecture where the cores can individually operate at a different frequency levels. In this scenario, we show how to employ the frequency slack to accelerate the tasks in the critical path of LUpp in order to produce a faster global execution as well as a lower energy consumption. [ABSTRACT FROM AUTHOR]

Finding the optimal parameters that can reproduce experimental data (such as the velocity-density relation and the specific flow rate) is a very important component of the validation and calibration of microscopic crowd dynamic models. Heavy computational demand during parameter search is a known limitation that exists in a previously developed model known as the Harmony Search-Based Social Force Model (HS-SFM). In this paper, a parallel-based mechanism is proposed to reduce the computational time and memory resource utilisation required to find these parameters. More specifically, two MATLAB-based multicore techniques (parfor and create independent jobs) using shared memory are developed by taking advantage of the multithreading capabilities of parallel computing, resulting in a new framework called the Parallel Harmony Search-Based Social Force Model (P-HS-SFM). The experimental results show that the parfor-based P-HS-SFM achieved a better computational time of about 26 h, an efficiency improvement of 54% and a speedup factor of 2.196 times in comparison with the HS-SFM sequential processor. The performance of the P-HS-SFM using the create independent jobs approach is also comparable to parfor with a computational time of 26.8 h, an efficiency improvement of about 30% and a speedup of 2.137 times. [ABSTRACT FROM AUTHOR]

Graphical processing unit (GPU) has proven a beneficial tool in handling computationally intensive algorithms, by introducing massive parallelism in the calculations. In this study, an effective and low‐cost fingerprint identification (FI) solution is proposed that can exploit the parallel computational power of GPU proficiently. It is achieved by mapping a generalised minutia neighbour‐based novel encoding and matching algorithm on low‐cost GPU technology. The proposed solution achieves high accuracy in comparison with two open source matchers and it is shown to be scalable by comparing matching performance on different GPUs. The proposed GPU implementation employs multithreading and loop unrolling, which minimises the use of nested loops and avoids sequential matching of encoded minutia features. After a thorough and careful designing of data structures, memory transfers and computations, a GPU‐based fingerprint matching system is developed. It achieves on average 50,196 fingerprint matches per second on a single GPU. As compared to the sequential central processing unit implementation, the proposed system achieves a speed up of around 92 times, while maintaining the accuracy. The proposed system with matcher integrated on GPU can be considered as a good, low‐cost, robust and efficient solution for large‐scale applications of automated FI systems. [ABSTRACT FROM AUTHOR]

Background: Recent breakthroughs in molecular biology and next generation sequencing technologies have led to the expenential growh of the sequence databases. Researchrs use BLAST for processing these sequences. However traditional software parallelization techniques (threads, message passing interface) applied in newer versios of BLAST are not adequate for processing these sequences in timely manner. Methods: A new method for array job parallelization has been developed which offers O(T) theoretical speed-up in comparison to multi-threading and MPI techniques. Here T is the number of array job tasks. (The number of CPUs that will be used to complete the job equals the product of T multiplied by the number of CPUs used by a single task.) The approach is based on segmentation of both input datasets to the BLAST process, combining partial solutions published earlier (Dhanker and Gupta, Int J Comput Sci Inf Technol_5:4818-4820, 2014), (Grant et al., Bioinformatics_18:765-766, 2002), (Mathog, Bioinformatics_19:1865-1866, 2003). It is accordingly referred to as a "dual segmentation" method. In order to implement the new method, the BLAST source code was modified to allow the researcher to pass to the program the number of records (effective number of sequences) in the original database. The team also developed methods to manage and consolidate the large number of partial results that get produced. Dual segmentation allows for massive parallelization, which lifts the scaling ceiling in exciting ways. Results: BLAST jobs that hitherto failed or slogged inefficiently to completion now finish with speeds that characteristically reduce wallclock time from 27 days on 40 CPUs to a single day using 4104 tasks, each task utilizing eight CPUs and taking less than 7 minutes to complete. Conclusions: The massive increase in the number of tasks when running an analysis job with dual segmentation reduces the size, scope and execution time of each task. Besides significant speed of completion, additional benefits include fine-grained checkpointing and increased flexibility of job submission. "Trickling in" a swarm of individual small tasks tempers competition for CPU time in the shared HPC environment, and jobs submitted during quiet periods can complete in extraordinarily short time frames. The smaller task size also allows the use of older and less powerful hardware. The CDRH workhorse cluster was commissioned in 2010, yet its eight-core CPUs with only 24GB RAM work well in 2017 for these dual segmentation jobs. Finally, these techniques are excitingly friendly to budget conscious scientific research organizations where probabilistic algorithms such as BLAST might discourage attempts at greater certainty because single runs represent a major resource drain. If a job that used to take 24 days can now be completed in less than an hour or on a space available basis (which is the case at CDRH), repeated runs for more exhaustive analyses can be usefully contemplated. [ABSTRACT FROM AUTHOR]

A graph is a very important structure to describe many applications in the real world. In many applications, such as dependency graphs and debt graphs, it is an important problem to find and remove cycles to make these graphs be cycle-free. The common algorithm often leads to an out-of-memory exception in commodity personal computer, and it cannot leverage the advantage of multicore computers. This paper introduces a new problem, cycle detection and removal with vertex priority. It proposes a multithreading iterative algorithm to solve this problem for large-scale graphs on personal computers. The algorithm includes three main steps: simplification to decrease the scale of graph, calculation of strongly connected components, and cycle detection and removal according to a pre-defined priority in parallel. This algorithm avoids the out-of-memory exception by simplification and iteration, and it leverages the advantage of multicore computers by multithreading parallelism. Five different versions of the proposed algorithm are compared by experiments, and the results show that the parallel iterative algorithm outperforms the others, and simplification can effectively improve the algorithm's performance. [ABSTRACT FROM AUTHOR]

Earth observation data are typically compressed using general-purpose single-threaded compression algorithms that operate at a fraction of the bandwidth of modern storage and processing systems. We present evidence that recently developed multi-threaded compression codecs offer substantial benefits over widely used single-threaded codecs in terms of compression efficiency when applied to a selection of moderate resolution imaging spectroradiometer (MODIS) datasets stored in the HDF5 format. Compression codecs from the LZ77 and Rice families are shown to vary in efficacy when applied to different MODIS data products, highlighting the need for compression strategies to be tailored to different classes of data. We also introduce LPC-Rice, a new multi-threaded codec, that performs particularly well when applied to time-series data. [ABSTRACT FROM AUTHOR]

An enormous effort had been placed for converting sequential code to parallel in an automated way. In this regard, the frameworks like JOMP and JaMP, were proposed to facilitate Java programmers for parallelization of code. However, the programmer was still bound to provide directives to the compiler about possibly parallel portion of code and architectural specification in some predefined format. Moreover, these frameworks required source code as input, thereby constraining performance improvement subject to the availability of the source code. This paper proposed a framework called Hybrid Java Parallelizer (HJP) which was aimed at performance improvement through parallelization of Java code. It did not require source code for parallelization and was able to create threads according to the available cores. Experimentation was performed on the well-known matrix multiplication benchmark. Results showed that HJP achieved average speed-ups of 6.99, 3.54, and 6.98 times on machines having Intel Corei7, Core i5, and Xeon based processors, respectively. [ABSTRACT FROM AUTHOR]

To solve, manage and analyze biological problems using computer technology is called bioinformatics. With the emergent evolution in computing era, the volume of biological data has increased significantly. These large amounts of data have increased the need to analyze it in reasonable space and time. DNA sequences contain basic information of species, and pattern matching between different species is an important and challenging issue to cope with. There exist generalized string matching and some specialized DNA pattern matching algorithms in the literature. There is still need to develop fast and space efficient pattern matching algorithms that consider new hardware development. In this paper, we present a novel DNA sequences pattern matching algorithm called EPMA. The proposed algorithm utilizes fixed length 2-bits binary encoding, segmentation and multi-threading. The idea is to find the pattern with multiple searcher agents concurrently. The proposed algorithm is validated with comparative experimental results. The results show that the new algorithm is a good candidate for DNA sequence pattern matching applications. The algorithm effectively utilizes modern hardware and will help researchers in the sequence alignment, short read error correction, phylogenetic inference etc. Furthermore, the proposed method can be extended to generalized string matching and their applications. [ABSTRACT FROM AUTHOR]

Recently, the graphic processing units (GPUs) are becoming increasingly popular for the high performance computing applications. Although the GPUs provide high peak performance, exploiting the full performance potential for application programs, however, leaves a challenging task to the programmers. When launching a parallel kernel of an application on the GPU, the programmer needs to carefully select the number of blocks (grid size) and the number of threads per block (block size). These values determine the degree of SIMD parallelism and the multithreading, and greatly influence the performance. With a huge range of possible combinations of these values, choosing the right grid size and the block size is not straightforward. In this paper, we propose a mathematical model for tuning the grid size and the block size based on the GPU architecture parameters. Using our model we first calculate a small set of candidate grid size and block size values, then search for the optimal values out of the candidate values through experiments. Our approach significantly reduces the potential search space instead of exhaustive search approaches in the previous research. Thus our approach can be practically applied to the real applications. [ABSTRACT FROM AUTHOR]

As the need for multicore-aware programmers rises in both science and industry, Computer Science departments in universities around the USA are having to rethink their parallel computing curriculum. At Rice University, this rethinking took the shape of COMP 322, an introductory parallel programming course that is required for all Bachelors students. COMP 322 teaches students to reason about the behavior of parallel programs, educating them in both the high level abstractions of task-parallel programming as well as the nitty gritty details of working with threads in Java. In this paper, we detail the structure, principles, and experiences of COMP 322, gained from 6 years of teaching parallel programming to second-year undergraduates. We describe in detail two particularly useful tools that have been integrated into the curriculum: the HJlibparallel programming library and the Habanero Autograder for parallel programs. We present this work with the hope that it will help augment improvements to parallel computing education at other universities. [ABSTRACT FROM AUTHOR]

By introducing parallelism in introductory programming courses, all computer science students can receive a basic understanding of this crucial topic. Such an early introduction, however, has many challenges. This paper first presents a fall 2013 comparison of two Computer Science I (CS1) sections, leading to a conclusion emphasizing the importance of devoting sufficient time to a sufficiently small set of parallelism topics. Six additional CS1 sections are then considered, offered from spring 2014 through spring 2016 by three different instructors. Five of these removed coverage of Java thread programming due to challenges found in fall 2013, only to show measurably reduced effectiveness of the parallelism module. Thus a new thread programming integration strategy is presented, as done in spring 2016. This strategy includes active out-of-class activities that split the disparate challenges of Java thread programming into distinct exercises. Results demonstrate improved student interest and learning. [ABSTRACT FROM AUTHOR]

We present accurate time and energy piece-wise models of high-performance multi-threaded implementations for the general matrix multiplication, triangular system solve with multiple right-hand sides, and symmetric rank- k update. Furthermore, these are then assembled to provide accurate models of the Cholesky factorization built on top of these Level-3 BLAS operations. Our models consider the costs, in terms of time and energy, of the floating-point operations involved in the routines as well as the overhead due to data movements across the levels of the memory hierarchy. The accuracy of the multi-threaded models is tested on an Intel Xeon E5-2620 processor, reporting relative errors for the Cholesky factorization that are, respectively, around 2.4 and 2.9 % on average for time and energy. [ABSTRACT FROM AUTHOR]

Deterministic multithreading is a promising new research area that aims to enable reproducible deterministic execution of multithreaded applications. Some of the proposed approaches can render data races deterministic. In this study, the authors introduce the intention preservation problem in multithreaded applications and point out that existing deterministic multithreading approaches do not always preserve the program intention. While it is desirable to automatically capture the full intention of a program and preserve it in deterministic multithreading, it might be an intractable problem. Instead, they provide a partial solution for two specific cases. In the first case, they aim to preserve the program intention for read and write operations on primitive types by tracking read–write causality. In the second case, they preserve the program intention for concurrent write operations on ordered collection types by applying an operational transformation. [ABSTRACT FROM AUTHOR]

The ASDEX Upgrade Discharge Control System (DCS) is a distributed real-time control system executing complex control and monitoring tasks. Up to now, DCS control algorithms have been implemented by coding dedicated application processes with the C++ programming language. Algorithm changes required code modification, compilation and commissioning which only experienced programmers could perform. This was a significant constraint of flexibility for both control system operation and design. The new approach extends DCS with the capability of configuration-defined control algorithms. These are composed of chains of small, configurable standard function blocks providing general purpose functions like algebraic operations, filters, feedback controllers, output limiters and decision logic. In a later phase a graphical editor could help to compose and modify such configuration in a Simulink-like fashion. Building algorithms from standard functions can result in a high number of elements. In order to achieve a similar performance as with C++ coding, it is essential to avoid administrative bottlenecks by design. As a consequence, DCS executes a function block chain in the context of a single real-time thread of an application process. No concurrency issues as in a multi-threaded context need to be considered resulting in strongly simplified signal handling and zero performance overhead for inter-block communication. Instead of signal-driven synchronization, a block scheduler derives the execution sequence automatically from the block dependencies as defined in the configuration. All blocks and connecting signals are instantiated dynamically, based on definitions in a configuration file. Algorithms thus are not defined in the code but only in the configuration. The concept has been developed in view of Simulink block libraries and MARTe General Application Modules (GAM) but extends these with the DCS virtues of distributed computing and multi-threading. With growing diversity of general-purpose blocks the DCS framework will reach an unprecedented degree of universality and flexibility. Configuration-defined algorithms will gradually replace many existing DCS applications. Finally, the concept might also become of interest for the upcoming ITER plasma control system. [ABSTRACT FROM AUTHOR]

Asymmetric multicore processors have recently emerged as an appealing technology for severely energy-constrained environments, especially in mobile appliances where heterogeneity in applications is mainstream. In addition, given the growing interest for low-power high performance computing, this type of architectures is also being investigated as a means to improve the throughput-per-Watt of complex scientific applications on clusters of commodity systems-on-chip. In this paper, we design and embed several architecture-aware optimizations into a multi-threaded general matrix multiplication ( gemm), a key operation of the BLAS, in order to obtain a high performance implementation for ARM big.LITTLE AMPs. Our solution is based on the reference implementation of gemm in the BLIS library, and integrates a cache-aware configuration as well as asymmetric-static and dynamic scheduling strategies that carefully tune and distribute the operation's micro-kernels among the big and LITTLE cores of the target processor. The experimental results on a Samsung Exynos 5422, a system-on-chip with ARM Cortex-A15 and Cortex-A7 clusters that implements the big.LITTLE model, expose that our cache-aware versions of gemm with asymmetric scheduling attain important gains in performance with respect to its architecture-oblivious counterparts while exploiting all the resources of the AMP to deliver considerable energy efficiency. [ABSTRACT FROM AUTHOR]

Single‐ISA heterogeneous multi‐core processors trade‐off power with performance; however, threads that co‐run on shared resources suffer from resource contention, which induces performance degradation and energy inefficiency. The authors introduce a novel approach to optimise the co‐scheduling of multi‐threaded applications on heterogeneous processors. The approach is based on the concept of stakes function, which represents the trade‐off between isolation and sharing of resources. The authors also develop a co‐scheduling algorithm that use stakes functions to optimise resource usage while mitigating resource contention, thus improving performance and energy efficiency. They validated the approach using applications from the Princeton Application Repository for Shared‐Memory Computers (PARSEC) benchmark suite, obtaining up to 12.88% performance speed‐up, 13.65% energy speed‐up and 28.29% energy delay speed‐up with respect to the standard Linux heterogeneous multi‐processing scheduler. [ABSTRACT FROM AUTHOR]

Incomplete LU (ILU) preconditioning is typically used when an iterative solver is applied on an asymmetric system of linear equations. A fill-in selection policy significantly affects the ILU preconditioned iterative solver. In this study, by introducing a new fill-in control method based on blocks into ILU preconditioning, we propose a new ILU preconditioning method called ILUB preconditioning. In this method, the effect of the permitted fill-ins on the solver convergence is fully exploited because the resulting preconditioner matrix involves dense matrix blocks that can be processed efficiently using SIMD instructions. We implemented sequential and parallel ILUB preconditioned GMRES solvers and evaluated the solver performance in numerical tests. The numerical results demonstrated that ILUB preconditioning outperformed conventional ILU(0) preconditioning. [ABSTRACT FROM AUTHOR]

With a lot of enhanced coding tools introduced, High Efficiency Video Coding (HEVC) achieves significant improvement in coding efficiency at the cost of increased computational complexity. To efficiently reduce the encoding time of HEVC, a wavefront-based high parallel (WHP) solution integrating novel data-level and task-level methods is proposed in this paper. On data level, optimal single-instruction-multiple-data algorithms are designed for the enhanced coding tools, i.e., replacing the multiplication in motion compensation by add and shift operations with reduced instruction cycles, removing the transpose in transform via realignment of coefficients, and minimizing the memory access in sum of absolute difference/sum of squared differences calculation by fully reusing the registers. On task level, a novel inter-frame wavefront (IFW) method is developed by effectively decreasing the dependence of wavefront parallel processing (WPP). In addition, a coding tree block level parallelism analysis method is presented to prove the superior of IFW method compared with other HEVC representative parallel methods. Besides, a three-level thread management scheme is proposed to best exploit the parallelism of IFW method and achieve corresponding encoding speedup. Extensive experimental results show that, the overall WHP solution can bring up to $57.65\times $ , $65.55\times $ , and $88.17\times $ speedup for HEVC encoding of Wide Video Graphics Array, 720p and 1080p standard test sequences, while maintaining the same coding performance as with WPP. The proposed solution is also applied in several leading video companies in China, providing HEVC video service for more than 1.3 million users everyday. [ABSTRACT FROM PUBLISHER]

In this paper we demonstrate the methodology for parallelizing the computation of large one-dimensional discrete fast Fourier transforms (DFFTs) on multi-core Intel Xeon processors. DFFTs based on the recursive Cooley–Tukey method have to control cache utilization, memory bandwidth and vector hardware usage, and at the same time scale across multiple threads or compute nodes. Our method builds on a single-threaded Intel Math Kernel Library (MKL) implementation of real-to-complex DFFT, and uses the Intel Cilk Plus framework for thread parallelism. We demonstrate the ability of Intel Cilk Plus to handle parallel recursion with nested loop-centric parallelism without tuning the code to the number of cores or cache metrics. The result of our work is a library called EFFT that performs 1D DFTs of size 2 N for N ≥ 21 faster than the corresponding Intel MKL parallel DFT implementation by up to 1.5 × , and faster than FFTW by up to 2.5x. The code of EFFT is available for free download under the GPLv3 license. This work provides a new efficient DFFT implementation, and at the same time demonstrates an educational example of how computer science problems with complex parallel patterns can be optimized for high performance using the Intel Cilk Plus framework. [ABSTRACT FROM AUTHOR]

Human cytogenetic data are the typical laboratory results from hospitals. Karyogram is used to show the chromosome characteristics. The characteristics are written as karyotype strings. For a particular patient, there may be many records of karyotype strings due to several visits. These data for many patients are increasingly large and must be stored properly for further investigation and analysis. This research introduces the information system for the hospital for keeping the karyotypes of patients and applies the parallel method for searching required karyotypes, extracting related patient information. Particularly, we exploit the technology of Node.js with multithreads while splitting queries to search in parallel. The search method is integrated to the cytogenetic information system which is aimed to use for studying karyotypes of leukemia patients. [ABSTRACT FROM AUTHOR]