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The recent shift toward wire pipelining (WP) mandated by technological factors has attracted attention toward latency-controlled floorplanning. However, no systematic study has been published so far that takes into account block and logic-delay limitations. This paper aims at filling the gap by showing that block delay can limit and possibly prevent any real gain WP might promise. In this paper, the authors also show how a modified adaptive WP scheme, on the other hand, allows relevant gains. They built a SoC floorplanner based on the use of adaptive and nonadaptive WP, which optimizes the data rate, taking block delay into account. The results of new and old WP techniques applied on benchmarks and on an MPEG decoder are compared to the optimal results obtained when no WP is employed. [ABSTRACT FROM AUTHOR]

The size of future high-performance SoC is such that the time-of-flight of wires connecting distant pins in the layout can be much higher than the clock period. In order to keep the frequency as high as possible, the wires may be pipelined. However, the insertion of flip-flops may alter the throughput of the system due to the presence of loops in the logic netlist. In this paper, we address the problem of floorplanning a large design where long interconnects are pipelined by inserting the throughput in the cost function of a tool based on simulated annealing. The results obtained on a series of benchmarks are then validated using a simple router that breaks long interconnects by suitably placing flip-flops along the wires. [ABSTRACT FROM AUTHOR]

In this paper, we address the problem of designing very high-throughput finite-state machines (FSMs). The presence of loops in sequential circuits prevents a straightforward application of pipelining to increase performance. We observe that appropriate extensions of the "wave steering" technique can partially overcome the problem. We find that FSM decomposition theory is useful for decoupling the state-variable dependencies. Experiments on MCNC benchmarks show a 217 percent improvement in throughput, at the expense of a similar increase in area (2.15 times). Latency loss is relatively small, on the order of 20 percent, as compared to standard cell implementations. [ABSTRACT FROM AUTHOR]

The super-KEKB B factory, currently under construction at the KEK High Energy Accelerator Research Organization in Japan, has a goal of producing 50 ab^-1 of integrated luminosity, thus allowing the Belle II experiment to study rare decays of B mesons, D mesons, and \tau leptons. Such large statistics on these decays provide an experimental probe of physics beyond the Standard Model. An online trigger system is indispensable to Belle II to reduce the number of beam background events associated with high electron and positron beam currents, as well as to enhance physics-oriented events. For this purpose, we have designed the Belle II online trigger system with two kinds of primary Level 1 trigger components: a track trigger and an energy trigger. The track trigger is composed of 2-dimensional and 3-dimensional tracking algorithms, and the energy trigger implements algorithms based on total energy, isolated clusters, and identification of Bhabha events. In addition, precise event trigger timing and muon tagging information are provided by the time-of-propagation detector and iron flux return muon detector, respectively. [ABSTRACT FROM PUBLISHER]

The Time-Of-Propagation detector is a Cherenkov particle identification detector based on quartz radiator bars for the Belle II experiment at the SuperKEKB e + e − − collider. The purpose of the detector is to identify the type of charged hadrons produced in e + e − − collisions, and requires a single photon timing resolution below 100 picoseconds. A novel front-end electronic system was designed, built, and integrated to acquire data from the 8192 microchannel plate photomultiplier tube channels in the detector. Waveform sampling of these analog signals is done by switched-capacitor array application-specific integrated circuits. The processes of triggering, digitization of windows of interest, readout, and data transfer to the Belle II data acquisition system are managed by Xilinx Zynq-7000 programmable system on a chip devices. [ABSTRACT FROM AUTHOR]