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The Booth multipliers require lower number of addition operations compared to the traditional multipliers. Further, higher radix Booth multiplier requires lesser number of adders in its circuit implementation. Multiply and accumulate (MAC) unit plays a crucial role in digital signal processing circuits. Handling the data in area-efficient MAC circuits is challenging since the data word length closely doubles on each multiplication. The data path of higher word length possesses higher hardware complexity. However, such hardware complexity can be minimized by deploying the fixed-width multipliers (FWM) in MAC circuits. In FWMs, the multiplication result of X L - bits × Y L - bits is rounded to the higher significant L bits by truncating the rest of lower significant bits. Nevertheless, this truncation introduces the error in multiplication result. This paper presents a radix-8 Booth-based fixed-width signed multipliers with error compensation. Moreover, the estimation of bias value for the error compensation in radix-8 Booth FWM is presented. Accuracy of the fixed-width multiplication with the proposed compensation is analyzed. In addition, the multiplier circuits based on the proposed methods are designed and implemented and the experimental results are discussed. [ABSTRACT FROM AUTHOR]

This study presents a variable length multi‐path delay commutator fast Fourier transform (FFT)/inverse FFT (IFFT) architecture for a multiple input multiple output orthogonal frequency division multiplexing system. It supports the FFT/ IFFT lengths of 512/256/128/64 samples to process each symbol carried by eight spatial streams and achieves a speed of 160 MHz to meet the IEEE 802.11ac timing requirements. A resource scheduling methodology to minimise the hardware complexity of the design is proposed and adopted in the architecture presented. A novel stagger word length strategy is also proposed and applied to achieve the better accuracy with lesser hardware. Here, the signal to quantisation noise ratio of 57.23 dB is obtained. The twiddle coefficient storage space is significantly compressed to achieve the coefficient generation with reduced hardware. The design is implemented using the TSMC‐65 nm complementary metal oxide semiconductor technology with a supply voltage of 1 V at 160 MHz. The implementation results show that the architecture has a gate count of 3,48,013 with power consumption of 105.1 mW and area of 0.492 mm2. The hardware complexity and performance of the design are compared with earlier reported architectures. It is observed that the proposed design achieves better performance in terms of hardware complexity and normalised energy for the given specifications. [ABSTRACT FROM AUTHOR]

The IEEE 802.11ac is the recently ratified standard developed for the fifth generation wireless fidelity technology, in which the multi‐user (MU) multiple‐input multiple‐output orthogonal frequency division multiplexing (MIMO‐OFDM) technique is adopted for the high data rate communication. In an MIMO‐OFDM System, the forward/inverse fast Fourier transform (FFT/IFFT) processor is a key component. On proper reception, the reordering and scheduling of data is important for the optimal utilisation of butterfly resources in the pipelined FFT/IFFT processor. In this study, a mathematical model for an eight‐parallel multimode (N = 512/256/128/64) multi‐path delay commutator‐based FFT/IFFT processor which is suitable for the IEEE 802.11ac compliant MU‐MIMO‐OFDM system is presented. On the other hand, the data reordering, scheduling methodologies and its architectures are proposed for the pre‐, post‐FFT/IFFT process are proposed. The design implementations are done using TSMC 65 nm complementary metal–oxide–semiconductor technology at 160 MHz. The power and area metrics with and without clock gating are compared. The clock gated implementation reports show that the power consumption is 17.44 mW for the pre‐transformed data reordering and 11.64 mW for the post‐transformed data reordering with an area occupation of 0.7694 mm2 and 0.5111 mm2, respectively. [ABSTRACT FROM AUTHOR]