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A transient waveform capture and digitization circuit with continuous synchronous 2-GHz sampling capability and real-time programmable windowed trigger generation has been fabricated and tested. Designed in 0.25 \mum CMOS, the digitizer contains a circular array of 128 sample and hold circuits for continuous sample acquisition, and attains 2-GHz sample speeds with over 800-MHz analog bandwidth. Sample clock generation is synchronous, combining a phase-locked loop for high-speed clock generation and a high-speed fully-differential shift register for distributing clocks to all 128 sample circuits. Using two comparators per sample, the sampled voltage levels are compared against two reference levels, a high threshold and a low threshold, that are set via per-comparator digital to analog converters (DACs). The 256 per-comparator 5-bit DACs compensate for comparator offsets and allow for fine reference level adjustment. The comparator results are matched in 8-sample-wide windows against up to 72 programmable patterns in real time using an on-chip programmable logic array. Each 8-sample trigger window is equivalent to 4 ns of acquisition, overlapped sample by sample in a circular fashion through the entire 128-sample array. The 72 pattern-matching trigger criteria can be programmed to be any combination of High—above the high threshold, Low—below the low threshold, Middle—between the two thresholds, or “Don't Care”—any state is accepted. A trigger pattern of “HLHLHLHL,” for example, watches for a waveform that is oscillating at about 1 GHz given the 2-GHz sample rate. A trigger is flagged in under 20 ns if there is a match, after which sampling is stopped, and on-chip digitization can proceed via 128 parallel 10-bit converters, or off-chip conversion can proceed via an analog readout. The chip exceeds 11 bits of dynamic range, nets over 800-MHz -3-dB bandwidth in a realistic system, and jitter in the PLL-based sampling clock has been measured to be about 1 part per million, RMS. [ABSTRACT FROM AUTHOR]

The ARIANNA experiment will observe high-energy cosmogenic neutrino signatures via a large array of autonomous radio listening stations dispersed on the Ross Ice Shelf in Antarctica. Each station in the projected array of 900 stations will contain RF antennas, amplifiers, digitization, real-time triggering circuitry, a CPU with solid-state data storage, and redundant remote communications paths. Power is provided by both sun and wind. Two prototype stations have been installed, with a hexagonal array of seven stations, with each positioned 1 km apart, due for deployment over the next two seasons. The station's core data acquisition system includes four channels of analog sampling circuits that operate at 2 GHz and achieve over 11 bits of dynamic range. These circuits sample continuously over a 128-sample circular analog storage array. The circuits use a phase-locked loop to generate the 2 GHz internal sample clocking from a \sim 30 MHz external clock. Unlike most previous such designs, the high-speed sample clocking is completely synchronous and has very high timing stability, with about 1 ppm RMS jitter. The sampling circuits include the ability to produce a real-time trigger based on pattern-matching of the incoming waveform. Up to 72 patterns can be searched for in parallel, and each pattern looks at 8 consecutive samples, requiring that any or all of the samples be above a high threshold, below a separate low threshold, in-between the two thresholds, or a “don't care” condition. Each station also includes computing and solid-state event storage, environmental monitoring of voltage and power consumption, wind and temperature conditions, and both long-distance wireless to McMurdo Station and Iridium satellite communications. For the 2011–2012 austral season, about 1.4 million events were acquired between the second station's installation on December 21, 2011 and March 15, 2012. [ABSTRACT FROM PUBLISHER]

A monolithic solid-state linear sensor array has been designed and fabricated in a 0.35 μm, 3.3 V, thin-oxide digital CMOS process. The sensor arrays are targetted at such instruments and applications as digital streak cameras, 2-D cameras for proton radiography, and fiber-optic array readout. The prototype consists of a I-D linear array of 150 integrated photodiodes, followed by fast analog buffers and on-chip, 150-deep analog frame storage. Frame storage consists of 150 analog sample circuits per pixel, with each sample circuit including an n-channel sample switch, a 0.1 pF double- polysilicon sample capacitor, a reset switch to clear the capacitor, and a multiplexed source-follower readout buffer. Sampling speeds of 400 M-frames/s have been achieved using electrical input signals, and 100 MHz with optical input signals, both with a dynamic range of ∼11.5 bits, rms. Circuit design details are presented, along with the results of electrical measurements and optical experiments with fast pulsed laser light sources at several wavelengths. A set of next-generation concept designs are also presented that aims to include PLL-based clock multiplication for 1 GHz continuous sampling, plus a new real-time trigger circuit technique that examines windowed regions of stored samples to form a sophisticated trigger decision. [ABSTRACT FROM AUTHOR]

Monolithic CMOS cameras for direct imaging in electron microscopy and other radiation imaging applications have been developed and have been used to capture images with high signal to noise and resolution. Based on CMOS Active Pixel Sensor (APS) technology, the arrays use an 8 to 20 μm epitaxial layer that acts as a thicker sensitive region for the liberation and collection of ionization electrons resulting from impinging charged particles. This results in a 100% fill factor and a far larger signal per incident charged particle than a typical CMOS photodiode could provide. The per-pixel CDS scheme discussed in this paper has demonstrated reductions in kT/C noise by a factor of four, to 11 electrons RMS at room temperature. The CDS scheme requires only one read instead of the two reads plus pre- and post-integration subtraction required by traditional CDS, and is hence faster than alternate schemes. In addition, the test device was used in the observation of Random Telegraph Signal noise (RTS) in small-capacitance pixels under different Vgs conditions. [ABSTRACT FROM AUTHOR]

Abstract: Direct-detection CMOS image sensors optimized for charged-particle imaging applications, such as electron microscopy and particle physics, have been designed, fabricated and characterized. These devices directly image charged particles without reliance on image-degrading hybrid technologies such as the use of scintillating materials. Based on standard CMOS Active Pixel Sensor (APS) technology, the sensor arrays use an 8–20μm thick epitaxial layer that acts as a sensitive region for the generation and collection of ionization electrons resulting from impinging high-energy particles. A range of optimizations to this technology have been developed via simulation and experimental device design. These include the simulation and measurement of charge-collection efficiency vs. recombination, effect of diode area and stray capacitance vs. signal gain and noise, and the effect of different epitaxial silicon depths. Several experimental devices and full-scale prototypes are presented, including two prototypes that systematically and independently vary pixel pitch and diode area, and a complete high-resolution camera for electron microscopy optimized through experiment and simulation. The electron microscope camera has 1×1k2 pixels with a 5μm pixel pitch and an 8μm epitaxial silicon thickness. [Copyright &y& Elsevier]

Abstract: CMOS image sensors optimized for charged particle imaging applications, such as electron microscopy and particle physics, have been designed and characterized. These directly image charged particles without reliance on performance-degrading hybrid technologies such as the use of scintillating materials. Based on standard CMOS active pixel sensor (APS) technology, the sensor arrays uses an 8–20μm epitaxial layer that acts as a thicker sensitive region for the generation and collection of ionization electrons resulting from impinging high-energy particles. This results in a 100% fill factor and a far larger signal per incident electron than a standard CMOS photodiode could provide. A 512×550 pixels prototype has been fabricated and used extensively in an electron microscope, including having been used to take sample images. Temporal noise was measured to be 0.9mV RMS, and the dynamic range was 60dB. Power consumption at 70frames/s is 20mW. The full-width half-maximum of the collected ionization electron distribution was found to be 5.5μm, yielding a spatial resolution of approximately 2.3μm for individual incident electrons, and the modulation transfer function of the sensor at the Nyquist limit is to be 32%. [Copyright &y& Elsevier]

Three novel integrated CMOS active pixel sensor circuits for vertex detector applications have been designed with the goal of increased signal-to-noise ratio and speed. First, a large-area native epitaxial silicon photogate sensor was designed to increase the charge collected per hit pixel and to reduce charge diffusion to neighboring pixels. High charge to voltage conversion is maintained by subsequent charge transfer to a low capacitance readout node. Second, a per-pixel correlated double sampling kT/C reset noise reduction circuit was tested. It requires only one read, as compared to two for typical double sampling in active pixel sensors, and no off-pixel storage or subtraction is needed, The technique reduced input-referred temporal noise by a factor of 2.5 to a measured 15.6 e-, rms. Finally, a column-level active reset technique was designed that suppresses kT/C reset noise. It reduced noise by up to a factor of 7.6, to an estimated 8.3 input-referred electrons, rms. The technique also dramatically reduces fixed pattern (pedestal) noise, by up to a factor of 21. This may reduce pixel-by-pixel pedestal differences enough to permit sparse data scan without per-pixel offset corrections. [ABSTRACT FROM AUTHOR]

Two CMOS image sensor circuit prototypes equipped with in situ frame storage have been fabricated and tested. Capable of 4-400 M-frames/s and between 66 and 79 dB rms dynamic range, these developments are intended for the capture of fast, brief, transient events with high resolution. Applications include accelerator-based flash radiography such as proton radiography [1]. The first is a small two-dimensional (2-D) prototype in which each pixel includes either a capacitive trans-impedance amplifier or a direct-integration source-follower front end, followed by an array of 64 frame storage sample capacitors and associated readout electronics. The acquisition of either 32 frames using correlated double sampling (CDS) at 4 M-frames/s, or 64 frames without CDS at up to 10.5 M-frames/s (-3 dB), and up to 13 b dynamic range was achieved. The second is a monolithic solid state "streak camera:," a 1-D linear array of 150 photo diodes, with a 150-frame analog storage array. This device reached 400-M-frames/s operation with electrical test inputs, at least 100-M-frames/s operation with optical inputs, and achieves over 11 b of dynamic range. These circuits demonstrate the high performance possible with CMOS sensor circuits containing in situ frame storage. [ABSTRACT FROM AUTHOR]

Deals with a study which designed, tested and fabricated a series of multichannel transient waveform digitization integrated circuits with up to 5 GHz sample rates and parallel 10-bit digitization in large quantities. Sample circuit configurations; Simulated analog sampling performance; Sample clock generation.

Abstract: A prototype direct detection device (DDD) camera system has shown great promise in improving both the spatial resolution and the signal to noise ratio for electron microscopy at 120–400keV beam energies (Xuong et al., 2007. Methods in Cell Biology, 79, 721–739). Without the need for a resolution-limiting scintillation screen as in the charge coupled device (CCD), the DDD camera can outperform CCD based systems in terms of spatial resolution, due to its small pixel size (5μm). In this paper, the modulation transfer function (MTF) of the DDD prototype is measured and compared with the specifications of commercial scientific CCD camera systems. Combining the fast speed of the DDD with image mosaic techniques, fast wide-area imaging is now possible. In this paper, the first large area mosaic image and the first tomography dataset from the DDD camera are presented, along with an image processing algorithm to correct the specimen drift utilizing the fast readout of the DDD system. [Copyright &y& Elsevier]

Deals with a study which discussed the design and testing of 2 generations of active pixel sensor chips. Chip configurations; Tests with Fe[sup55]; Effect of radiation.

This paper describes the hardware, firmware and software systems used in data acquisition for the NA61/SHINE experiment at the CERN SPS accelerator. Special emphasis is given to the design parameters of the readout electronics for the 40 m 3 volume Time Projection Chamber detectors, as these give the largest contribution to event data among all the subdetectors: events consisting of 8 bit ADC values from 256 time slices of 200 k electronic channels are to be read out with ~ 100 Hz rate. The data acquisition system is organized in “push-data mode”, i.e. local systems transmit data asynchronously. Techniques of solving subevent synchronization are also discussed. [ABSTRACT FROM AUTHOR]

Direct-detection CMOS image sensors optimized for charged-particle imaging applications, such as electron microscopy and particle physics, have been designed, fabricated and characterized. Based on standard silicon CMOS Active Pixel Sensor (APS) technology, the sensor arrays uses an 8 to 20 μm epitaxial layer that acts as a thicker sensitive region in the generation and collection of ionization electrons resulting from impinging high-energy particles. A range of optimizations to this technology have been developed via simulation and experimental device design. These include the simulation and measurement of charge collection efficiency versus recombination, effect of diode size and stray capacitance versus signal gain and noise, and the effect of different epitaxial silicon depths and the energy of incident electrons. Results from several experimental devices are presented and compared with simulations, including measurements from two prototypes that systematically and independently vary pixel pitch and diode area. [ABSTRACT FROM AUTHOR]

Abstract: A new high-resolution recording device for transmission electron microscopy (TEM) is urgently needed. Neither film nor CCD cameras are systems that allow for efficient 3-D high-resolution particle reconstruction. We tested an active pixel sensor (APS) array as a replacement device at 200, 300, and 400keV using a JEOL JEM-2000 FX II and a JEM-4000 EX electron microscope. For this experiment, we used an APS prototype with an area of 64×64 pixels of 20μm×20μm pixel pitch. Single-electron events were measured by using very low beam intensity. The histogram of the incident electron energy deposited in the sensor shows a Landau distribution at low energies, as well as unexpected events at higher absorbed energies. After careful study, we concluded that backscattering in the silicon substrate and re-entering the sensitive epitaxial layer a second time with much lower speed caused the unexpected events. Exhaustive simulation experiments confirmed the existence of these back-scattered electrons. For the APS to be usable, the back-scattered electron events must be eliminated, perhaps by thinning the substrate to less than 30μm. By using experimental data taken with an APS chip with a standard silicon substrate (300μm) and adjusting the results to take into account the effect of a thinned silicon substrate (30μm), we found an estimate of the signal-to-noise ratio for a back-thinned detector in the energy range of 200–400keV was about 10:1 and an estimate for the spatial resolution was about 10μm. [Copyright &y& Elsevier]

Abstract: Research has shown that Active Pixel CMOS sensors can detect charged particles. We have been studying whether this process can be used in a collider environment. In particular, we studied the effect of radiation with 55MeV protons. These results show that a fluence of about 2×1012 protons/cm2 reduces the signal by a factor of two while the noise increases by 25%. A measurement 6 months after exposure shows that the silicon lattice naturally repairs itself. Heating the silicon to 100°C reduced the shot noise and increased the collected charge. CMOS sensors have a reduced signal-to-noise ratio per pixel because charge diffuses to neighboring pixels. We have constructed a photogate to see if this structure can collect more charge per pixel. Results show that a photogate does collect charge in fewer pixels, but it takes about 15ms to collect all of the electrons produced by a pulse of light. [Copyright &y& Elsevier]

We describe work that extends three-dimensional (3-D) patterned overlay high-density interconnect (HDI) to high-performance imaging applications. The work was motivated by the rigorous requirements of the multiple-pulse imager for dynamic proton radiography. The optical imager has to provide large (>90%) optical fill factor, high quantum efficiency, 200-ns inter-frame time interval, and storage for >32 frames. In order to accommodate the massively parallel electronics including the signal storage for a large number of frames, it is necessary to provide novel 3-D interconnect and packaging architectures. Recently, a 3-D interconnect technology was successfully demonstrated to assemble a stack of 50 signal-processing chips into a cube. Each chip contained test connections (interconnect continuity only) simulating 160 channels of pixel read-out electronics. Test cube assemblies, based on these mock-up integrated circuits, have been fabricated to explore the feasibility of constructing functional cube arrays. A novel 3D integrated sensor-electronics (mirror-cube) imager architecture is proposed. We also briefly review progress in the custom fast image-processing electronics. [ABSTRACT FROM AUTHOR]