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As technology nodes continue to shrink, layout patterns become more sensitive to lithography processes, resulting in lithography hotspots that need to be identified and eliminated during physical verification. We propose an accurate hotspot detection approach based on principal component analysis-support vector machine classifier. Several techniques, including hierarchical data clustering, data balancing, and multilevel training, are provided to enhance the performance of the proposed approach. Our approach is accurate and more efficient than conventional time-consuming lithography simulation and provides a high flexibility for adapting to new lithography processes and rules. [ABSTRACT FROM AUTHOR]

Recently, directed self-assembly (DSA) has emerged as a promising lithography solution for cut manufacturing. We perform a comprehensive study on the DSA aware mask optimization problem to provide a DSA friendly design on cut layers. We first formulate the problem as an integer linear programming (ILP) to assign cuts to different guiding templates, targeting both conflict minimization and line-end extension minimization. As ILP may not be scalable for very large size problems, we then propose two speed-up strategies. The first one is to decompose the initial problem into smaller ones and solve them separately, followed by solution merging without much loss of quality. The second one is using the set cover algorithm to decide the DSA guiding pattern assignment, and then legalize the template placement. Our approaches can be naturally extended to handle arbitrary DSA guiding template patterns with complicated shapes. Experimental results show that our methodologies can significantly improve the DSA friendly, i.e., both the unresolved pattern number and the line-end extensions can be reduced. [ABSTRACT FROM AUTHOR]

Triple patterning lithography (TPL) is one of the most promising techniques in the 14-nm logic node and beyond. Conventional LELELE type TPL technology suffers from native conflict and overlapping problems. Recently, as an alternative process, TPL with end-cutting (LELE-EC) was proposed to overcome the limitations of LELELE manufacturing. In the LELE-EC process, the first two masks are LELE type double patterning, while the third mask is used to generate the end-cuts. Although the layout decomposition problem for LELELE has been well studied in the literature, only a few attempts have been made to address the LELE-EC layout decomposition problem. We propose a comprehensive study for LELE-EC layout decomposition. Layout graph and end-cut graph are constructed to extract all the geometrical relationships of both input layout and end-cut candidates. Based on these graphs, integer linear programming is formulated to minimize the conflict and the stitch numbers. The experimental results demonstrate the effectiveness of the proposed algorithms. [ABSTRACT FROM AUTHOR]