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Network congestion is one of the critical reasons for degradation of data throughput performance in Networks-on-Chip (NoCs), with delays caused by data-buffer queuing in routers. Local buffer or router congestion impacts on network performance as it gradually spreads to neighbouring routers and beyond. In this paper, we propose a novel approach to NoC traffic prediction using Spiking Neural Networks (SNNs) and focus on predicting local router congestion so as to minimize its impact on the overall NoCs throughput. The key novelty is utilizing SNNs to recognize temporal patterns from NoC router buffers and predicting traffic hotspots. We investigate two neural models, Leaky Integrate and Fire (LIF) and Spike Response Model (SRM) to check performance in terms of prediction coverage. Results on prediction accuracy and precision are reported using a synthetic and real-time multimedia applications with simulation results of the LIF based predictor providing an average accuracy of 88.28%–96.25% and precision of 82.09%–96.73% as compared to 85.25%–95.69% accuracy and 73% and 98.48% precision performance of SRM based model when looking at congestion formations 30 clock cycles in advance of the actual hotspot occurrence. • A novel use of SNN to predict router-level congestion in NoC architectures. • We investigate two SNN models (LIF and SRM) to evaluate prediction coverage. • Results are formulated by using synthetic and real-time multimedia applications. • Proposed models provide better accuracy than existing NoC congestion predictors. [ABSTRACT FROM AUTHOR]

The significant decline in the cost of genome sequencing has dramatically changed the typical bioinformatics pipeline for analysing sequencing data. Where traditionally, the computational challenge of sequencing is now secondary to genomic data analysis. Short read alignment (SRA) is a ubiquitous process within every modern bioinformatics pipeline in the field of genomics and is often regarded as the principal computational bottleneck. Many hardware and software approaches have been provided to solve the challenge of acceleration. However, previous attempts to increase throughput using many-core processing strategies have enjoyed limited success, mainly due to a dependence on global memory for each computational block. The limited scalability and high energy costs of many-core SRA implementations pose a significant constraint in maintaining acceleration. The Networks-On-Chip (NoC) hardware interconnect mechanism has advanced the scalability of many-core computing systems and, more recently, has demonstrated potential in SRA implementations by integrating multiple computational blocks such as pre-alignment filtering and sequence alignment efficiently, while minimizing memory latency and global memory access. This article provides a state of the art review on current hardware acceleration strategies for genomic data analysis, and it establishes the challenges and opportunities of utilizing NoCs as a critical building block in next-generation sequencing (NGS) technologies for advancing the speed of analysis. [ABSTRACT FROM AUTHOR]

Hardware has become more prone to faults as a result of geometric scaling, wear‐out and faults caused during the manufacturing process, therefore, the reliability of hardware is reliant on the need to continually adapt to faults. A computational model of biological self‐repair in the brain, derived from observing the role of astrocytes (a glial cell found in the mammalian brain), has captured self‐repair within models of neural networks known as neuro‐glia networks. This astrocyte‐driven repair process can address the issues of faulty synapse connections between neurons. These astrocyte cells are distributed throughout a neuro‐glia network and regulate synaptic activity, and it has been observed in computational models that this can result in a fine‐grained self‐repair process. Therefore, mapping neuro‐glia networks to hardware provides a strategy for achieving self‐repair in hardware. The internal interconnecting of these networks in hardware is a challenge. Previous work has focused on addressing neuron to astrocyte communication (local), however, the global self‐repair process is dependent on the communication infrastructure between astrocyte‐to‐astrocyte; e.g. astrocyte network. This study addresses the key challenge of providing a scalable communication interconnect for global astrocyte network requirements and how it integrates with existing local communication mechanism. Area/power results demonstrate scalable implementations with the ring topology while meeting timing requirements. [ABSTRACT FROM AUTHOR]

Fault tolerance and adaptive capabilities are challenges for modern networks-on-chip (NoC) due to the increase in physical defects in advanced manufacturing processes. Two novel adaptive routing algorithms, namely coarse and fine-grained (FG) look-ahead algorithms, are proposed in this paper to enhance 2-D mesh/torus NoC system fault-tolerant capabilities. These strategies use fault flag codes from neighboring nodes to obtain the status or conditions of real-time traffic in an NoC region, then calculate the path weights and choose the route to forward packets. This approach enables the router to minimize congestion for the adjacent connected channels and also to bypass a path with faulty channels by looking ahead at distant neighboring router paths. The novelty of the proposed routing algorithms is the weighted path selection strategies, which make near-optimal routing decisions to maintain the NoC system performance under high fault rates. Results show that the proposed routing algorithms can achieve performance improvement compared to other state of the art works under various traffic loads and high fault rates. The routing algorithm with FG look-ahead capability achieves a higher throughput compared with the coarse-grained approach under complex fault patterns. The hardware area/power overheads of both routing approaches are relatively low which does not prohibit scalability for large-scale NoC implementations. [ABSTRACT FROM PUBLISHER]

A novel adaptive routing algorithm – Efficient Dynamic Adaptive Routing (EDAR) is proposed to provide a fault-tolerant capability for Networks-on-Chip (NoC) via an efficient routing path selection mechanism. It is based on a weighted path selection strategy, which exploits the status of real-time NoC traffic made available via monitor modules. The key performance goal is to maintain throughput under congested and faulty conditions via effective routing path decisions. In the proposed EDAR, port weights are calculated in real-time according to the channel status – Idle/Busy/Congested/Faulty, and the port with the lowest weighting is ranked as the near-optimal route to forward packets. This mechanism enables the router to bypass congested ports and tolerate faulty ports. To assess the latency and throughput of the proposed routing algorithm, several traffic patterns for both fault-free and faulty NoCs were evaluated. Results show that EDAR can achieve higher throughput compared to other state of the art routing algorithms under various traffic patterns and levels of injected faults. In addition, the hardware area overhead for EDAR is demonstrated to have a reasonably low cost which maintains scalability for large NoC implementations. [ABSTRACT FROM AUTHOR]

Abstract: A key requirement for modern Networks-on-Chip (NoC) is the ability to detect and diagnose faults and failures. This paper addresses the challenge of fault diagnosis using online testing where the interruption of the runtime operation (performance) under diagnosis is minimised. A novel Monitor Module (MM) is proposed to detect NoC interconnect faults which minimise the intrusion of the regular NoC traffic throughput by (1) using a channel tester which only examines NoC channels when they are idle; and (2) using a testing interval parameter based on the Binary Exponential Back off algorithm to dynamically balance the level of testing when recovering from temporary faults. The paper presents results on the minimal impact on NoC throughput for a range of testing conditions and also highlights the minimal area overhead of the MM (11.56%) compared with an adaptive NoC router implemented on FPGA hardware. Simulation results demonstrate non-intrusion of the NoC runtime traffic throughput when channel are fault free, and also how throughput loss is minimised when faults are identified. [Copyright &y& Elsevier]

Spiking neural networks (SNNs) attempt to emulate information processing in the mammalian brain based on massively parallel arrays of neurons that communicate via spike events. SNNs offer the possibility to implement embedded neuromorphic circuits, with high parallelism and low power consumption compared to the traditional von Neumann computer paradigms. Nevertheless, the lack of modularity and poor connectivity shown by traditional neuron interconnect implementations based on shared bus topologies is prohibiting scalable hardware implementations of SNNs. This paper presents a novel hierarchical network-on-chip (H-NoC) architecture for SNN hardware, which aims to address the scalability issue by creating a modular array of clusters of neurons using a hierarchical structure of low and high-level routers. The proposed H-NoC architecture incorporates a spike traffic compression technique to exploit SNN traffic patterns and locality between neurons, thus reducing traffic overhead and improving throughput on the network. In addition, adaptive routing capabilities between clusters balance local and global traffic loads to sustain throughput under bursting activity. Analytical results show the scalability of the proposed H-NoC approach under different scenarios, while simulation and synthesis analysis using 65-nm CMOS technology demonstrate high-throughput, low-cost area, and power consumption per cluster, respectively. [ABSTRACT FROM PUBLISHER]

Abstract: The brain is highly efficient in how it processes information and tolerates faults. Arguably, the basic processing units are neurons and synapses that are interconnected in a complex pattern. Computer scientists and engineers aim to harness this efficiency and build artificial neural systems that can emulate the key information processing principles of the brain. However, existing approaches cannot provide the dense interconnect for the billions of neurons and synapses that are required. Recently a reconfigurable and biologically inspired paradigm based on network-on-chip (NoC) and spiking neural networks (SNNs) has been proposed as a new method of realising an efficient, robust computing platform. However, the use of the NoC as an interconnection fabric for large-scale SNNs demands a good trade-off between scalability, throughput, neuron/synapse ratio and power consumption. This paper presents a novel traffic-aware, adaptive NoC router, which forms part of a proposed embedded mixed-signal SNN architecture called EMBRACE (EMulating Biologically-inspiRed ArChitectures in hardwarE). The proposed adaptive NoC router provides the inter-neuron connectivity for EMBRACE, maintaining router communication and avoiding dropped router packets by adapting to router traffic congestion. Results are presented on throughput, power and area performance analysis of the adaptive router using a 90 nm CMOS technology which outperforms existing NoCs in this domain. The adaptive behaviour of the router is also verified on a Stratix II FPGA implementation of a 4 × 2 router array with real-time traffic congestion. The presented results demonstrate the feasibility of using the proposed adaptive NoC router within the EMBRACE architecture to realise large-scale SNNs on embedded hardware. [Copyright &y& Elsevier]

Industrial manufacturing systems and processes- related courses cover subject areas that are as diverse as electrical and product engineering and industrial automation. The proliferation of Web-based distance education courses in this area in recent years poses unique challenges for the teaching of a discipline that traditionally involves a high level of practical work. Increasingly, Web-based distance education courses are on offer, augmented by the provision of remote experimentation laboratories facilitating distant access to campus-based physical resources. The design and implementation of effective and usable remote experimentation facilities is a difficult task, given the inherent complexities of the learning environment and the constraints imposed by a Web-based delivery medium. Developments in recent years have addressed many of these issues as this constant innovation has necessitated educational institutions and other training providers to continually reassess the content and delivery of engineering curricula in the context of this developing field. However, autonomous learning environments, by their very nature, offer minimal educator assistance, and from a student's perspective, it is inevitable that, at some stage of the experimental process, context-specific help will be required. This paper seeks to address this issue in relation to the practical aspect of Web-based engineering-related courses and presents an intelligent help system to support students in the practical use of autonomous learning environments for remote experimentation. [ABSTRACT FROM AUTHOR]

A novel memristive synapse model based on the HP memristor is proposed in this paper, which can address the problem of synaptic weight infinite modulations. The sliding threshold mechanism of the Bienenstock-Cooper-Munro rule (BCM) is used to redefine the memristance (i.e. synaptic weight) adjustment process of the memristive synapse model. Based on the proposed memristor-based synapse and Leaky Integrate-and-Fire neurons, a spiking neural network (SNN) hardware fragment is constructed, where spike trains with different frequencies are used to evaluate the stability performance of the proposed SNN hardware. Results show that compared to other approaches, the network is stable under different stimuli due to the characteristics of the memristor-based synapse model, and prove that the proposed synapse model is able to mimic biological synaptic behaviour and the problem of synaptic weight infinite modulations is addressed. [ABSTRACT FROM AUTHOR]

A biophysical model that captures molecular homeostatic control of ions at the perisynaptic cradle (PsC) is of fundamental importance for understanding the interplay between astroglial and neuronal compartments. In this paper, we develop a multi-compartmental mathematical model which proposes a novel mechanism whereby the flow of cations in thin processes is restricted due to negatively charged membrane lipids which result in the formation of deep potential wells near the dipole heads. These wells restrict the flow of cations to “hopping” between adjacent wells as they transverse the process, and this surface retention of cations will be shown to give rise to the formation of potassium (K+) and sodium (Na+) microdomains at the PsC. We further propose that a K+ microdomain formed at the PsC, provides the driving force for the return of K+ to the extracellular space for uptake by the neurone, thereby preventing K+ undershoot. A slow decay of Na+ was also observed in our simulation after a period of glutamate stimulation which is in strong agreement with experimental observations. The pathological implications of microdomain formation during neuronal excitation are also discussed. [ABSTRACT FROM AUTHOR]

Spiking Neural Network (SNN) is the most recent computational model that can emulate the behaviour of biological neuron system. However, its main drawback is that it is computationally intensive, which limits the system scalability. This paper highlights and discusses the importance and significance of emulating SNNs in hardware devices. A layer-level tile architecture (LTA) is proposed for hardware-based SNNs. The LTA employs a two-level sharing mechanism of computing components at the synapse and neuron levels, and achieves a trade-off between computational complexity and hardware resource costs. The LTA is implemented on a Xilinx FPGA device. Experimental results demonstrate that this approach is capable of scaling to large hardware-based SNNs. [ABSTRACT FROM AUTHOR]

Astrocytes display a highly complex, spongiform morphology, with their fine terminal processes (leaflets) exercising dynamic degrees of synaptic coverage, from touching and surrounding the synapse to being retracted from the synaptic region. In this paper, a computational model is used to reveal the effect of the astrocyte-synapse spatial relationship on ionic homeostasis. Specifically, our model predicts that varying degrees of astrocyte leaflet coverage influences concentrations of K+, Na+ and Ca2+, and results show that leaflet motility strongly influences Ca2+ uptake, as well as glutamate and K+ to a lesser extent. Furthermore, this paper highlights that an astrocytic leaflet that is in proximity to the synaptic cleft loses the ability to form a Ca2+ microdomain, whereas when the leaflet is remote from the synaptic cleft, a Ca2+ microdomain can form. This may have implications for Ca2+-dependent leaflet motility. [ABSTRACT FROM AUTHOR]

In recent years research suggests that astrocyte networks, in addition to nutrient and waste processing functions, regulate both structural and synaptic plasticity. To understand the biological mechanisms that underpin such plasticity requires the development of cell level models that capture the mutual interaction between astrocytes and neurons. This paper presents a detailed model of bidirectional signaling between astrocytes and neurons (the astrocyte-neuron model or AN model) which yields new insights into the computational role of astrocyte-neuronal coupling. From a set of modeling studies we demonstrate two significant findings. Firstly, that spatial signaling via astrocytes can relay a ''learning signal'' to remote synaptic sites. Results show that slow inward currents cause synchronized postsynaptic activity in remote neurons and subsequently allow Spike-Timing-Dependent Plasticity based learning to occur at the associated synapses. Secondly, that bidirectional communication between neurons and astrocytes underpins dynamic coordination between neuron clusters. Although our composite AN model is presently applied to simplified neural structures and limited to coordination between localized neurons, the principle (which embodies structural, functional and dynamic complexity), and the modeling strategy may be extended to coordination among remote neuron clusters. [ABSTRACT FROM AUTHOR]

The current global pandemic due to Severe Acute Respiratory Syndrome Coronavirus 2 (SARS-CoV-2) has taken a substantial number of lives across the world. Although few vaccines have been rolled-out, a number of vaccine candidates are still under clinical trials at various pharmaceutical companies and laboratories around the world. Considering the intrinsic nature of viruses in mutating and evolving over time, persistent efforts are needed to develop better vaccine candidates. In this study, various immuno-informatics tools and bioinformatics databases were deployed to derive consensus B-cell and T-cell epitope sequences of SARS-CoV-2 spike glycoprotein. This approach has identified four potential epitopes which have the capability to initiate both antibody and cell-mediated immune responses, are non-allergenic and do not trigger autoimmunity. These peptide sequences were also evaluated to show 99.82% of global population coverage based on the genotypic frequencies of HLA binding alleles for both MHC class-I and class-II and are unique for SARS-CoV-2 isolated from human as a host species. Epitope number 2 alone had a global population coverage of 98.2%. Therefore, we further validated binding and interaction of its constituent T-cell epitopes with their corresponding HLA proteins using molecular docking and molecular dynamics simulation experiments, followed by binding free energy calculations with molecular mechanics Poisson–Boltzmann surface area, essential dynamics analysis and free energy landscape analysis. The immuno-informatics pipeline described and the candidate epitopes discovered herein could have significant impact upon efforts to develop globally effective SARS-CoV-2 vaccines. [ABSTRACT FROM AUTHOR]

Purpose: To assess the feasibility of delivering microwave ablation for targeted treatment of aldosterone producing adenomas using image-based computational models. Methods: We curated an anonymized dataset of diagnostic 11C-metomidate PET/CT images of 14 patients with aldosterone producing adenomas (APA). A semi-automated approach was developed to segment the APA, adrenal gland, and adjacent organs within 2 cm of the APA boundary. The segmented volumes were used to implement patient-specific 3D electromagnetic-bioheat transfer models of microwave ablation with a 2.45 GHz directional microwave ablation applicator. Ablation profiles were quantitatively assessed based on the extent of the APA target encompassed by an ablative thermal dose, while limiting thermal damage to the adjacent normal adrenal tissue and sensitive critical structures. Results: Across the 14 patients, adrenal tumor volumes ranged between 393 mm3 and 2,395 mm3 . On average, 70% of the adrenal tumor volumes received an ablative thermal dose of 240CEM43, while limiting thermal damage to non-target structures, and thermally sparing 83.5–96.4% of normal adrenal gland. Average ablation duration was 293 s (range: 60–600 s). Simulations indicated coverage of the APA with an ablative dose was limited when the axis of the ablation applicator was not well aligned with the major axis of the targeted APA. Conclusions: Image-based computational models demonstrate the potential for delivering microwave ablation to APA targets within the adrenal gland, while limiting thermal damage to surrounding nontarget structures. [ABSTRACT FROM AUTHOR]

This case study provides feasibility analysis of adapting Spiking Neural Networks (SNN) based Structural Health Monitoring (SHM) system to explore low-cost solution for inspection of structural health of damaged buildings which survived after natural disaster that is, earthquakes or similar activities. Various techniques are used to detect the structural health status of a building for performance benchmarking, including different feature extraction methods and classification techniques (e.g., SNN, K-means and artificial neural network etc.). The SNN is utilized to process the sensory data generated from full-scale seven-story reinforced concrete building to verify the classification performances. Results show that the proposed SNN hardware has high classification accuracy, reliability, longevity and low hardware area overhead. [ABSTRACT FROM AUTHOR]

Abstract Recent studies have shown that the electronic hardware devices can be compromised by the faults and fault tolerance is a crucial capability. This paper addresses the challenge of fault detection in the CMOS circuits, using two bio-inspired structures based on the HP lab's memristor and the BSIM3v3.2.2 transistor models. The first fault detection circuit (FDC) includes the memristor-based synapses and a modified leaky integrate-and-fire (LIF)-based neuron. The memristor-based synapse circuits can be further optimized which is the proposed second fault detection method (O-FDC), and it has a lower hardware overhead and power consumption compared to the former. Experimental results demonstrate that the proposed structures can detect the circuit faults under the inputs of direct current (DC), alternating current (AC) voltage sources, and pulse signals. Under the input of DC, the fault detection times for the two proposed structures are about 0.16 ms and 1.2 ms, respectively; when the input source is AC, the corresponding fault detection times are about 0.206 ms and 0.758 ms; and it takes only 6.47us for fault detection under the input of pulse signals. This work provides an alternative solution to enhance the fault-tolerant capability of the hardware systems. [ABSTRACT FROM AUTHOR]

The ability of astrocytes to rapidly clear synaptic glutamate and purposefully release the excitatory transmitter is critical in the functioning of synapses and neuronal circuits. Dysfunctions of these homeostatic functions have been implicated in the pathology of brain disorders such as mesial temporal lobe epilepsy. However, the reasons for these dysfunctions are not clear from experimental data and computational models have been developed to provide further understanding of the implications of glutamate clearance from the extracellular space, as a result of EAAT2 downregulation: although they only partially account for the glutamate clearance process. In this work, we develop an explicit model of the astrocytic glutamate transporters, providing a more complete description of the glutamate chemical potential across the astrocytic membrane and its contribution to glutamate transporter driving force based on thermodynamic principles and experimental data. Analysis of our model demonstrates that increased astrocytic glutamate content due to glutamine synthetase downregulation also results in increased postsynaptic quantal size due to gliotransmission. Moreover, the proposed model demonstrates that increased astrocytic glutamate could prolong the time course of glutamate in the synaptic cleft and enhances astrocyte-induced slow inward currents, causing a disruption to the clarity of synaptic signalling and the occurrence of intervals of higher frequency postsynaptic firing. Overall, our work distilled the necessity of a low astrocytic glutamate concentration for reliable synaptic transmission of information and the possible implications of enhanced glutamate levels as in epilepsy. [ABSTRACT FROM AUTHOR]

Spiking neural networks (SNNs) are well suited for functions such as data/pattern classification, estimation, prediction, signal processing and robotic control applications. Whereas the real-world embedded applications are often multi-functional with orthogonal or contradicting functional requirements. The EMBRACE hardware modular SNN architecture has been previously reported as an embedded computing platform for complex real-world applications. The EMBRACE architecture employs genetic algorithm (GA) for training the SNN which offers faster prototyping of SNN applications, but exhibits a number of limitations including poor scalability and search space explosions for the evolution of large-scale, complex, real-world applications. This paper investigates the limitations of evolving real-world embedded applications with orthogonal functional goals on hardware SNN using GA-based training. This paper presents a novel, fast and efficient application prototyping technique using the EMBRACE hardware modular SNN architecture and the GA-based evolution platform. Modular design and evolution of a robotic navigational controller application decomposed into obstacle avoidance controller and speed and direction manager application subtasks is presented. The proposed modular evolution technique successfully integrates the orthogonal functionalities of the application and helps to overcome contradicting application scenarios gracefully. Results illustrate that the modular evolution of the application reduces the SNN configuration search space and complexity for the GA-based SNN evolution, offering rapid and successful prototyping of complex applications on the hardware SNN platform. The paper presents validation results of the evolved robotic application implemented on the EMBRACE architecture prototyped on Xilinx Virtex-6 FPGA interacting with the player-stage robotics simulator. [ABSTRACT FROM AUTHOR]

The chaotic map has complex dynamics under ideal conditions however it suffers from the problem of performance degradation in the case of finite computing precision. In order to prevent the dynamics degradation, in this paper the continuous Chen chaotic system is used to perturb both the inputs and parameters of Chebyshev map to minimize the chaotic degradation phenomenon under finite precision. Experimental evaluations and corresponding performance analysis demonstrate that the Chebyshev chaotic map has a good randomness and complex dynamic performance by using the proposed perturbation method, and some attributes of the proposed system are stronger than the original system (e.g. chaos attractor and approximate entropy). Finally, the corresponding pseudorandom number generator (PRNG) is constructed by this method and then its randomness is evaluated via NIST SP800-22 and TestU01 test suites, respectively. Statistical test results show that the proposed PRNG has high reliability of randomness, thus it can be used for cryptography and other potential applications. [ABSTRACT FROM AUTHOR]

Highlights: [•] SystemC simulation based analysis of the synaptic information distortion in NoC based hardware SNNs. [•] Fixed spike transfer latency ring topology interconnect for spike communication between neural tiles, using a novel timestamped spike broadcast flow control scheme. [•] Spike transfer latency results and elimination of information jitter in hardware SNNs. [•] Micro-architecture of the proposed ring router, FPGA and ASIC synthesis results. [•] A hierarchical NoC architecture comprising ring topology interconnect within a mesh topology NoC. [ABSTRACT FROM AUTHOR]