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This study introduces a reconfigurable and agile RF front-end (RFFE) architecture that significantly enhances the performance of software-defined radios (SDRs) by seamlessly adjusting to varying signal requirements, frequencies, and protocols. This flexibility greatly enhances spectrum utilization, signal integrity, and overall system efficiency—critical factors in aviation, where reliable communication, navigation, and surveillance systems are vital for safety. A versatile RF front-end is thus indispensable, enhancing connectivity and safety standards. We explore the integration of this flexible RF front-end in SDRs, focusing on the detailed design of essential components, such as receivers, transmitters, RF switches, combiners, and splitters, and their corresponding RF pathways. Comprehensive performance evaluations confirm the architecture's reliability and functionality, including an extensive analysis of receiver gain, linearity, and two-tone test results. These assessments validate the architecture's suitability for aviation radios and address considerations of size, weight, and power-cost (SWaP-C), demonstrating significant gains in operational efficiency and cost-effectiveness. The introduction of the new RF front-end on a single SDR board not only substantially reduces size and weight but also adds up to 18 dB gain to the received signal. It also allows for a high level of design flexibility, enabling seamless software transitions between different radios and the capacity to manage three times more radios with the same hardware, thereby significantly boosting the system's ability to handle multiple radio channels efficiently. [ABSTRACT FROM AUTHOR]

This letter demonstrates an X‐band transceiver front‐end in 130‐nm CMOS technology for phased‐array systems. To solve the problem that passive attenuator performance deteriorates significantly in wideband systems, a 6‐bit attenuator with source follower and common‐gate amplifier is proposed. Besides, an 8‐bit vector‐summing phase shifter is implemented in common path to realize the phase coverage of 360° with the least significant bit of 5.625°. In the frequency range of 8–12 GHz, the measured root‐mean‐square (rms) amplitude and phase errors of the attenuator in the transceiver are less than 0.36 dB and 2.2°, respectively. The rms phase and amplitude errors of the phase shifter in the transceiver are less than 4.8° and 0.56 dB, respectively. The whole chip area including pads is 3 × 2.3 mm2. [ABSTRACT FROM AUTHOR]

This paper focuses on the topic of joint communication and radar sensing (JCRS) and its applications in the scope of upcoming sixth-generation (6G) technology. While the fifth-generation applications have reached the consumer market in the last few years, JCRS has been identified as one of the key technologies for next generation networks. The role of JCRS will vary, ranging from tasks such as radar coordination, context awareness for communication, enhanced security, increased availability, and improving the resilience and trustworthiness of future networks. In this work, the niche of JCRS technology in the future 6G ecosystem, as well as several potential applications, are discussed with a focus on RF hardware. The use of centimeter (cmWave) and millimeter (mmWave) frequency spectrums in the context of JCRS system implementation have been further elaborated. After presenting the near-term application scenarios, the circuit implementation perspectives are investigated in terms of radio frequency (RF) front-end architectures, antenna implementation, and phased arrays. Different communication and radar antenna options are compared, and the best candidates are identified. The packaging options are also presented. From circuit and system perspectives, link budget and self-interference cancellation (SIC) are highlighted. Furthermore, future directions including the next steps on the path to enabling JCRS technology are presented throughout this article. Prior works focused more on physical layers and network capabilities of JCRS systems, with less focus on hardware possibilities; to fill this gap, this article aims to contribute to this exciting research topic with a holistic review of RF hardware, highlighting the diversity of applications and the available technologies to tackle the near- and long-term needs of consumer applications. [ABSTRACT FROM AUTHOR]

Oxygen-free high-conductivity copper (OFHC), chromium-zirconium copper (CuCrZr), and Glidcop® AL-15 are widely used in the high heat load absorber elements at the front end of synchrotron radiation facilities. It is necessary to choose the most suitable material according to the actual engineering conditions (such as the specific heat load, material performance, and costs). In the long-term service period, the absorber elements have to bear hundreds or kilowatts of high heat load and its "load-unload" cyclic loading mode. Therefore, the thermal fatigue and thermal creep properties of the materials are critical and have been extensively studied. In this paper, based on the published pieces of the literature, the thermal fatigue theory, experimental principles, methods, test standards, test types of equipment, and key indicators of the thermal fatigue performance of typical copper metal materials used in the front end of synchrotrons radiation Facilities are reviewed, as well as the relevant studies carried out by the well-known synchrotron radiation institutions. In particular, the fatigue failure criteria for these materials and some effective methods for improving the thermal fatigue resistance performance of the high-heat load components are also presented. [ABSTRACT FROM AUTHOR]

The front‐end process integration of the selective acetylene hydrogenation provides several advantages over the tail‐end option. But extensive knowledge of the process and reaction kinetics are required. This work combines the ideal conditions of the advanced TEMKIN reactor in a laboratory plant for gradient‐free kinetic analysis of eggshell catalyst under industrially relevant front‐end conditions. With this system an industrial state of the art Pd‐Ag/Al2O3 eggshell catalyst is investigated and the temperature dependent data under various feed compositions including information on the formation of C4‐species are reported. [ABSTRACT FROM AUTHOR]

Silicon photomultipliers (SiPM) have gained popularity in particle physics due to their inherent advantages in terms of compactness, low power consumption, and high photon detection efficiency. Moreover, we have to deal with signals ranging from a few photoelectrons (PE), where we need to reconstruct the exact shape, up to thousands of PEs in short time intervals. The design of this amplifier was conceived to handle the SiPMs signal in both cases, combining together a high-speed amplifier for precisely reconstruct the shape of the signals of a few PEs and an integrated one in which the output voltage level is directly proportional to the number of the input PEs. [ABSTRACT FROM AUTHOR]

A digital asynchronous logic is proposed as a generic matrix readout for Monolithic active pixel sensors. The architecture is implemented for pixel pitch ranging from 18 to 30 µm. Post-layout simulations with realistic hit shapes and rates up to 200 MHz/cm 2 show that time stamping at the 20 ns level can be achieved for a digital power cost below 10 mW/cm 2. [ABSTRACT FROM AUTHOR]

With the tremendous growth in mobile phones, mobile application development is an important emerging arena. Moreover, various applications fail to serve the purpose of getting the attention of the intended users, which is determined by their User Interface (UI) and User Experience (UX). As a result, developers often find it challenging to meet the users' expectations. To date, several reviews have been carried out which explored various aspects of design and the experience of mobile applications using UX/UI. However, many of these existing surveys primarily focused on only some of the issues in isolation but did not consider all the major parameters such as visualisation/graphics, context, user behaviour/emotions/control, usability, adaptability/flexibility, language, and feedback. In our pilot survey, we gathered the preferences and perceptions of a heterogeneous group of concerned people and considered all the aforementioned parameters. These preferences would serve as a reference to mobile application developers, giving them useful insights. Our proposed approach would help mobile application developers and designers focus on the particular UI/UX problems of mobile applications as per their relevant context. A comparative analysis of the various UI and UX factors that determine a mobile application interface is presented in this paper. [ABSTRACT FROM AUTHOR]

This work has successfully demonstrated a system for monitoring pink-beam X-rays exiting from a beamline front-end, which has a specific spatial distribution based on each energy component. In this study, the X-rays scattered from a single-crystal chemical-vapor-deposited diamond film were converted into a cross-sectional image using pinhole optics, followed by digitization with a direct detection complementary metal-oxide-semiconductor 2D detector. By using single crystals instead of poly-crystals, good quality images were obtained with no diffraction bright spots. As a result of applying photon energy discrimination using the droplet analysis to the image information, the spatial distribution of each energy component of the undulator radiation was successfully visualized. The result was found to be in good agreement with the theoretically calculated result obtained using the synchrotron radiation calculation code SPECTRA. The new synchrotron radiation beam monitor proposed in this paper can serve as a powerful beam diagnostic tool for diffraction-limited rings that require strict light source stability. [ABSTRACT FROM AUTHOR]

A new millimeter-wave (mm-wave) fully-integrated 0.18- $\mu \text{m}$ BiCMOS frequency division duplex (FDD) transmit–receive (T/R) front-end module with internal power amplifier (PA) and low noise amplifier (LNA) is reported. It employs an active circuit to cancel the transmitter (TX) signal leaking into the receiver (RX). The T/R module provides 43.6 dB isolation between the PA output and LNA input at 29 GHz and 9.5 dB average noise figure (NF) over 27–29 GHz on the entire RX path. At 29 GHz, the T/R module has 13.8 and 10.6 dB gain on the RX and TX path, respectively. A design methodology is also presented for maximum isolation and optimum NF. It occupies a small area of 2 mm2. [ABSTRACT FROM AUTHOR]

This article proposes and presents an innovative approach to realizing the concurrent dual-band transmission with only a single front-end and local oscillator at radio frequency (RF). Fundamentally, the proposed concurrent dual-band front-end is based on the conventional multiport interferometric architecture for single-band operation. Nevertheless, the conventional variable loads are replaced by diode networks with IF input signals to produce the RF signals at their designated center frequencies. Furthermore, due to the linear characteristics of a multiport network, the signals with different data contents will be mixed into both RF channels. To this end, an inverse matrix operation is applied to reversely convert the original data streams before the modulations of IF input signals. As a result, the two original data streams can be effectively modulated into specific RF channels (for transmission) with minimal interchannel interferences based on this configuration. In addition to the theoretical analyses, this innovative concurrent dual-band transmitting front-end has been investigated and verified with $M$ -quadrature amplitude modulation (QAM) signals in simulations and experiments. All outcomes demonstrate excellent performances in concurrent dual-band transmission with significant reductions in both size and biasing power. [ABSTRACT FROM AUTHOR]

This work is focused on the design and the experimental characterization of an analog channel developed for the readout of lithium-drifted silicon detectors of the General AntiParticle Spectrometer (GAPS) experiment aimed at the search for dark matter. The instrument is designed for the identification of antideuteron particles from cosmic rays during an Antarctic balloon mission scheduled for late 2022. A low-noise analog front-end, featuring a dynamic signal compression to comply with the wide input range, has been designed in commercial 180-nm CMOS technology. The channel was fabricated in 2018 and is the first building block toward the development of a multichannel readout ASIC. The article will provide a description of the design criteria, the architecture of the channel, and a summary of the results of the experimental characterization. [ABSTRACT FROM AUTHOR]

A time-division duplex (TDD) transmit/receive (T/R) millimeter-wave (mm-wave) front-end in 0.13- $\mu \text{m}$ SiGe BiCMOS for fifth generation (5G) is presented. The front-end is composed of a power amplifier (PA), a low noise amplifier (LNA), and a single-pole double-throw (SPDT) switch. At mm-wave bands, the traditional SPDT switch limits the output power of the front-end in transmit mode. In this article, an asymmetric SPDT switch is proposed with high-power-handling capability (simulated OP $_{\mathrm {1\,dB}} > 28$ dBm), low insertion loss, and compact structure at 24–30 GHz. A balanced architecture is used to implement a high gain and high linearity PA with excellent input/output return losses and load-variation insensitivity. The effect of the feedback capacitor in the base of the cascode stage has been analyzed. The standalone PA achieves OP $_{\mathrm {1\,dB}}$ /peak $\text {PAE} > 16.9$ dBm/18.7% across 24–30 GHz and the OP $_{\mathrm {1\,dB}}$ /peak PAE still exceeds >15.9 dBm/16.3% including the switch loss and compression. 5G NR FR2 64-QAM modulation tests demonstrate the high linearity of the balanced PA. At 28 GHz, the standalone PA shows the EVM of −29.93 dB/−26.06 dB with an average output power ($P_{\mathrm {avg}}$) of 10.15 dBm/12.16 dBm. The front-end in transmit mode shows the EVM of −29.63 dB/−26.02 dB with an average output power of 7.76 dBm/9.59 dBm. A wideband LNA is designed and exhibits a measured gain of 26 dB with a 3-dB bandwidth of 19–35 GHz, a noise figure (NF) < 5.3 dB at 24–30 GHz including the switch loss. The proposed front-end achieves high linearity in transmit mode and low NF in receive mode. [ABSTRACT FROM AUTHOR]

Many commercial benchtop impedance analyzers are incapable of acquiring accurate tetrapolar measurements, when large electrode contact impedances are present, as in bioimpedance measurements using electrodes with micrometer-sized features. External front-end amplifiers can help overcome this issue and provide high common-mode rejection ratio (CMRR) and input impedance. Several discrete component-based topologies are proposed in the literature. In this article, these are compared with new alternatives with regard to their performance in measuring known loads in the presence of electrode contact impedance models, to emulate tetrapolar bioimpedance measurements. These models are derived from bipolar impedance measurements taken from the electrodes of a tetrapolar bioimpedance sensor. Comparison with other electrode models used in the literature established that this is a good and challenging model for bioimpedance front-end amplifier evaluation. Among the examined amplifiers, one of the best performances is achieved with one of the proposed topologies based on a custom front-end with no external resistors (AD8066/AD8130). Under the specific testing conditions, it achieved an uncalibrated worst-case absolute measurement deviation of 4.4% magnitude and 4° at 20 Hz, and 2.2% and 7° at 1 MHz accordingly with loads between $10~\Omega $ and 10 $\text{k}\Omega $. Finally, the practical use of the front-end with the impedance analyzer is demonstrated in the characterization of the bioimpedance sensor, in saline solutions of varying conductivities (2.5–20 mS/cm) to obtain its cell constant. This article serves as a guide for evaluating and choosing front-end amplifiers for tetrapolar bioimpedance measurements both with and without impedance analyzers for practical/clinical applications and material/sensor characterization. [ABSTRACT FROM AUTHOR]

Digital oscilloscope’s structure has analog signal acquisition circuit, which transforms signal’s amplitude to fit ADC dynamic range. This circuit is commonly called oscilloscope’s vertical or front-end amplifier. Difficulty in designing front-end amplifiers in GHz range largely affects higher frequency range oscilloscope’s price. This work is focused on designing a front-end amplifier using discrete and openly sold components. We propose a design for attenuator, buffer, variable gain circuits. Amplifier’s prototype is designed. Main characteristics of the amplifier were measured. Measured bandwidth is 3 GHz. Amplifier’s gain and attenuation can support vertical scale sensitivity range from 10 mV/div to 1 V/div. Step response distortion is under 10 %. SMD and PTH relay model attenuators were evaluated. In this paper we review oscilloscope’s front-end purpose and structure. We review amplifiers design and provide the results of experimental measurements. [ABSTRACT FROM AUTHOR]

In the design of CMOS optical receivers, it is challenging to compromise the bandwidth, noise, and gain of the transimpedance amplifier (TIA). The inverter-based cascaded structure is often used in TIA designs. However, the traditional 3-stage TIA needs bandwidth expansion techniques to get good performance. In the designed front-end, we propose a 5-stage cascaded TIA that achieves performance improvement without using bandwidth expansion technique. Besides, the stability of the main amplifier (MA) is improved by adopting a feed-forward compensation technique. Designed in a 0.13- μ m CMOS process, the proposed front-end exhibits a bandwidth of 8.9 GHz, a transimpedance gain of 123.5 dB Ω and an average input-referred noise of 12.2 pA/ Hz. The whole circuit consumed 19.1 mW from mixed input of 1 V and 1.5 V supply voltages. • A 5-stage cascaded transimpedance amplifier without bandwidth expansion technique. • The main channel can work with low supply voltage. • The static power consumption of the front-end is 19.1 mW. • The technique to reduce signal overshoot and keep circuit stability. [ABSTRACT FROM AUTHOR]

Abstract We present the experimental results obtained with TOFPET2, a readout and digitization ASIC for radiation detectors using Silicon Photomultipliers. The circuit is designed in CMOS 110 nm technology, has 64 independent channels and is optimized for time-of-flight measurement in PET or other applications. The chip has quad-buffered TDCs and charge integration ADCs in each channel. The chip tape-out was done in September 2016 and first tests started in beginning March 2017. Coincidence Time Resolution (CTR) of 164 ps FWHM has been measured with 22Na point source. The energy resolution achieved for the 511 keV peak is 10.5% FWHM. Highlights • We present TOFPET2, a readout and digitization ASIC for radiation detectors using Silicon Photomultipliers. • The ASIC is meant for Time of Flight PET applications, with internal digitization of time of arrival and energy of the signals. • Background events contamination removed thanks to energy measurement. • Coincidence Time Resolution in the order of 215ps (FWHM) achieved for a single LYSO crystal. • Coincidence Time Resolution in the order of 260ps (FWHM) achieved for a 4 × 4 array. [ABSTRACT FROM AUTHOR]

Abstract An ideal readout circuit would detect X-ray beam with full spectral information and Fano-limited precision and would deal with high count rates, limited only by charge transport within the detector. Unfortunately in a real readout IC in particular the performance in speed and noise are conflicting requirements. In this review the speed–noise trade-off is discussed, referring to the recent ICs for hybrid detectors: those with best results in the energy resolution and those with the highest counting rates. ICs demonstrating the best performance from each end and also intermediate solutions are analysed. [ABSTRACT FROM AUTHOR]

Abstract The Mini-EUSO telescope is designed by the JEM-EUSO Collaboration to observe the UV emission of the Earth from the vantage point of the International Space Station (ISS) in low Earth orbit. The main goal of the mission is to map the Earth in the UV, thus increasing the technological readiness level of future EUSO experiments and to lay the groundwork for the detection of Extreme Energy Cosmic Rays (EECRs) from space (Ebisuzaki et al., 2014). Due to its high time resolution of 2.5 μs, Mini-EUSO is capable of detecting a wide range of UV phenomena in the Earth's atmosphere. In order to maximise the scientific return of the mission, it is necessary to implement a multi-level trigger logic for data selection over different timescales. This logic is key to the success of the mission and thus must be thoroughly tested and carefully integrated into the data processing system prior to the launch. This article introduces the motivation behind the trigger design and details the integration and testing of the logic. [ABSTRACT FROM AUTHOR]

Invertebrates represent a large proportion of the biomass in aquatic ecosystems, particularly in the ocean. In recent years, invertebrates have been well-consolidated models in evolutionary developmental biology research and, consequently, genomic and transcriptomic sequence databases from a plethora of species across the animal kingdom have become available. This has provided an excellent source of evidence confirming that invertebrates operate endogenous mechanisms for PUFA production. The present paper reviews the current knowledge of gene complement and, where possible, the function of desaturases and elongases with pivotal roles in PUFA biosynthesis of aquatic invertebrates. More specifically, this review covers three major enzyme types, namely ωx desaturases, front-end desaturases and elongases, that have been characterised from species of sponges, cnidarians, molluscs, annelids, crustaceans, rotifers, echinoderms and non-vertebrate chordates (amphioxus and sea squirt). These studies have shown that invertebrates operate alternative and unusual pathways of PUFA biosynthesis involving gene families with complex phylogeny and functional diversity. Consequently, research in this area provides potentially valuable molecular tools in the form of genes that can be used in the biotechnological production of n-3 products. [ABSTRACT FROM AUTHOR]

IC-PIX28 (Integrated Circuit for PIXel detectors) is an analog read-out front-end fabricated in 28 nm Bulk-CMOS technology to process the charge signal produced by the pixel detector having 100 fF parasitic capacitance. The device is composed by a Charge Sensitive Pre-amplifier (CSPreamp) and a comparator. The development of IC-PIX28 manages several issues due to the poor analog performance of the standard-process MOS transistors in 28 nm Bulk-CMOS technology, whose choice is motivated by the expected rad-hard performance up to 1 Grad of Total Ionizing Dose. IC-PIX28 achieves performance robustness and low-power consumption by specific circuital solutions and it operates from a single 900 mV supply voltage. The full IC-PIX28 read-out channel consumes 4.3 μ W. The CSPreamp performs 35 mV/fC sensitivity, 40 dB Signal-to-Noise Ratio, and 0.033 fC (204 e rms − ) Equivalent Noise Charge. Moreover, a switched-capacitors inverter-based comparator performs the Time-over-Threshold (ToT, at very low power consumption) with a measured ToT range of 500 ns convertible in a digital word with a high bit resolution (> 14). [ABSTRACT FROM AUTHOR]

Advanced RF packages are demonstrate with active (low-noise amplifier, RF switch) and passive integration in ultra-thin 3D glass packages with miniaturization and enhanced performance. The novelty of this RF packages is three-fold: 1) Ultra-thin 100 μm glass, 2) Double-side thinfilm RF circuits interconnected with Through-Package Vias (TPVs), and 3) Direct assembly of the glass-core package to the board with Land Grid Array (LGA) connections. An innovative double-via process, starting from prefabricated vias in bare glass, polymer filling and via drilling, is utilized for a robust and high-yield substrate fabrication process. Scalable and low-cost panel laminate processes are utilized to form the RF circuits on the build-up layers. The performance benefits are demonstrated through interconnect loss, impedance match, electrical gain and noise figure measurements. Compared to existing RF substrates, the glass substrates show 2.5X miniaturization in substrate thickness with extensibility to thinner substrates. [ABSTRACT FROM AUTHOR]

Hyper-Kamiokande (Hyper-K) is a next generation underground water Cherenkov detector designed to study neutrinos from J-PARC accelerator and astronomical sources, nucleon decay, with the main focus on the determination of leptonic CP violation. To detect the weak Cherenkov light generated by neutrino interactions or proton decay, the newly developed 20"-PMTs by Hamamatsu will be used. The addition of a system of small photomultipliers as implemented in the KM3NeT experiment, the so called multi-PMT module (mPMT), is considered to improve the Hyper-K physics capability. The mPMT system consists of a pressure resistant vessel with inside 19 3"-PMTs and all the electronics required for the system, with a power budget of only 4 W. An overview of the developed electronics system, that has been fully validated and it is now ready for the mass production, is presented. [ABSTRACT FROM AUTHOR]

This paper investigates an issue largely ignored in the transport literature on cost overruns, namely, cost increases in the early project phase, long before the decision to build is made. This is the phase of project planning that is referred to as the front-end phase in the literature. The rationale of the study is that unless cost estimates during the front-end phase are relatively accurate, the wrong projects may be selected for further development. We first argue for why it is important to address cost escalation during the front-end phase of project planning. We then use Norwegian data to demonstrate the magnitude of cost escalations during the front-end phase of projects and in comparison to the implementation phase. We find that even in a sample of projects with relatively small cost overruns as in the case of Norway, there are substantial cost increases before the formal decision to build was made. This raises the issue of whether decisions and priorities taken at the early stages of project development are based on false information and whether this may lead to the wrong project concepts being selected. [ABSTRACT FROM PUBLISHER]

We have developed a preamplifier which processes signals from large area pixel sensors each comprising a 4 × 4 array of SiPMs. These amplifiers constitute a front-end portion of 256 pixel camera for an Imaging Atmospheric Cherenkov Telescope (IACT). The camera would be mounted at the focal plane of the 4-m class telescope. The primary design objective of the camera is to detect the wide energy range of the celestial Gamma-rays by detecting the atmospheric Cherenkov photons produced by them in the atmosphere. The other important objective of the camera is to be able to resolve single photon response for accurate pixel gain calibration. There are several factors like large size sensor, long time response, single p.e. resolution, etc., which have led to a customized design of the preamplifier. We propose an original circuit topology to achieve the design goals. The paper describes the design features of the preamplifier and performance evaluation. [ABSTRACT FROM AUTHOR]

ASTRI SST-2M is one of the prototypes of the small size class of telescopes proposed for the Cherenkov Telescope Array. Its optical design is based on a dual-mirror Schwarzschild-Couder configuration, and the camera is composed by a matrix of monolithic multipixel silicon photomultipliers managed by ad-hoc tailored front-end electronics. This paper describes the procedures for the gain calibration on the ASTRI SST-2M. Since the SiPM gain depends on the operative voltage and the temperature, we adjust the operative voltages for all sensors to have equal gains at a reference temperature. We then correct gain variations caused by temperature changes by adjusting the operating voltage of each sensor. For that purpose the SiPM gain dependence on operating voltage and on temperature have been measured. In addition, we present the calibration procedures and the results of the experimental measurements to evaluate, for each pixel, the parameters necessary to make the trigger uniform over the whole focal plane. [ABSTRACT FROM AUTHOR]

A new pixel detector for the CMS experiment is being built, owing to the instantaneous luminosities anticipated for the Phase I Upgrade of the LHC. The new CMS pixel detector provides four-hit tracking while featuring a significantly reduced material budget as well as new cooling and powering schemes. A new front-end readout chip mitigates buffering and bandwidth limitations, and comprises a low-threshold comparator. These improvements allow the new pixel detector to sustain and improve the efficiency of the current pixel tracker at the increased requirements imposed by high luminosities and pile-up. This contribution gives an overview of the design of the upgraded pixel detector and the status of the upgrade project, and presents test beam performance measurements of the production read-out chip. [ABSTRACT FROM AUTHOR]

The single mirror Small Size Telescope (SST-1M) is one of the proposed designs for the smallest type of telescopes, SSTs that will compose the Cherenkov Telescope Array (CTA). The SST-1M camera will use Silicon PhotoMultipliers (SiPM) which are nowadays commonly used in High Energy Physics experiments and many imaging applications. However the unique pixel shape and size have required a dedicated development by the University of Geneva and Hamamatsu. The resulting sensor has a surface of ∼94 mm 2 and a total capacitance of ∼3.4 nF. These unique characteristics, combined with the stringent requirements of the CTA project on timing and charge resolution have led the University of Geneva to develop custom front-end electronics. The preamplifier stage has been tailored in order to optimize the signal shape using measurement campaigns and electronic simulation of the sensor. A dedicated trans-impedance pre-amplifier topology is used resulting in a power consumption of 400 mW per pixel and a pulse width < 30 ns . The measurements that have led to the choice of the different components and the resulting performance are detailed in this paper. The slow control electronics was designed to provide the bias voltage with 6.7 mV precision and to correct for temperature variation with a forward feedback compensation with 0.17 °C resolution. It is fully configurable and can be monitored using CANbus interface. The architecture and the characterization of the various elements are presented. [ABSTRACT FROM AUTHOR]

The paper presents first results from the Front-End Board (FEB) with the biggest Cyclone® V E FPGA 5CEFA9F31I7N, supporting 8 channels sampled up to 250 MSps @ 14-bit resolution. Considered sampling for the planned upgrade of the Pierre Auger surface detector array is 120 MSps, however, the FEB has been developed with external anti-aliasing filters to keep a maximal flexibility. Six channels are targeted to the SD, two the rest for other experiments like: Auger Engineering Radio Array and additional muon counters. More channels and higher sampling generate larger size of registered events. We used the standard radio channel for a radio transmission from the detectors to the Central Data Acquisition Station (CDAS) to avoid at present a significant modification of a software in both sides: the detector and the CDAS (planned in a future for a final design). Several variants of the FPGA code were tested for 120, 160, 200 and even 240 MSps DAQ. Tests confirmed a stability and reliability of the FEB design in real pampas conditions with more than 40°C daily temperature variation and a strong sun exposition with a limited power budget only from a single solar panel. Seven FEBs have been deployed in a hexagon of test detectors on a dedicated Engineering Array. [ABSTRACT FROM PUBLISHER]

This contribution describes the system performing the trigger and the readout of the PMTs for the High Energy Particle Detector (HEPD-02) onboard the second satellite of the China Seismo Electromagnetic Satellite (CSES-02) mission. CSES is a project developed to research the ionospheric perturbations associated with earthquakes. The mission aims at building a network of multi-instrument satellites to conduct a thorough study of ionospheric phenomena. The HEPD-02 is designed to detect cosmic rays, i.e., electrons and protons, along with light nuclei, in the energy range between a few MeV and a few hundreds of MeV. The instrument consists of a tracker, a trigger and a calorimeter surrounded by a veto. All scintillating detectors are readout by a single board which also issues and manages the trigger signals for the whole apparatus. The HEPD-02 trigger system must be extremely versatile because along the orbit of CSES-02 particle fluxes span several orders of magnitude and data acquisition must guarantee the measurement of energy spectra with a high duty cycle. The HEPD-02 trigger system features concurrent trigger configurations and prescaling capability to match the amount of data the instrument can process and send to the ground. Each trigger pattern is optimized after scientific requirements about the field of view and the nature of particles impinging in HEPD-02, with prescaling settings suitably adjusted. All the trigger configurations will be monitored by rate meters. In addition, a trigger configuration dedicated to gamma-rays will be tracked on a time basis of 10 ms, to measure photon fluxes in the MeV-tens of MeV energy range and provide sensitivity for Gamma Ray Bursts. We provide a comprehensive description of the design criteria and the architecture of the trigger system. [ABSTRACT FROM AUTHOR]

This paper reports the design and experimental results from the characterization of an integrated circuit developed for the readout of the X-ray spectrometer and tracking system of the General AntiParticle Spectrometer (GAPS) balloon mission. GAPS will search for an indirect signature of dark matter through the detection of low-energy (< 0.25 GeV/n) cosmic-ray antiprotons, antideuterons and antihelium nuclei. The ASIC, named SLIDER32 (32 channels Si-LI DEtector Readout ASIC), was fabricated in a 180 nm CMOS technology and is comprised of 32 analog readout channels, an 11-bit SAR ADC and a digital back-end section which is responsible for defining channel settings and for sending digital information to the data acquisition system. The core of the ASIC is a low-noise analog channel implementing a dynamic signal compression which makes the chip suitable for resolving both X-rays in the range of 20 to 100 keV and charged particles with energy deposition of up to 100 MeV. It features an energy resolution of 4 keV FWHM in the 20–100 keV range with a 40 pF detector capacitance, to clearly distinguish X-rays from antiprotonic or antideuteronic exotic atoms. The readout electronics of the ASIC will run at a temperature of about –40 ° C , complying with a detector leakage current of the order of 5–10 nA per strip. [ABSTRACT FROM AUTHOR]

Tracking detectors based on segmented semiconductor sensors have been present in high-energy physics experiments for more than 40 years. The development of these sensors was always strongly linked to advances in CMOS technologies that offer features supporting the design of specialized ASICs for readout purposes. While in the beginning, the front-end electronics only provided simple signal reception and amplification, sending out the raw analog data, growing demands from the experiments lead designers to begin directly integrating more advanced features for data processing and storage, power management, calibration functions, amongst others, on-chip. This development was, and continues to be, possible due to CMOS technology evolution, in particular the scaling. Besides higher speed and better transconductance, today's sub-micron processes offer intrinsic ionizing radiation tolerance which, together with Single Event Effect (SEE) hardening techniques, allows design for reliable operation in a harsh radiation environment. Despite the enhanced functionality and greater number of transistors, higher time resolution and, in consequence, faster analog shaping and readout speed, the power consumption of typical front-end electronics measured per area of tracking detector remains of the order of a few tens of mW per square centimeter. The basic architecture of the input stage has also remained practically the same over the last 40 years. The optimal solution providing wide bandwidth and high open-loop gain at minimum power is the cascode: a cascade of common-source and common-gate amplifiers. Although each particular implementation differs slightly depending on the specific requirements and process used, the core of the preamplifier remains the same since its conception. [ABSTRACT FROM AUTHOR]

This work is concerned with the design of a low-noise Charge Sensitive Amplifier featuring a dynamic signal compression based on the non-linear features of an inversion-mode MOS capacitor. These features make the device suitable for applications where a non-linear characteristic of the front-end is required, such as in imaging instrumentation for free electron laser experiments. The aim of the paper is to discuss a methodology for the proper design of the feedback network enabling the dynamic signal compression. Starting from this compression solution, the design of a low-noise Charge Sensitive Amplifier is also discussed. The study has been carried out by referring to a 65 nm CMOS technology. [ABSTRACT FROM AUTHOR]

In this paper, we report on the recent development of a 32-channel low-noise front-end readout ASIC for cadmium zinc telluride (CdZnTe) X-ray and \gamma -ray detectors. Each readout channel includes a charge sensitive amplifier, a CR-RC shaping amplifier and an analog output buffer. The readout ASIC is implemented using TSMC 0.35 - \mu \m mixed-signal CMOS technology, the die size of the prototype chip is 2.2~\mm \times 4.8~\mm. At room temperature, the equivalent noise level of a typical channel reaches 133~\e^ - (rms) with the input parasitic capacitance of 0 pF for the average power consumption of 2.8 mW per channel. The linearity error is less than \pm 2\% and the input energy dynamic range of the readout ASIC is from 10 keV to 1 MeV. The crosstalk between the channels is less than 0.4%. By connecting the readout ASIC to a CdZnTe detector, we obtained a \gamma -ray spectrum, the energy resolution is 1.8% at the 662-keV line of ^137Cs source. [ABSTRACT FROM AUTHOR]

The Cherenkov Imaging Telescope Integrated Read Out Chip, CITIROC, is a chip adopted as the front-end of the camera at the focal plane of the imaging Cherenkov ASTRI dual-mirror small size telescope (ASTRI SST-2M) prototype. This paper presents the results of the measurements performed to characterize CITIROC tailored for the ASTRI SST-2M focal plane requirements. In particular, we investigated the trigger linearity and efficiency, as a function of the pulse amplitude. Moreover, we tested its response by performing a set of measurements using a silicon photomultiplier (SiPM) in dark conditions and under light pulse illumination. The CITIROC output signal is found to vary linearly as a function of the input pulse amplitude. Our results show that it is suitable for the ASTRI SST-2M camera. [ABSTRACT FROM AUTHOR]

Modern radio front ends are required to operate over diverse channel conditions requiring the incorporation of significant performance overheads into their design. This results in significantly higher power consumption over most of the operational period since the worst case channels are not statistically prevalent. Adaptive systems solve this problem by adapting the performance and power consumption depending on channel conditions. In this paper, it is demonstrated that depending upon the throughput requirements of the system multiple low-power adaptation modes can be designed. These modes ensure either highest throughput operation or lowest energy-per-bit operation. The operation of these modes is demonstrated in simulation using multiple-input-multiple-output (MIMO) receiver and transmitter front ends. Subsequently, the concepts are demonstrated in hardware for both MIMO and single-input-single-output front ends. [ABSTRACT FROM PUBLISHER]

Inductors are used extensively in Radio Frequency Integrated Circuits to design matching networks, load circuits of voltage controlled oscillators, filters, mixers and many other RF circuits. However, on-chip inductors are large and cannot be ported easily from one process to the next. Due to modern CMOS scaling, inductorless RF design is rapidly becoming possible. In this paper a new methodology for designing the RF frontend necessary for the DVB-SH in a 90 nm CMOS technology based on the use current conveyors (CC) is presented. The RF frontend scheme is composed of a second generation CC (CCII) LNA with asymmetric input and output, an asymmetric to differential converter, and a passive differential mixer followed by two CCII transimpedance amplifiers to obtain a high gain conversion. Measurements show a conversion gain of 20.8 dB, a 14.5 dB noise figure, an input return loss (S11) of −14.3 dB and an output compression point of −3.9 dBm. This combination draws 28.4 mW from a ±1.2 V supply. [ABSTRACT FROM AUTHOR]

The surface detector (SD) array of the Pierre Auger Observatory needs an upgrade which allows space for more complex triggers with higher bandwidth and greater dynamic range. To this end this paper presents a front-end board (FEB) with the largest Cyclone V E FPGA 5CEFA9F31I7N. It supports eight channels sampled with max. 250 MSps@14-bit resolution. Considered sampling for the SD is 120 MSps; however, the FEB has been developed with external anti-aliasing filters to retain maximal flexibility. Six channels are targeted at the SD, two are reserved for other experiments like: Auger Engineering Radio Array and additional muon counters. The FEB is an intermediate design plugged into a unified board communicating with a micro-controller at 40 MHz; however, it provides 250 MSPs sampling with an 18-bit dynamic range, is equipped with a virtual NIOS processor and supports 256 MB of SDRAM as well as an implemented spectral trigger based on the discrete cosine transform for detection of very inclined “old” showers. The FEB can also support neural network development for detection of “young” showers, potentially generated by neutrinos. A single FEB was already tested in the Auger surface detector in Malargüe (Argentina) for 120 and 160 MSps. Preliminary tests showed perfect stability of data acquisition for sampling frequency three or four times greater. They allowed optimization of the design before deployment of seven or eight FEBs for several months of continuous tests in the engineering array. [ABSTRACT FROM PUBLISHER]

This paper examines the individual and combined impacts of various front-end approaches on the performance of deep neural network (DNN) based speech recognition systems in distant talking situations, where acoustic environmental distortion degrades the recognition performance. Training of a DNN-based acoustic model consists of generation of state alignments followed by learning the network parameters. This paper first shows that the network parameters are more sensitive to the speech quality than the alignments and thus this stage requires improvement. Then, various front-end robustness approaches to addressing this problem are categorised based on functionality. The degree to which each class of approaches impacts the performance of DNN-based acoustic models is examined experimentally. Based on the results, a front-end processing pipeline is proposed for efficiently combining different classes of approaches. Using this front-end, the combined effects of different classes of approaches are further evaluated in a single distant microphone-based meeting transcription task with both speaker independent (SI) and speaker adaptive training (SAT) set-ups. By combining multiple speech enhancement results, multiple types of features, and feature transformation, the front-end shows relative performance gains of 7.24% and 9.83% in the SI and SAT scenarios, respectively, over competitive DNN-based systems using log mel-filter bank features. [ABSTRACT FROM AUTHOR]

This paper presents the analysis, design, and measurements of a 2.5-GHz receiver front-end in a 40-nm CMOS technology. The front-end utilizes RLC-resonator quality factor (Q) boosting and four-phase N-path filtering to improve the blocker filtering capabilities of the low-noise amplifier (LNA). Systematic analysis is performed in order to obtain a thorough design approach. Particular attention is paid to the passive mixer switches in the RLC case, for which we show that minimum switch resistance does not provide best noise figure (NF), nor best relative blocker attenuation. Moreover, the N-path filter extends the stable operating region of a Q-boosted LNA, and adding a noisy Q-boosting circuit can actually improve the receiver NF in practical realizations. The experimental CMOS front-end is flip-chip packaged, and a parasitic-aware input matching method for the electrostatic-discharge-protected LNA is proposed, analyzed, and verified. In nominal operation, the programmable front-end achieves a measured gain of 39 dB, an NF of 3.5 dB, and an out-of-band input-referred third order intercept point of >\0 dBm, while consuming 48 mA from a 1.1-V supply. [ABSTRACT FROM AUTHOR]

Abstract: In this paper, we present the design and characteristics of a novel low-noise front-end readout application-specific integrated circuit dedicated to CdZnTe (CZT) detectors for a small animal PET imaging system. A low-noise readout method based on the charge integration and the delayed peak detection is proposed. An eight-channel front-end readout prototype chip is designed and implemented in a 0.35μm CMOS process. The die size is 2.3mm ×2.3mm. The prototype chip is tested in different methods including electronic test, energy spectrum test and irradiation test. The input range of the ASIC is from 2000e− to 180,000e−, reflecting the energy of the gamma ray from 11.2keV to 1MeV. The gain of the readout channel is 65mV/fC at the shaping time of 1μs. The best test result of the equivalent noise charge (ENC) is 58.9e− at zero farad plus 5.4e− per picofarad. The nonlinearity and the crosstalk are less than 3% and less than 2%, respectively, at the room temperature. The static power dissipation is about 3mW/channel. [Copyright &y& Elsevier]

ABSTRACT This article describes a low-power RF front-end for digital video broadcasting-satellite services to handhelds (2.17-2.2 GHz) implemented in UMC CMOS 90-nm process. This receiver includes a resistive feedback low-noise amplifier and a double-balanced Gilbert mixer. Measurements show a conversion gain of 24.1 dB, a 3-dB noise figure, an input return loss of −11.9 dB, and an output compression point of −2.2 dBm. This combination draws 12.4 mW from a 1.2 V supply. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:528-531, 2014 [ABSTRACT FROM AUTHOR]