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Due to the imaginary interference, the filter bank multi-carrier with offset quadrature amplitude modulation (FBMC/OQAM) performs poor in context of multiple-input multiple-output (MIMO) communication scenarios. In this article, we propose an imaginary interference-free method for FBMC/OQAM, which is appropriate for both of the subcarrier-based singular valued decomposition (SVD) precoding as well as subband-based precoding with codebook schemes. Specifically, the critical design utilizes a repeated block with the reverse arrangement of symbols. Moreover, we investigate the leakage of imaginary interference of the precoding MIMO-FBMC/OQAM system under frequency selective channel. It is found that these developed precoding solutions may particularly inhibit the inter-carrier interference (ICI) via the meticulous designed symbols block. Theoretical analysis and simulation results over different frequency selective channels validate that the proposed precoding schemes are capable of providing considerable performance gains over the conventional schemes in terms of bit error rate (BER). [ABSTRACT FROM AUTHOR]

The numerically controlled oscillator is often supposed to operate after interpolation in a conventional digital up converter, but such a converter works at quite high frequencies and consumes more power. In this paper, a type of low power structure digital up converter is proposed which carries out mixing and interpolating gradually, where the numerically controlled oscillator and the interpolation filter can both work at a lower frequency. Low power structure can move signal to any position within the whole Nyquist Band. Furthermore, the interpolation filter adopts a half-band filter with the structure of two parallel branches, which combines the functions of stuffing zero, filtering and modulation, and makes programmable modulation by exchanging input paths. A simulation is carried out on the Xilinx KC705 development kit, which indicates that its maximum work frequency of the low power structure reaches 392 MHz while its power consumption reduces by 33.3% compared to the conventional structure. [ABSTRACT FROM AUTHOR]

Coordinate rotation digital computer (CORDIC) algorithm has been widely used in modern digital communication systems such as all-digital phase-locked loop, fast Fourier transform and direct digital frequency synthesizers. Precision of the CORDIC algorithm implemented using pipelined architecture has to be guaranteed by increasing the number of iterations, which leads to large delay, excessive consumption of hardware resource and other problems, unfavorable for applications calling for high real-time performance and low power consumption. In this paper, through integrated use of binary to bipolar recoding, angle domain folding, merging iteration and optimized lookup table, an iteration-free CORDIC algorithm was proposed, with which it takes only two clock cycles to get the output, and it enables certain improvements in hardware consumption and output precision when compared with other basic implementation methods. [ABSTRACT FROM AUTHOR]