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In industrial application of adjustable speed drive for electrical motors, some sensors are supplying mandatory information such as speed or position of the rotor to the electronic command. In most deployed applications, these data are transmitted through an additional dedicated line. In order to avoid this additional installation, power line communication (PLC) technology can be used. This study proposes a PLC communication solution between an inverter and a motor through a variable length cable. This solution relies on the modelling of this communication channel as well as the characterisation of the pulse‐width modulated signal. The communication parameters such as carrier frequency or modulation format (quadrature phase shift keying etc.) have been optimised to reduce the channel‐to‐noise ratio in this context. An error free 2 Mbit/s communication has been achieved on a 2 kW test bench. [ABSTRACT FROM AUTHOR]

Wide-bandgap (WBG) semiconductor materials offer faster and more reliable power electronic components in electric energy conversion systems. However, their faster switching speed and abilities to operate at higher frequency than silicium devices have brought new challenges, such as electromagnetic interference (EMI) issues. In gate driver applications, EMI issues must be tackled given the close proximity between gate driver systems and WBG power modules. This article focuses on planar pulse transformers for gate drivers in high power applications (3.3 kV, 500 A SiC module). This article tries to give a standard procedure to design, then, simulate pulse transformers with their electrostatic shielding. First, a design guideline using Altium designer is proposed to respect the European standards. A method to extract the transformer design from Altium to Ansys is also proposed. Finally, a frequency analysis is discussed to use in Ansys simulations and parameters extraction. Tests have been performed to check the proposed transformer’s electromagnetic compatibility immunity under a 125 kV μs−1 common mode transient immunity test. [ABSTRACT FROM AUTHOR]

A new digital predistortion technique based on a direct learning architecture is proposed for linearising power amplifiers (PAs) with nonlinear memory effects. It is based on the non‐uniform memory polynomial (MP) model and with a quadratically interpolated LUT. There are mainly two innovations. First, compared with the conventional MP model, the non‐uniform MP model achieves the same modelling accuracy with less coefficients. Secondly, compared with the linearly interpolated LUT, the quadratically interpolated LUT has higher accuracy, which is adopted to realise a part of the mathematical computations in the predistortion. The proposed solution is validated on a real PA ZFL‐2500. It reduces the number of the model's coefficients and achieves a spectrum regrowth suppression of about 15 dB with a table size of only 8. [ABSTRACT FROM AUTHOR]

A new digital predistortion technique based on a direct learning architecture is proposed for linearising power amplifiers (PAs) with nonlinear memory effects. It is based on the non-uniform memory polynomial (MP) model and with a quadratically interpolated LUT. There are mainly two innovations. First, compared with the conventional MP model, the non-uniform MP model achieves the same modelling accuracy with less coefficients. Secondly, compared with the linearly interpolated LUT, the quadratically interpolated LUT has higher accuracy, which is adopted to realise a part of the mathematical computations in the predistortion. The proposed solution is validated on a real PA ZFL-2500. It reduces the number of the model's coefficients and achieves a spectrum regrowth suppression of about 15 dB with a table size of only 8. [ABSTRACT FROM AUTHOR]