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This paper presents an experimental platform for regulating the DC motor angular speed powered by photovoltaic cells. The experimental platform comprises an Eco Green Energy EGE-260P-60 solar panel, DC/DC SEPIC converter, DC bus, DC/DC buck converter, DC motor and Nexys 4 board with an Artix-7 100T FPGA. The DC/DC SEPIC converter is used for harvesting the maximum amount of energy from the PV cells using the perturb and observe algorithm to track the maximum power point. The DC/DC buck converter is used as the motor drive using the active disturbance rejection control to regulate the angular speed of the DC motor. In addition, the FPGA architecture design is presented using a hierarchical top-down methodology with the VHDL hardware description language and Xilinx System Generator tool. The software takes advantage of the FPGA's concurrency to simultaneously evaluate the different processes, which is the main reason for choosing this digital device. Several tests were performed on the platform such as irradiance changes, DC bus variations, DC motor connection and load torque variations applied in the motor shaft. The results indicate that the maximum power is obtained from the photovoltaic cells, establishing the minimum operating conditions. In addition, the control approach estimates and cancels the effects of disturbances caused by variations in the environmental conditions, photovoltaic system, DC bus, and load changes in order to regulate DC motor speed. [ABSTRACT FROM AUTHOR]

This study presents a passivity-based controller for a single-phase active rectifier–DC motor (SPAR-DCM) system. The main objective in the mechanical stage (DCM) is to regulate and maintain the desired angular speed of the motor under sudden load torque changes. Moreover, in the electric power stage, namely single-phase active rectifier (SPAR), the power factor (PF) should stay close to unity. We designed an Online Algebraic Estimator (OAE) to estimate the load torque parameter, adapted to the linear controller based on the exact static error dynamic passive output feedback (ESEDPOF) to minimize its effects. To synchronize the SPAR-DCM system with the grid, we used a second-order general integrator phase-locked loop to generate the necessary reference signals for the ESEDPOF controller. The arithmetic processing is programmed at medium-scale field-programmable gate array Spartan-6 XC6SLX16 through a detailed architecture design in 32 bits and in floating point, according to the standard IEEE-754. Experimental results verified the correctness and effectiveness of the proposed control algorithm. Furthermore, we demonstrated that the PF value is close to unity through power quality measurements. [ABSTRACT FROM AUTHOR]