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This study provides necessary condition (lower bound) and sufficient condition (upper bound) for the existence of Solid Burst (SB) errors locating PCD’s codes within a sub-block where the length of the code is assumed that it is split up into a fix number of identically sized sub-blocks. An example of such a code is also provided. The codes obtained here have been compared with the previously existing codes that are capable to detect and locate the repeated burst errors. [ABSTRACT FROM AUTHOR]

Quantum error correction lies at the heart of building reliable quantum information processing systems. Stabilizer codes, a fundamental class of quantum errorcorrecting codes, play a pivotal role in mitigating the adverse effects of noise and decoherence in quantum systems. This paper introduces a novel construction of quantum stabilizer codes using Hadamard difference sets, an elegant mathematical concept derived from combinatorial design theory. In this paper, the construction of the quantum stabilizer codes over non- cyclic Hadamard difference sets with parameters (4m²,2m²-m, m²-m), where m is a positive integer is discussed. Firstly, the parity check matrices are constructed from the Circulant permutation matrices with the help of Hadamard difference sets and then, the Symplectic inner product condition for Hadamard difference sets over binary operation for parity check matrices are obtained to affirm the commutative condition for Stabilizer operators which is vital for the error detection. For application, we constructed a Hadamard difference sets with parameters (16,6,2) for m = 2 of ordered pair of the group Z2 Z8 × (non-cyclic group) and quantum stabilizer codes are obtained by parity-check matrix. [ABSTRACT FROM AUTHOR]

A column‐weight k$k$ LDPC code with the parity‐check matrix H$H$ is called decomposable if there exists a permutation π$\pi$ on the rows of H$H$, such that π(H)${\pi }(H)$ can be decomposed into k$k$ column‐weight one matrix. In this paper, some variations of edge coloring of graphs are used to construct some column‐weight three decomposable LDPC codes with girths at least six and eight. Applying the presented method on several known classes of bipartite graphs, some classes of column‐weight three decomposable LDPC codes are derived having flexibility in length and rate. Interestingly, the constructed parity‐check matrices based on the proper edge coloring of graphs can be considered as the base matrix of some high rate column‐weight three quasi‐cyclic (QC) LDPC codes with maximum‐achievable girth 20. The paper also leads to a simple characterization of elementary trapping sets of the decomposable codes based on the chromatic index of the corresponding normal graphs. This characterization corresponds to a simple search algorithm finds all possible existing elementary trapping sets in a girth‐6 or girth‐8 column‐weight 3 LDPC code which are layered super set of a short cycle in the Tanner graph of the code. Simulation results indicate that the QC‐LDPC codes with large girths lifted from the constructed base matrices have good performances over AWGN channel. [ABSTRACT FROM AUTHOR]

In this paper, we construct new types of codes, called Weighted Block-wise Burst Error Correcting Codes (Weighted BBEC Codes), which are an improvement on the previously known block wise burst error correcting codes in the sense of their weight, i.e., (n = n1 + n2, k) linear codes that correct all the bursts of length b1 (fixed) with the weight w1(w1 ≤ b1) or more (less) in the first sub-block of length n1 and all the bursts of length b2 (fixed) with the weight w2 or more (less) in the next sub-block of length n2. [ABSTRACT FROM AUTHOR]

...-ispotty-byte error correcting codes over Zq [7] are non-binary codes generalizing the binary irregular-spotty-byte codes [3] suitable for semiconductor memories in which a word is divided into irregular bytes not necessarily of the same length. The distance between distinct words is measured in terms of newly defined ... - metric function [7]. In this paper, we present the code construction methods of ...-ispotty-byte error correcting codes in terms of their parity check matrix. [ABSTRACT FROM AUTHOR]

In this work, we determine new linear equations for the weight distribution of linear codes over finite chain rings. The identities are determined by counting the number of some special submatrices of the parity-check matrix of the code. Thanks to these relations we are able to compute the full weight distribution of codes with small Singleton defects, such as MDS, MDR and AMDR codes. [ABSTRACT FROM AUTHOR]

Nested linear coding is a widely used technique in wireless communication systems for improving both security and reliability. Some parameters, such as the relative generalized Hamming weight and the relative dimension/length profile, can be used to characterize the performance of nested linear codes. In addition, the rank properties of generator and parity-check matrices can also precisely characterize their security performance. Despite this, finding optimal nested linear secrecy codes remains a challenge in the finite-blocklength regime, often requiring brute-force search methods. This paper investigates the properties of nested linear codes, introduces a new representation of the relative generalized Hamming weight, and proposes a novel method for finding the best nested linear secrecy code for the binary erasure wiretap channel by working from the worst nested linear secrecy code in the dual space. We demonstrate that our algorithm significantly outperforms the brute-force technique in terms of speed and efficiency. [ABSTRACT FROM AUTHOR]

The traditional LDPC encoding and decoding system is characterized by low throughput and high resource consumption, making it unsuitable for use in cost-efficient, energy-saving sensor networks. Aiming to optimize coding complexity and throughput, this paper proposes a combined design of a novel LDPC code structure and the corresponding overlapping decoding strategies. With regard to structure of LDPC code, a CCSDS-like quasi-cyclic parity check matrix (PCM) with uniform distribution of submatrices is constructed to maximize overlap depth and adapt the parallel decoding. In terms of reception decoding strategies, we use a modified 2-bit Min-Sum algorithm (MSA) that achieves a coding gain of 5 dB at a bit error rate of 10 − 6 compared to an uncoded BPSK, further mitigating resource consumption, and which only incurs a slight loss compared to the standard MSA. Moreover, a shift-register-based memory scheduling strategy is presented to fully utilize the quasi-cyclic characteristic and shorten the read/write latency. With proper overlap scheduling, the time consumption can be reduced by one third per iteration compared to the non-overlap algorithm. Simulation and implementation results demonstrate that our decoder can achieve a throughput up to 7.76 Gbps at a frequency of 156.25 MHz operating eight iterations, with a two-thirds resource consumption saving. [ABSTRACT FROM AUTHOR]

In this article, a graph-theoretic method (taking advantage of constraints among sets associated with the corresponding parity-check matrices) is applied for the construction of a double low-density parity-check (D-LDPC) code (also known as LDPC code pair) in a joint source-channel coding (JSCC) system. Specifically, we pre-set the girth of the parity-check matrix for the LDPC code pair when jointly designing the two LDPC codes, which are constructed by following the set constraints. The constructed parity-check matrices for channel codes comprise an identity submatrix and an additional submatrix, whose column weights can be pre-set to be any positive integer numbers. Simulation results illustrate that the constructed D-LDPC codes exhibit significant performance improvement and enhanced flexible frame length (i.e., adaptability under various channel conditions) compared with the benchmark code pair. [ABSTRACT FROM AUTHOR]

In this paper, two polar code-based identification schemes are proposed in which the polar codes are used instead of random codes. The security of the proposed identification schemes is based on the hardness of coding problems such as general decoding problem (GDP) and syndrome decoding problem (SDP). By exploiting the properties of polar codes in the proposed identification schemes, it does not need to save the parity check or generator matrix of polar codes completely as a public data. Therefore, the public data size of the proposed identification schemes is reduced up to 90% in comparison with the Stern and Veron identification schemes. Also, by using the efficient techniques of seed generation and compression, it is shown that the communication costs of the proposed identification schemes are reduced up to 53% compared to the Stern and Veron identification schemes. Moreover, security analyses show that the proposed identification schemes have low cheating probability and also have proper resistance against information set decoding attack. [ABSTRACT FROM AUTHOR]

The large number of inexpensive and energy-efficient terminals in IoT systems is one of the emerging elements of the recent landscape of information and communication technologies. IoT nodes are usually embedded systems with limited processing power devices and strict requirements on energy consumption. In this paper, we consider the design and implementation of a part of the IoT communication uplink stack, namely the error correction coding scheme, for energy-efficient operation. We examine how an efficient rate-adaptive coding scheme, namely the Raptor-like (RL) quasi-cyclic (QC) subclass of low-density parity check (LDPC) codes, can be applied. We present an encoding algorithm designed for an embedded CPU; a respective QC-RL-LDPC decoding scheme, based on typical LDPC iterative decoding; and a combined design procedure for construction of the QC-RL-LDPC parity check matrices. Next, we conduct experiments to explore the time intervals for implemented encoding and the goodput of the coding system with incremental redundancy. We provide the statistical results by combining the measured energy consumption of the encoder and the simulated radio transmitter energy consumption. We demonstrate the comparison of normalized energy consumption statistics with the fixed-rate LDPC coding case. As conclusion, we note that under an unknown channel corruption level, the short block QC-RL-LDPC code implemented in the CPU can achieve higher energy efficiency per information bit compared to a fixed-rate LDPC code. Future work will include an extension of the work to nonbinary QC-RL-LDPC coding design. [ABSTRACT FROM AUTHOR]

Reliability of Static Random Access Memories (SRAMs) is immensely affected by radiation induced soft errors. Multiple Cell Upsets (MCUs) are caused by these soft errors and this lead to data corruption in several SRAM cells. Error Correcting Codes are normally exploited to alleviate the effect of MCUs. Single Error Correction–Double Error Detection (SEC–DED) codes are not the appropriate preference against MCUs rather these codes are suitable for protecting SRAM cells against Single Cell Upset. Single Error Correction–Double Error Detection–Double Adjacent Error Correction (SEC–DED–DAEC) codes are more suitable due to increasing trends of single and double-adjacent errors in SRAM cells. In this paper, a new SEC–DED–DAEC code has been proposed which is proficient of correcting single and double-adjacent errors in SRAMs. Our newly proposed code has been termed as Single and Double-adjacent Error Correcting Code (SDECC). Proposed codecs have been designed by employing new parity check matrices for different word lengths which are frequently applied in memory. The mis-correction probability of proposed SDECC codes are up to 88.24% and 80.67% lesser for 2-random and 3-random bit errors respectively with respect to related existing designs. Proposed codecs have been replicated and synthesized in ASIC environment. It is observed that area and power consumption of the proposed codecs are reduced up to 8.93% and 21.47% compared to the recently published results respectively. [ABSTRACT FROM AUTHOR]

The occurrences of Multiple Cell Upset (MCU) are more liable to arise in modern memory systems with the continuous upgradation of microelectronics technology from micron to deep submicron scales. These MCUs are mainly induced due to radiations in memory systems. Error Correcting Codes (ECCs) with lower design complexity are generally preferred for the mitigation of MCUs. The major drawback of the existing ECC is requiring higher overheads as error correction capability increases. In this paper, authors have proposed a new class of high performance t -bit Burst Error Correcting (BEC) codes. Parity check matrices (H) have been proposed for 3-bit and 4-bit BEC codes with word lengths of 16-bit, 32-bit and 64-bit. Also a simplified decoding scheme has been introduced for these codes. The proposed codecs have been designed and implemented in FPGA and ASIC platforms. The proposed codecs are compact in area, faster in speed and efficient in power compared to existing related schemes. But these lower design constrains are achieved at the cost of increase in redundancy. So, the proposed codecs can be employed in applications where redundancy is not the only constrain for correcting t -bit burst errors caused by MCUs. [ABSTRACT FROM AUTHOR]

The goal of this paper is to construct the linear code, and its dual which corresponding to classification of projective line PG(1,31), we will present Some important results of coding theory, the generator matrix of every linear code in PG(1,31) is found, A parity check matrix is also found . The mathematical programming language GAP was a main computing tool . [ABSTRACT FROM AUTHOR]

This paper studies the blind recognition method of the sparse parity‐check matrices of low‐density parity‐check codes in noncooperative communication, which is critical to the reverse analysis of communication protocols using LDPC codes. In this paper, two improvements are made to the algorithm of Liu Qian et al. (2021) for this problem. Firstly, a Gaussian elimination method based on random column exchange and soft information is proposed to enhance the fault tolerance of the elimination process. Secondly, according to the sparse property of the parity‐check matrices of LDPC codes, a random extraction method is proposed to further improve the fault tolerance of the algorithm, and it is verified theoretically. Finally, simulations verify the superior performance of the algorithm proposed in this paper. [ABSTRACT FROM AUTHOR]

In this paper, codes over the direct product of two finite commutative chain rings are studied. The standard form of the parity-check matrix is determined. The structure of self-dual codes is described. A distance preserving Gray map from the direct product of chain rings to a finite field is defined. Two upper bounds on minimum distance are obtained. [ABSTRACT FROM AUTHOR]

Since their rediscovery in the early 1990s, low-density parity-check (LDPC) codes have become the most popular error-correcting codes owing to their excellent performance. An LDPC code is a linear block code that has a sparse parity-check matrix. Cycles in this matrix, particularly short cycles, degrade the performance of such a code. Hence, several methods for counting short cycles in LDPC codes have been proposed, such as Fan's method to detect 4-cycles, 6-cycles, 8-cycles, and 10-cycles. Unfortunately, this method fails to count all 6-cycles, i.e., ignores numerous 6-cycles, in some given parity-check matrices. In this paper, an improvement of this algorithm is presented that detects all 6-cycles in LDPC codes, as well as in general bipartite graphs. Simulations confirm that the improved method offers the exact number of 6-cycles, and it succeeds in detecting those ignored by Fan's method. [ABSTRACT FROM AUTHOR]

We propose a multidimensional reconciliation encoding algorithm based on a field-programmable gate array (FPGA) with variable data throughput that enables quantum key distribution (QKD) systems to be adapted to different throughput requirements. Using the circulatory structure, data flow in the most complex pipeline operation in the same time interval, which enables the structural multiplexing of the algorithm. We handle the calculation and storage of eight-dimensional matrices cleverly to conserve resources and increase data processing speed. In order to obtain the syndrome more efficiently, we designed a simplified algorithm according to the characteristics of the FPGA and parity-check matrix, which omits the unnecessary operation of matrix multiplication. The simplified algorithm could adapt to different rates. We validated the feasibility and high speed of the algorithm by implementing the multidimensional reconciliation encoding algorithm on a Xilinx Virtex-7 FPGA. Our simulation results show that the maximum throughput could reach 4.88 M symbols/s. [ABSTRACT FROM AUTHOR]

For the identification of Reed‐Solomon (RS) codes, the existing methods need to test the possible codeword length and the primitive polynomials exhaustively. Exhaustive search leads to high computational complexity. To overcome this limitation and fulfill the requirement in practice, a fast blind identification method is proposed. Different with most methods, our identification method is discussed in Galois Field of 2. First, by using Gaussian elimination, the bit matrix is transformed to the simplest upper triangular form. If the assumed codeword length is right, the matrix is of deficient rank, and the parameters of an RS code can be estimated according to the rank. The null space of the matrix, defined as the equivalent binary parity check matrix, can also be obtained from the simplification result. Then, a candidate set of primitive polynomials is constructed according to the estimated codeword length. By using the matrix null space, the correctness of a candidate primitive polynomial is tested through matrix analysis. Finally, by combining the estimated parameters, the generator polynomial of an RS code is identified. To decrease the bit errors in the matrix, soft‐decision data is used to select reliable bits. Experimental results show the effectiveness and robustness of our method. [ABSTRACT FROM AUTHOR]

We present two lower bounds on sub-packetization level $\alpha $ of MSR codes with parameters $(n, k, d=n-1, \alpha)$ where $n$ is the block length, $d$ is the number of helper nodes contacted during single-node repair, $\alpha $ the sub-packetization level and $k\alpha $ the scalar dimension. The first bound we present is for any MSR code and is given by $\alpha \ge e^{\frac {(k-1)(r-1)}{2r^{2}}}$. The second bound we present is for the case of optimal-access MSR codes and the bound is given by $\alpha \ge \min \left\{{ r^{\frac {n-1}{r}}, r^{k-1} }\right\}$. There exist optimal-access MSR constructions that achieve the second sub-packetization level bound with an equality making this bound tight. We also prove that for an optimal-access MSR code to have optimal sub-packetization level under the constraint that the $\beta $ scalar symbol indices we access from a given helper node is dependent only on the index of the failed node, it is necessary that the support of the parity-check matrix be the same as the support structure of the existing MSR constructions in literature such as the Clay code. [ABSTRACT FROM AUTHOR]

This paper presents a unifying framework to construct low-density parity-check (LDPC) codes with associated Tanner graphs of desired girth. Towards this goal, we highlight the role that a certain square matrix that appears in the product of the parity-check matrix with its transpose has in the construction of codes with graphs of desired girth and further explore it in order to generate the set of necessary and sufficient conditions for a Tanner graph to have a given girth between 6 and 12. For each such girth, we present algorithms to construct codes of the desired girth and we show how to use them to compute the minimum necessary value of the lifting factor. For girth larger than 12, we show how to use multi-step graph lifting methods to deterministically modify codes in order to increase their girth. We also give a new perspective on LDPC protograph-based parity-check matrices by viewing them as rows of a parity-check matrix equal to the sum of certain permutation matrices and obtain an important connection between all protographs and those with variable nodes of degree 2. We also show that the results and methodology that we develop for the all-one protograph can be used and adapted to analyze the girth of the Tanner graph of any parity-check matrix and demonstrate how this can be done using a well-known irregular, multi-edge protograph specified by the NASA Consultative Committee for Space Data Systems (CCSDS). Throughout the paper, we exemplify our theoretical results with constructions of LDPC codes with Tanner graphs of any girth between 6 and 14 and give sufficient conditions for a multi-step lifted parity-check matrix to have girth between 14 and 22. [ABSTRACT FROM AUTHOR]

The traditional definition of Integrated Interleaved (II) codes generally assumes that the component nested codes are either Reed-Solomon (RS) or shortened Reed-Solomon codes. By taking general classes of codes, we present a recursive construction of Extended Integrated Interleaved (EII) codes into multiple layers, a problem that brought attention in literature for II codes. The multiple layer approach allows for a hierarchical scheme where each layer of the code provides for a different locality. In particular, we present the erasure-correcting capability of the new codes and we show that they are ideally suited as Locally Recoverable codes (LRC) due to their hierarchical locality and the small finite field required by the construction. Properties of the multiple layer EII codes, like their minimum distance and dimension, as well as their erasure decoding algorithms, parity-check matrices and performance analysis, are provided and illustrated with examples. Finally, we will observe that the parity-check matrices of high layer EII codes have low density. [ABSTRACT FROM AUTHOR]

Although long polar codes with successive cancellation decoding can asymptotically achieve channel capacity, the performance of short blocklength polar codes is far from optimal. Recently, Arıkan proposed employing a convolutional pre-transformation before the polarization network, called polarization-adjusted convolutional (PAC) codes. In this paper, we focus on improving the performance of short PAC codes concatenated with a cyclic redundancy check (CRC) outer code, CRC-PAC codes, since error detection capability is essential in practical applications, such as the polar coding scheme for the control channel. We propose an enhanced adaptive belief propagation (ABP) decoding algorithm with the assistance of CRC bits for PAC codes. We also derive joint parity-check matrices of CRC-PAC codes suitable for iterative BP decoding. The proposed CRC-aided ABP (CA-ABP) decoding can effectively improve error performance when partial CRC bits are used in the decoding. Meanwhile, the error detection ability can still be guaranteed by the remaining CRC bits and adaptive decoding parameters. Moreover, compared with the conventional CRC-aided list (CA-List) decoding, our proposed scheme can significantly reduce computational complexity, to achieve a better trade-off between the performance and complexity for short PAC codes. [ABSTRACT FROM AUTHOR]

A block code is called a locally recoverable code (LRC for short) with $(r,\delta)$ -locality, if subject to any $\delta -1$ erasure failures, every symbol in the encoding can still be recovered by accessing at most $r$ other symbols. Recently, it was discovered by several authors that a $q$ -ary optimal $(r,\delta)$ -LRC, i.e., an LRC achieving the generalized Singleton-type bound, can have length much bigger than $q+1$. This is quite different from the classical $q$ -ary MDS codes where it is conjectured that the code length is upper bounded by $q+1$ (or $q+2$ for some special cases). In this paper, we further investigate constructions of optimal $(r,\delta)$ -LRCs along the line of using parity-check matrices. Inspired by classical Reed-Solomon codes and the work in Jin (2019), we equip parity-check matrices with the Vandermonde structure. It turns out that a parity-check matrix with the Vandermonde structure that produces an optimal LRC must obey certain disjoint property for subsets of $\mathbb {F}_{q}$. We manage to show the existence of these disjoint subsets. Thus, this yields an optimal $(r,\delta)$ -LRC with code length $\Omega \left({q^{\frac {\delta }{2}\left({1+\frac {1}{\lfloor \frac {d-1}{\delta }\rfloor -1}}\right)}}\right)\vphantom {\bigg)_{j}}$ , where $d$ is the minimum distance. In particular, to our surprise, for $\delta =2$ this disjoint condition is equivalent to a well-studied problem in extremal graph theory. With the help of extremal graph theory, we succeed to improve all of the best known results in Guruswami et al. (2018) for $d\geq 7$. In addition, for $d=6$ , we are able to remove the constraint required in Jin (2019) that $q$ is even. [ABSTRACT FROM AUTHOR]

The rth generalized Hamming weight of a linear [n, k] code C is the cardinality of the smallest support of any r-dimensional subcode of C. In this paper, we obtain the generalized Hamming weights of the binary linear codes whose parity check matrices are the incidence matrices of the Cartesian product of graphs. We also determine the rth generalized Hamming weights of their dual codes. [ABSTRACT FROM AUTHOR]

Nonvolatile memories (NVMs) have been widely studied in the post-Moore era. However, noise/defect in NVMs has brought a challenging reliability problem in write/read access operations. A linear error correction code (ECC) has been widely used in memories to correct errors. In general, a codec hardware is required to encode or decode the information, resulting in area and energy overhead. In this article, we propose a new approach to implement the ECC codec by exploiting the existing write and read peripheral circuitry of NVMs based on an in-memory computing (IMC) architecture. In our approach, the desired code words can be generated through using write-like logic operations, given the original information and generation matrix during the encoding (write) process, while syndrome vectors (or error correction) can also be achieved through using read-like logic operations, given the parity-check matrix during the decoding (read) process, respectively. Therefore, we do not need a specific codec hardware but exploit the write-like and read-like logic operations. With an emerging toggle spin torque magnetic random access memory (TST-MRAM) and Hamming code as an example, we validated the feasibility of our approach and evaluated the performance of the design in the 40-nm technology node. The results show that our approach can significantly reduce energy consumption compared with state-of-the-art designs. [ABSTRACT FROM AUTHOR]

We propose a novel approach to optimization of irregular nonbinary (NB) quasi-cyclic (QC)-LDPC codes over small alphabets. In this approach, first, the base parity-check matrices are constructed by a simulated annealing method, and then these matrices are labeled by the field elements while maximizing the so- called generalized girth of the Tanner graph. In order to analyze the performance of the constructed irregular NB LDPC codes, a new ensemble of irregular NB LDPC codes over the extensions of the binary Galois field is introduced. A finite-length random coding bound on the error probability of the maximum-likelihood (ML) decoding over the binary phase shift keying (BPSK) input AWGN channel for the new code ensemble is derived. The frame error rate (FER) performance of the sum-product belief-propagation (BP) decoding of the constructed NB QC-LDPC block codes is compared to that of both the optimized binary QC-LDPC block codes in the 5G standard and the best known NB QC-LDPC codes as well as to the derived random coding bound on the ML decoding error probability. It is shown that the obtained bound predicts the behavior of BP decoding performance of practical NB QC-LDPC codes more accurately than the BP decoding thresholds do. [ABSTRACT FROM AUTHOR]

An MRD code (n , k , n − k + 1) is a k -dimensional q N -linear subspace of the n -dimensional vector space q N n over q N for n ≤ N. Linear codes ′ (n ′ , k ′ , d) (of length n ′ ≥ n , dimension k ′ ≥ k) that are obtained from MRD codes (n , k , d) satisfying the property ′ ∩ ′ ⊥ = { 0 } are defined to be LCD MRD codes. An inherent relationship between the generator G and parity-check matrices H of LCD MRD codes is observed. This in fact identifies LCD MRD codes as trivial (G G T = I) and nontrivial (G G T ≠ I) codes. Further, two classes of LCD MRD codes of length n ℓ are constructed from ℓ (trivial and nontrivial) LCD MRD codes of length n. Examples are provided for demonstration of results obtained. [ABSTRACT FROM AUTHOR]

Reed-Solomon (RS) codes are used in many storage systems for failure recovery. In popular software implementations, RS codes are defined by using a parity check matrix that is either a Cauchy matrix padded with an identity or a Vandermonde matrix. The encoding complexity can be reduced by searching for a Cauchy matrix that has a smaller number of ‘1's in its bit matrices or exploiting Reed-Muller (RM) transform in the Vandermonde matrix multiplication. This article proposes two new approaches that improve upon the previous schemes. In our first approach, different constructions of finite fields are explored to further reduce the number of ‘1's in the bit matrices of the Cauchy matrix and a new searching method is developed to find the matrices with minimum number of ‘1's. Our second approach defines RS codes using a parity check matrix in the format of a Vandermonde matrix concatenated with an identity matrix so that the multiplication with the inverse erasure columns in the encoding is eliminated and the decoding can be carried out using simplified formulas. The Vandermonde matrix in such an unconventional RS code definition needs to be constructed using finite field elements in non-consecutive order. A modification is also developed in this article to enable the application of the RM transform in this case to reduce the matrix multiplication complexity. For 4-erasure-correcting RS codes over $GF(2^8)$ G F (2 8) , the two proposed approaches increase the encoding throughput by 40 and 15 percent on average over the prior works based on Cauchy matrix and Vandermonde matrix with RM transform, respectively, for a range of codeword length. Moreover, the decoding throughput is also significantly improved. [ABSTRACT FROM AUTHOR]

Let C be a code with parity-check matrix H. A stopping set S of size l ≤ n for H is an l-columns submatrix of Hs of H which dose not contain a row with weight one. In this paper we consider the code which parity-check matrix is incidence matrix of complete graph Km. These codes are LDPC codes and we obtain the stopping sets for these codes. [ABSTRACT FROM AUTHOR]

An end-to-end joint source–channel (JSC) encoding matrix and a JSC decoding scheme using the proposed bit flipping check (BFC) algorithm and controversial variable node selection-based adaptive belief propagation (CVNS-ABP) decoding algorithm are presented to improve the efficiency and reliability of the joint source–channel coding (JSCC) scheme based on double Reed–Solomon (RS) codes. The constructed coding matrix can realize source compression and channel coding of multiple sets of information data simultaneously, which significantly improves the coding efficiency. The proposed BFC algorithm uses channel soft information to select and flip the unreliable bits and then uses the redundancy of the source block to realize the error verification and error correction. The proposed CVNS-ABP algorithm reduces the influence of error bits on decoding by selecting error variable nodes (VNs) from controversial VNs and adding them to the sparsity of the parity-check matrix. In addition, the proposed JSC decoding scheme based on the BFC algorithm and CVNS-ABP algorithm can realize the connection of source and channel to improve the performance of JSC decoding. Simulation results show that the proposed BFC-based hard-decision decoding (BFC-HDD) algorithm (ζ = 1) and BFC-based low-complexity chase (BFC-LCC) algorithm (ζ = 1, η = 3) can achieve about 0.23 dB and 0.46 dB of signal-to-noise ratio (SNR) defined gain over the prior-art decoding algorithm at a frame error rate (FER) = 10 − 1 . Compared with the ABP algorithm, the proposed CVNS-ABP algorithm and BFC-CVNS-ABP algorithm achieve performance gains of 0.18 dB and 0.23 dB, respectively, at FER = 10 − 3 . [ABSTRACT FROM AUTHOR]

Recently, there have been continuous rising interests of multi-bit error correction codes (ECCs) for protecting memory cells from soft errors which may also enhance the reliability of memory systems. The single error correction and double error detection (SEC-DED) codes are generally employed in many high-speed memory systems. In this paper, Hsiao-based SEC-DED codes are optimized based on two proposed optimization algorithms employed in parity check matrix and error correction logic. Theoretical area complexity of SEC-DED codecs require maximum 49.29%, 18.64% and 49.21% lesser compared to the Hsiao codes [M. Y. Hsiao, A class of optimal minimum odd-weight-column SEC-DED codes, IBM J. Res. Dev.14 (1970) 395–401], Reviriego et al. codes [P. Reviriego, S. Pontarelli, J. A. Maestro and M. Ottavi, A method to construct low delay single error correction codes for protecting data bits only, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.32 (2013) 479–483] and Liu et al. codes [S. Liu, P. Reviriego, L. Xiao and J. A. Maestro, A method to recover critical bits under a double error in SEC-DED protected memories, Microelectron. Reliab.73 (2017) 92–96], respectively. Proposed codec is designed and implemented both in field programmable gate array (FPGA) and ASIC platforms. The synthesized SEC-DED codecs need 31.14% lesser LUTs than the original Hsiao code. Optimized codec is faster than the existing related codec without affecting its power consumption. These compact and faster SEC-DED codecs are employed in cache memory to enhance the reliability. [ABSTRACT FROM AUTHOR]

In this paper we consider an error-detecting code based on linear quasigroups. Namely, each input block a 0 a 1 ... a n - 1 is extended into a block a 0 a 1 ... a n - 1 d 0 d 1 ... d n - 1 , where the redundant characters d 0 , d 1 , ... , d n - 1 are defined with d i = a i ∗ a i + 1 ∗ a i + 2 , where ∗ is a linear quasigroup operation and the operations in the indexes are modulo n. We give a proof that under some conditions the code is linear. Using this fact, we contribute to the determination of the error-detecting capability of the code. Namely, we determine the Hamming distance of the code and from there we obtain the number of errors that the code will detect for sure when linear quasigroups of order 4 from the best class of quasigroups of order 4 for which the constant term in the linear representation is zero matrix are used for coding. All results in the paper are derived for arbitrary length of the input blocks. With the obtained results we showed that when a small linear quasigroup of order 4 from the best class of quasigroups of order 4 is used for coding, the number of errors that the code surely detects is upper bounded with 4. [ABSTRACT FROM AUTHOR]

A large class of MDS linear codes is constructed. These codes are endowed with an efficient decoding algorithm. Both the definition of the codes and the design of their decoding algorithm only require from Linear Algebra methods, making them fully accessible for everyone. Thus, the first part of the paper develops a direct presentation of the codes by means of parity-check matrices, and the decoding algorithm rests upon matrix and linear maps manipulations. The somewhat more sophisticated mathematical context (non-commutative rings) needed for the proof of the correctness of the decoding algorithm is postponed to the second part. A final section locates the Reed-Solomon skew-differential codes introduced here within the general context of codes defined by means of skew polynomial rings. [ABSTRACT FROM AUTHOR]

To provide reliable transmissions with flexible rates for satellite communications, this paper presents a novel method of constructing multi-rate quasi-cyclic low-density parity-check (LDPC) codes. The basic idea is to generate low-rate codes from a high-rate mother code by combining shortening and extending, which ensures that the generated code family owns the same code length, in order to maintain the same frame structure. The code construction involves the design of base matrices and exponent matrices for the designed codes. A progressive row elimination and addition algorithm is proposed for designing the code base matrices from a high rate to low rates. This algorithm leads to the nested and systematic structure of the parity-check matrices, which are desirable for practical implementations of their encoders and decoders, while ensuring the optimal decoding thresholds. In addition, we construct a circulation coefficient matrix based on finite fields and select the optimal rows in this matrix to construct exponent matrices while considering of cycle structures. We demonstrate that the designed codes achieve better performance for all the code rates than the LDPC codes in DVB-S2X standards. In addition, the proposed codes do not exhibit error floors for their block error rates down to 10−5. [ABSTRACT FROM AUTHOR]

Maximum distance profile (MDP) convolutional codes have the property that their column distances are as large as possible for given rate and degree. There exists a well-known criterion to check whether a code is MDP using the generator or the parity-check matrix of the code. In this paper, we show that under the assumption that n − k divides δ or k divides δ , a polynomial matrix that fulfills the MDP criterion is actually always left prime. In particular, when k divides δ , this implies that each MDP convolutional code is noncatastrophic. Moreover, when n − k and k do not divide δ , we show that the MDP criterion is in general not enough to ensure left primeness. In this case, with one more assumption, we still can guarantee the result. [ABSTRACT FROM AUTHOR]

Layered decoding (LD) facilitates a partially parallel architecture for performing belief propagation (BP) algorithm for decoding low-density parity-check (LDPC) codes. Such a schedule for LDPC codes has, in general, reduced implementation complexity compared to a fully parallel architecture and higher convergence rate compared to both serial and parallel architectures, regardless of the codeword length or code-rate. In this paper, we introduce a modified shuffling method which shuffles the rows of the parity-check matrix (PCM) of a quasi-cyclic LDPC (QC-LDPC) code, yielding a PCM in which each layer can be produced by the circulation of its above layer one symbol to the right. The proposed shuffling scheme additionally guarantees the columns of a layer of the shuffled PCM to be either zero weight or single weight. This condition has a key role in further decreasing LD complexity. We show that due to these two properties, the number of occupied look-up tables (LUTs) on a field programmable gate array (FPGA) reduces by about 93% and consumed on-chip power by nearly 80%, while the bit error rate (BER) performance is maintained. The only drawback of the shuffling is the degradation of decoding throughput, which is negligible for low values of E b / N 0 until the BER of 1e−6. [ABSTRACT FROM AUTHOR]

As an important coding scheme in modern distributed storage systems, locally repairable codes (LRCs) have attracted a lot of attentions from perspectives of both practical applications and theoretical research. As a major topic in the research of LRCs, bounds and constructions of the corresponding optimal codes are of particular concerns. In this work, codes with $(r,\delta)$ -locality which have optimal minimal distance w.r.t. the bound given by Prakash et al. are considered. Through parity-check matrix approach, constructions of both optimal $(r,\delta)$ -LRCs with all symbol locality ($(r,\delta)_{a}$ -LRCs) and optimal $(r,\delta)$ -LRCs with information locality ($(r,\delta)_{i}$ -LRCs) are provided. As a generalization of a work of Xing and Yuan, these constructions are built on a connection between sparse hypergraphs and optimal $(r,\delta)$ -LRCs. With the help of constructions of large sparse hypergraphs, the lengths of codes obtained from our construction can be super-linear in the alphabet size. This improves upon previous constructions when the minimal distance of the code is at least $3\delta +1$. As two applications, optimal H-LRCs with super-linear lengths and GSD codes with unbounded lengths are also constructed. [ABSTRACT FROM AUTHOR]

Magic tricks based on I binary i Hamming codes are well known. Ternary and quinary cases are easier because the ring is same as the field for primes In the ternary trick, we first consider the ternary -Hamming code:. The number of the cards of Joker happens to be that makes the trick nice. In this article we generalize binary tricks to present magic card tricks based on Hamming codes over finite fields of 3, 4, and 5 elements. [Extracted from the article]

In this paper, we analyze the error floor of quasi-cyclic (QC) low-density parity-check (LDPC) codes decoded by the sum-product algorithm (SPA) with row layered message-passing scheduling. For this, we develop a linear state-space model of trapping sets (TSs) which incorporates the layered nature of scheduling. We demonstrate that the contribution of each TS to the error floor is not only a function of the topology of the TS, but also depends on the row layers in which different check nodes of the TS are located. This information, referred to as TS layer profile (TSLP), plays an important role in the harmfulness of a TS. As a result, the harmfulness of a TS in particular, and the error floor of the code in general, can significantly change by changing the order in which the information of different layers, corresponding to different row blocks of the parity-check matrix, is updated. We also study the problem of finding a layer ordering that minimizes the error floor, and obtain row layered decoders with error floor significantly lower than that of their flooding counterparts. As part of our analysis, we make connections between the parameters of the state-space model for a row layered schedule and those of the flooding schedule. Simulation results are presented to show the accuracy of analytical error floor estimates. [ABSTRACT FROM AUTHOR]

In cognitive radio context, the coding parameters are unknown at the receiver. The design of an intelligent receiver is essentially to identify these parameters from the received data blindly. In this paper, we are interested in the blind identification of binary linear block codes from received noisy data. In order to recognize the code length, the concept of the normalized column weight vector is defined and cosine similarity is used to measure the difference between linear block codes and random codes. Then, the correct code length could be obtained by finding the local minimum of cosine similarity. The proposed code length recognition method needs no prior knowledge about the codes, which results in completely blind identification. To reconstruct the parity check matrix, the concept of association rules mining is introduced to the problem of blind identification of channel codes for the first time. Furthermore, five criteria are proposed to reduce the redundant rules mined by the association rules mining algorithm and to recognize the parity check vectors effectively. Simulations show that the proposed two methods have excellent performance even in a high error rate transport environment. The performance comparisons with existing methods validate the advantages of our two proposed methods. [ABSTRACT FROM AUTHOR]

There is a local ring I of order 4, without identity for the multiplication, defined by generators and relations as I = ⟨ a , b ∣ 2 a = 2 b = 0 , a 2 = b , a b = 0 ⟩. We give a natural map between linear codes over I and additive codes over F 4 , that allows for efficient computations. We study the algebraic structure of linear codes over this non-unital local ring, their generator and parity-check matrices. A canonical form for these matrices is given in the case of so-called nice codes. By analogy with Z 4 -codes, we define residue and torsion codes attached to a linear I-code. We introduce the notion of quasi self-dual codes (QSD) over I, and Type IV I-codes, that is, QSD codes all codewords of which have even Hamming weight. This is the natural analogue of Type IV codes over the field F 4. Further, we define quasi Type IV codes over I as those QSD codes with an even torsion code. We give a mass formula for QSD codes, and another for quasi Type IV codes, and classify both types of codes, up to coordinate permutation equivalence, in short lengths. [ABSTRACT FROM AUTHOR]

With low-density parity-check (LDPC) codes and polar codes selected as the standard codes for the fifth generation (5 G) enhanced Mobile Broad Band scenario (eMBB), a decoding architecture that can simultaneously support the decoding of control and data plane becomes necessary at the terminal side to meet the raising requirement for 5 G network deployment. Due to the special structure of LDPC codes according to the Release 15 (R15) 5 G standard, a straight-forward extension of the existing reconfigurable scheme is in general difficult. Therefore in this paper, a unified decoding architecture is proposed that can be reconfigured to either LDPC codes or polar codes. Due to various differences between the two codes such as parity-check matrices, codeword lengths and iterative methods, a joint decoding algorithm is introduced by reordering basic decoding operations to the unified add-comparison-add pattern for both codes. Then, a pipelined structure of reconfigurable decoding unit (RDU) is presented correspondingly which is fully compatible with all decoding patterns of the R15 standard. And finally, a reconfigurable decoder is proposed with multiple levels of parallelism, and the reconfiguration scheme is introduced to improve the hardware utilization and decoding efficiency. The proposed decoder is implemented in FPGA and ASIC, respectively, and has achieved state-of-the-art performance in throughput and area efficiency compared to LDPC-only and polar-only decoders. [ABSTRACT FROM AUTHOR]

Linear nested codes, where two or more sub-codes are nested in a global code, have been proposed as candidates for reliable multi-terminal communication. In this article, we consider nested array-based spatially coupled low-density parity-check (SC-LDPC) codes and propose a line-counting based optimization scheme for minimizing the number of dominant absorbing sets in order to improve its performance in the high signal-to-noise ratio regime. Since the parity-check matrices of different nested sub-codes partially overlap, the optimization of one nested sub-code imposes constraints on the optimization of the other sub-codes. To tackle these constraints, a multi-step optimization process is applied first to one of the nested codes, then sequential optimization of the remaining nested codes is carried out based on the constraints imposed by the previously optimized sub-codes. Results show that the order of optimization has a significant impact on the number of dominant absorbing sets in the Tanner graph of the code, resulting in a trade-off between the performance of a nested code structure and its optimization sequence: the code which is optimized without constraints has fewer harmful structures than the code which is optimized with constraints. We also show that for certain code parameters, dominant absorbing sets in the Tanner graphs of all nested codes are completely removed using our proposed optimization strategy. [ABSTRACT FROM AUTHOR]

In his pioneering work on LDPC codes, Gallager dismissed codes with parity-check matrices of weight two after proving that their minimum Hamming distances grow at most logarithmically with their code lengths. In spite of their poor minimum Hamming distances, it is shown that quasi-cyclic LDPC codes with parity-check matrices of column weight two have good capability to correct phased bursts of erasures which may not be surpassed by using quasi-cyclic LDPC codes with parity-check matrices of column weight three or more. By modifying the parity-check matrices of column weight two and globally coupling them, the erasure correcting capability can be further enhanced. Quasi-cyclic LDPC codes with parity-check matrices of column weight three or more that can correct phased bursts of erasures and perform well over the AWGN channel are also considered. Examples of such codes based on Reed-Solomon and Gabidulin codes are presented. [ABSTRACT FROM AUTHOR]

We develop a systematic theory for the construction of quantum codes from classical Reed–Solomon over F p k , where p is prime and k ∈ Z + . Based on two classical [ n , n - d m + 1 , d m ] Reed–Solomon codes over F p k , we provide the construction of an [ [ n , n + n e - 2 (d m - 1) , d m ] ] entanglement-assisted Reed–Solomon code over qudits of dimension d = p k that saturates the quantum Singleton bound and needs n e entangled qudits, which involves obtaining the explicit form of the stabilizers for the code. Our contributions towards the entanglement-assisted Reed–Solomon code are multi-fold as follows: (a) Based on the parity check matrices of the classical Reed–Solomon codes, the explicit form of the stabilizers of the entanglement-assisted Reed–Solomon code are provided and the rate-optimal code is obtained. (b) Based on the entanglement-assisted Reed–Solomon code, a burst error correcting code for qudits of dimension p that corrects a burst of k (t m - 1) qudits or less, where t m = ⌊ (d m - 1) / 2 ⌋ is provided. (c) Finally, we provide amenable circuits for encoding and error correction with quantum circuit complexity of O (n 2) , useful for practical implementations. [ABSTRACT FROM AUTHOR]