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In many fields, e.g., ground-penetrating radar and ultra-wideband radiation, a high-pulse-repetition-frequency (PRF) and high-time-base-stability sub-nanosecond pulser is required, and its output waveform should be close to a gaussian pulse. In this article, the transistorized pulser is studied and optimized to improve its output parameters. The printed circuit board circuit parameters of the pulser are first optimized, which is beneficial for the amplitude and the rise time. To improve the time base stability, the collector voltage ramp triggering mode is adopted to replace the conventional base triggering mode for the pulser. For higher PRF, the pulser with the capacitance–transistor parallel structure is immersed in the fluorinert liquid. Moreover, the deficit-charge method is adopted, and small charging capacitances are used in the last few stages to weaken the oscillation in the pulse falling edge. From experimental results, the amplitude of the optimized pulser is 1.35 kV, its rise time is reduced from about 200 to 135 ps, the maximum PRF is improved from 250 to 500 kHz, the pulse jitter is reduced to 22 ps, and the pulse drift is reduced from hundreds of ps/min to 47 ps/min. Meanwhile, the oscillation in its falling edge is greatly suppressed. [ABSTRACT FROM AUTHOR]

Modern IC designs are exposed to a wide range of dynamic variations. Traditionally, a conservative timing guardband is required to guarantee correct operations under the worst-case variation, thus leading to performance degradation. To remove the guardband, resilient circuits are proposed. However, the short-path padding (hold time fixing) problem in resilient circuits is far severer than conventional IC design. Therefore, in this paper, we focus on the short-path padding problem to enable the timing error detection and correction mechanism of resilient circuits. Unlike recent prior work adopts greedy heuristics with a local view, we determine the padding values and locations with a global view. Moreover, we utilize spare cells and a dummy metal to further achieve the derived padding values at physical implementation. Experimental results show that our method is promising to validate timing error-resilient circuits. [ABSTRACT FROM PUBLISHER]

Clock power is the major contributor to dynamic power for modern integrated circuit design. A conventional single-bit flip-flop cell uses an inverter chain with a high drive strength to drive the clock signal. Clustering several such cells and forming a multibit flip-flop can share the drive strength, dynamic power, and area of the inverter chain, and can even save the clock network power and facilitate the skew control. Hence, in this paper, we focus on postplacement multibit flip-flop clustering to gain these benefits. Utilizing the properties of Manhattan distance and coordinate transformation, we model the problem instance by two interval graphs and use a pair of linear-sized sequences as our representation. Without enumerating all possible combinations, we identify only partial sequences that are necessary to cluster flip-flops, thus leading to an efficient clustering scheme. Moreover, our fast coordinate transformation also makes the execution of our algorithm very efficient. The experiments are conducted on industrial circuits. Our results show that concise representation delivers superior efficiency and effectiveness. Even under timing and placement density constraints, clock power saving via multibit flip-flop clustering can still be substantial at postplacement. [ABSTRACT FROM AUTHOR]

This paper presents an annular-structure lateral-diffused metal–oxide–semiconductor (LDMOS) RF transistor using a 0.5-\mum LDMOS process. This paper also examines the dc, small-signal, and large-signal characteristics of RF LDMOS transistors with different closed structures. In particular, the problem of evaluating the LDMOS aspect ratio for annular structure is addressed. The capacitance characteristics improvement in the LDMOS device design using the annular structure was also investigated. The power gain and efficiency of annular structure give nearly 5% enhancement compared to the traditional structure with 80-\mum gatewidth at 1.9 GHz. Results show that the annular structure appears to be a better layout design for RF LDMOS transistors. [ABSTRACT FROM AUTHOR]