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Abstract: This paper deals with the analysis of the parallelization of irregular reductions, a frequent operation found in many irregular applications, in the context of a shared-memory model. Locality exploitation is a classical problem in computer architecture and compiler design that presently still plays a fundamental role due to the growing gap between memory and processor speeds. This work contributes a formal description of the design space of locality-based parallel irregular reductions, which is used to achieve a quantitative analysis of them. The model allows to determine behavioural aspects in the methods that may influence their performance. Several parallel compiler techniques for irregular reductions are placed and examined within this model. Experimental evaluation is also presented, under various locality conditions, and the results were compared to those derived from the model. [Copyright &y& Elsevier]