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Detailed physics of the third quadrant electrical characteristics of 1.2-kV rated 4H-SiC accumulation (Acc) and inversion (Inv) channel MOSFETs, based on experimentally measured data and TCAD numerical simulations, are described in this paper for the first time. The power MOSFETs with various channel lengths (0.3, 0.5, 0.8, 1.1 $\mu \text{m}$) used in this paper were fabricated in a 6-in commercial foundry. Numerical simulations verified that there are two current paths in the third quadrant: 1) through the base region and 2) through the p-n body diode. This paper demonstrates that the Acc MOSFETs have a smaller third quadrant knee voltage (${V}_{{\text {knee}}})$ of −1.2 V compared with −1.9 V for the Inv MOSFETs (at ${V}_{g} = {0}$ V and room temperature). Numerical simulations show that this difference is due to a smaller potential barrier for electron transport from the drain to the source in the base region for accumulation channel devices than inversion channel devices. Acc devices are shown to have a lower voltage drop in the third quadrant. [ABSTRACT FROM AUTHOR]

In this paper, a microfluidic device is introduced based on direct current (dc) dielectrophoresis for the separation of circulating tumor cells from normal blood cells. Differential sidewall electrodes are designed inside the channel and two middle-channel outlets are located after the end of the electrodes, which are assigned to collect the normal blood cells. A maximum dc potential of 3 V is applied to the electrodes, resulting in a differential dielectrophoretic forces acting on the cells. This paper involves isolating MCF-7 breast cancer cells from white blood cells (WBCs) and red blood cells (RBCs), eliminating the demand for primary RBC lysis. Numerical simulation results revealed that the differential electrodes not only suppressed successfully the need for high applied voltages by dc dielectrophoresis but also diminished the joule heating effects. Besides that, the arrangement of the differential electrodes was observed to play a critical role in the separation performance. In particular, designing the outlets, as well as adjusting the electrode potentials, has effectively assisted the device to be tunable for different cancer cells even with different radii. More strikingly, the ability of the device to deflect the waste cells (WBCs and RBCs) to out of the microchannel prior to the cancer cells was proven to positively affect the separation efficiency and purity. The proposed device was capable of separating different cells leveraging various diameters with capture purity and efficiency of higher than 83% and 100%, respectively. [ABSTRACT FROM AUTHOR]

The dielectric screening property of a semiconductor is very crucial for the electrical characteristics of a MOSFET, and which can be described mathematically by Poisson equation via the permittivity. While the theory and experiments have corroborated the permittivity reduction of nanoscale Si, this paper studies the electrical characteristics of MOSFETs considering the reduced channel permittivity by quantum transport simulations. It is found that the channel permittivity reduction may mitigate the short-channel effects, showing subthreshold swing improvement and threshold voltage shift of MOSFETs in nanoscale. Compared to quantization effects, the positive and negative impacts of the channel permittivity reduction on the devices in particularly nanoscale have been investigated. This paper elucidates the necessity of considering semiconductor permittivity reduction for nanoscale device design and simulations. [ABSTRACT FROM AUTHOR]

The instability of amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) under ultraviolet (UV) light was thoroughly investigated in this paper. Unlike in a darkened state, an off-state leakage current can be found in the dual-sweep I–V transfer curve of a-IGZO TFTs under UV light illumination. Furthermore, despite the same UV light condition, the forward sweep and reverse sweep show different I–V curves, representing two different physical mechanisms. First, the subthreshold swing degradation and threshold voltage shift to the negative direction in the forward sweep are due to the total channel barrier lowering and can be confirmed by changing the light exposure region. Second, in the reverse sweep, the suggested back-channel leakage current can be controlled by dual-gate TFTs. UV light exposure of the metal–insulator–semiconductor–metal structure verifies that the off-state leakage current passes through the back channel in a reverse sweep. Finally, the physical mechanism links between forward and reverse sweeps have comprehensive interpretation in this paper. [ABSTRACT FROM AUTHOR]

Oxide semiconductors are highly attractive for fabrication of large-area thin-film electronics because of their high electrical performance, low process temperature, high uniformity, and ease of industrial manufacturing. n-type oxide semiconductors, such as InGaZnO, are highly developed and have already been commercialized for backplane drivers of flat-panel displays. To date, developing CMOS technology is still an urgent issue in order to build low-power electronic circuits based on oxide semiconductors. In this paper, various CMOS circuits, including inverters, NAND, NOR, XOR, d-latches, full adders, and 7-, 11-, 21-, and 51-stage ring oscillators (ROs), are fabricated based on sputtered p-type tin monoxide and n-type InGaZnO. The inverters show rail-to-rail output voltage behavior, low average static power consumption of 8.84 nW, high noise margin level up to ~40% supply voltage, high yield of 98%, and high uniformity with negligible standard deviation. The NAND, NOR, XOR, d-latches, and full adders show desirably ideal input–output characteristics. The performances of ROs indicate small stage delay of $\sim 1~\mu \text{s}$ , extremely high uniformity and high yieldwhich are essential for large-area thin-film electronics. This paper may inspire constructions of low power, large area, large scale, and high-performance transparent/flexible CMOS circuits fully based on oxide semiconductors for applications beyond flat-panel displays. [ABSTRACT FROM AUTHOR]

Inverter delay is often evaluated as $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ , where ${C}$ is the load capacitance, ${V}_{\text {dd}}$ is the supply voltage, and ${I}_{\text {eff}}$ is the effective drive current derived by approximating the inverter switching trajectory with a linear model. The ${I}_{\text {eff}}$ model utilizes high and low drain currents conventionally measured in wafer acceptance tests and does not require extraction of any parameters. Ease of use combined with reasonable accuracy (~15%) is the main reason for wide application of $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ delay metrics. However, $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ expression produces large errors when applied to another two important basic circuits: NAND and NOR. This is because NAND and NOR circuits contain transistor series connections not accounted for in the inverter model. In this paper, an analytical solution for the transistor series connection influence on the discharge/charge operation in NAND/NOR circuits is provided. The model for NAND/NOR effective drive current (denoted as ${I}_{\text {stack}}$) developed in this paper maintains simplicity of the original ${I}_{\text {eff}}$ expression. It requires only one additional measurement of the linear current. Model accuracy was assessed by comparing to extensive SPICE delay simulations of NAND and NOR circuits designed using state-of-the-art MOS technologies. Comparison results show that $\textit {CV}_{\text {dd}}/{I}_{\text {stack}}$ equation provides ~15% accuracy for NAND/NOR circuits in line with $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ accuracy for inverter. In an era of emphasis on low-power design, the developed model presents convenient means of exploring design space when optimizing circuit supply voltage for low-power operation. [ABSTRACT FROM AUTHOR]

The minimum specific ON-resistance $\text{R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ of the semisuperjunction (semi-SJ) device is realized in this paper. Based on the similar SJ optimization method in our previous works, the minimum $\text{R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ of the semi-SJ is searched by optimizing both the semi-SJ and the N-buffer regions. The proposed design formulas give the optimized doping concentration $\text{N}_{\textsf {SJ}}$ of the semi-SJ region, doping concentration $\text{N}_{\textsf {B}}$ , and length $\text{L}_{\textsf {B}}$ of the N-buffer region, respectively. As examples, 1000- and 1500-V semi-SJ devices are designed with the formulas. The calculated results are in a good agreement with the simulations. The comparisons between the simulations and the existing experiments demonstrate that the optimization in this paper realizes lower $\text{R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ under the same breakdown voltage $\text{V}_{\textsf {B}}$ even with a shorter SJ length. [ABSTRACT FROM AUTHOR]

In this paper, we propose a model for estimating short-channel effects (SCEs) in the shell-doped double-gate junctionless (JL) MOSFET. The main emphasis of this paper is to estimate SCEs by effectively capturing source/drain (S/D) extensions beyond the gate edges for different values of undoped core thickness (${T}_{\textsf {core}}$), shell doping (${N}_{\textsf {d}}$), gate length (${L}_{\textsf {g}}$), and gate (${V}_{\textsf {gs}}$) and drain (${V}_{\textsf {ds}}$) biases in subthreshold regime. The threshold voltage (${V}_{\textsf {th}}$), drain-induced barrier lowering and subthreshold swing (${S}$), extracted from transfer characteristics, are in good agreement with the simulation results. Results highlight the utility of shell doping and core thickness to provide an additional degree of freedom to control SCEs. The proposed model can be useful in estimating SCEs and optimizing core–shell JL architecture for low-power applications. [ABSTRACT FROM AUTHOR]

The introduction of metal nanocrystals (NCs) has been confirmed to improve electrical uniformity of oxide-based resistive random access memory (RRAM) devices significantly; however, the current reports do not systematically elucidate the relationship between the size/distribution of NCs and the electrical uniformity of RRAM devices. In this paper, we focused on the impact of metal NCs size and areal density on the resistive switching (RS) performances of oxide RRAM by atomic layer deposition (ALD) based on the experimental results and theoretical calculation. The dependence of ALD cycles of 50–130 during Pt or CoPtx NCs growth on the RS parameters of Al2O3 or HfO2 memory units has been evaluated systematically. The RRAM embedded Pt or CoPtx NCs shows the trends: with increasing ALD cycles, the forming voltage, set/reset voltage, the resistance in off and on state, and ${R}_{ \mathrm{\scriptscriptstyle OFF}}/{R}_{ \mathrm{\scriptscriptstyle ON}}$ ratio entirely first decrease, then flatten, and increase later with a minimum value at about 100 cycles. Although all metal NCs with various sizes enhance the electric field strength compared to at the planar region, only metal NCs with proper NCs size and areal density (9 nm/6– $10\times 10^{\textsf {11}}$ /cm2 in this paper) can effectively produce stronger localized electric field at the tip of metal NCs, leading to optimal RS behavior. [ABSTRACT FROM AUTHOR]

In this paper, we report on the assessment of self-amplified silicon–oxide–nitride–oxide–silicon (SONOS) memory device architecture for sub-50-nm gate length (${L}_{g}$) through calibrated simulations. Self-amplification (SA) effect in tunnel field-effect transistor-based SONOS (T-SONOS) memory device has been analyzed. Results show that memory window ($\Delta {W}$) in T-SONOS cell increases as buried oxide thickness increases due to capacitive coupling between the front and back gates. Although the enhanced $\Delta {W}$ can also be achieved in inversion-mode SONOS (I-SONOS) device, its performance is deteriorated when the gate length is scaled down. We have compared the performance of I-SONOS and T-SONOS memory devices for ${L}_{g}$ varying from 100 to 25 nm. Results highlight that I-SONOS device cannot be programmed at ${L}_{g} ={25}$ nm and thus deteriorate the memory operation. However, SA T-SONOS at ${L}_{g} = {25}$ nm achieves ${W} \sim {6}$ V. In addition, the effect of underlap on the performance of T-SONOS cell has been analyzed, and it is shown that memory operation of 25-nm T-SONOS device can further improved with a drain side underlap of 20 nm. This paper provides new opportunities to design SA T-SONOS memory device for the next-generation nonvolatile memories. [ABSTRACT FROM AUTHOR]

The application of capacitive deep trench isolation (CDTI) as a shared vertical transfer gate (VTG) in a back-side-illuminated CMOS image sensor pixel is investigated using 3-D device-level simulations. The parasitic capacitance existence between CDTI and deeply buried pinned photodiode (BPD), and also between CDTI and floating diffusion (FD) region, makes the charge transfer process more difficult. In order to design a lag-free pixel and obtain complete charge transfer from BPD to FD, various considerations regarding the device-level design should be taken into account which is discussed in this paper. A CDTI neighboring two pixels can be functionalized as a shared VTG. Using CDTI as shared VTG facilitates pixel miniaturization and can result in more circuit integration at the pixel surface. This paper proposes a ${2}\,\,\mu \text{m} \times {2}\,\,\mu \text{m}$ pixel with CDTI as shared VTG, an equilibrium full-well capacity of 4605 e−, and a complete charge transfer from BPD to FD. [ABSTRACT FROM AUTHOR]

In this paper, the pinning process of pinned photodiodes (PPDs) is described by a new analytical model, assuming the PPD to be composed of inner and junction regions. There are two definitions of the pinning potential: maximum conduction band potential variation ($\Delta \varphi _{M}$) and maximum electron quasi-fermi level potential variation ($\Delta $ FP $_{M}$). The output of the previous pinning potential models is only an approximation of $\Delta \varphi _{M}$. In this paper, a comprehensive model is proposed in which both aforementioned definitions of pinning potential can be achieved analytically. The proposed model is a system of equations relating PPD’s main characteristics such as $\Delta \varphi _{M}$ and equilibrium full-well capacity to other main PPD parameters such as PPD spatial dimensions, impurity dopant concentrations, maximum inner region potential, and remnant carrier population at $\Delta \varphi _{M}$. The proposed model is verified by two previously reported experiment-based data. [ABSTRACT FROM AUTHOR]

Stacks of 2-D materials, known as van der Waals (vdW) heterostructures, have gained vast attention due to their interesting electrical and optoelectronic properties. This paper presents an intuitive circuit model for the out-of-plane electrostatics of a vdW heterostructure composed of an arbitrary number of layers of 2-D semiconductors, graphene, or metal. We explain the mapping between the out-of-plane energy band diagram and the elements of the equivalent circuit. Although the direct solution of the circuit model for an n-layer structure is not possible due to the variable, nonlinear quantum capacitance of each layer, this paper uses the intuition gained from the energy band picture to provide an efficient solution in terms of a single variable. Our method employs Fermi–Dirac statistics while properly modeling the finite density of states (DOS) of 2-D semiconductors and graphene. The approach circumvents difficulties that arise in commercial TCAD tools, such as the proper handling of the 2-D DOS and the simulation boundary conditions when the structure terminates with a nonmetallic material. Based on this methodology, we have developed 2dmatstacks, an open-source tool freely available on nanohub.org. Overall, this paper equips researchers to analyze, understand, and predict experimental results in complicated vdW stacks. [ABSTRACT FROM AUTHOR]

This paper proposes a semianalytical model to estimate short-channel effects for independent gate operation in double-gate (DG) junctionless (JL) MOSFET incorporating gate-to-source/drain underlap, through the solution of Poisson’s equations in the subthreshold regime. The model also accounts for the asymmetry in device operation through variation in gate oxide thicknesses, gate work functions, and underlap lengths. Subthreshold drain current, threshold voltage, and subthreshold swing, evaluated from the channel potential, show reasonable agreement with simulation data. Results suggest the use of negative back gate bias and longer underlap length to reduce off-current. This paper highlights the role of doping, underlap length, and back gate bias in tuning the threshold voltage. This model serves as a generic formulation (within limits) with different asymmetries to estimate, design, and optimize self-aligned DG JL transistors for subthreshold logic applications. [ABSTRACT FROM AUTHOR]

4H-silicon carbide (SiC) is a suitable candidate for high-temperature and radiation prone applications, due to its superior electrical and material properties. Several researchers have demonstrated small-scale logic circuits, entirely in 4H-SiC; however, to build a complete electronic module in 4H-SiC, a memory component is yet to be developed. This paper presents for the first time the design, optimization, and performance analysis of a 4H-SiC-based bipolar memory column including a static random access memory cell and peripherals, designed for voltages as low as 5 V. The memory column has average noise margins of 2 V and delays in the range of few nanoseconds at room temperature. The proposed memory architecture also demonstrates robust operation across a wide range of temperatures (27 °C–500 °C) with stable noise margins and speeds. This paper validates the potential of developing memory architectures in 4H-SiC, which operates reliably for varying conditions, paving the way to build complete electronic systems entirely based on 4H-SiC. [ABSTRACT FROM AUTHOR]

Performance limitations of superjunction (SJ) devices due to charge imbalance (CI) are analyzed in this paper. It is demonstrated that in the presence of CI, the specific on-resistance has a quadratic dependence on blocking voltage, similar to a conventional drift region. We also show that by designing the SJ structure with an optimally modified pillar doping, we can achieve better performance under conditions of CI. The design guidelines presented in this paper are applicable to any semiconductor, although all calculations are based on silicon carbide. [ABSTRACT FROM AUTHOR]

In this paper, a n-type junctionless FET (JLFET) with a p-type fin body (FB) is investigated using a 3-D numerical simulator. We show that the proposed device (FB-JLFET) with a p+ FB can control the electrostatic potential of the channel more efficiently for multi- ${V} _{\text{TH}}$ (threshold voltage) and dynamic threshold (DT) operation. Moreover, body bias application is implemented in FB-JLFET and a large body factor ($\gamma $) is predicted for wide range ${V} _{\text{TH}}$ modulation. Thanks to the stronger potential coupling between the channel and FB, the proposed device exhibits $\gamma $ improvement compared to the conventional JL bulk FinFETs under the same electrostatic control. In addition, DT operation is studied in the form of a JLFET for the first time and it exhibits 37% improvement of the on-state drive current and better subthreshold swing (S.S.) compared to FB-JLFET without DT. This paper provides the feasibility of multi- ${V} _{\text{TH}}$ operation with body bias mode for high performance or low-power applications and DT operation for high-speed circuits with low power consumption. [ABSTRACT FROM AUTHOR]

This paper aims to investigate a porous silicon (PS)-based edge termination for planar type ac switch. TRIAC device prototypes, specifically dedicated to evaluate blocking performances, are fabricated by integrating electrochemical etching in device processing. A mixed porous morphology containingmicro-, meso-, and macropores is obtained in a p-Type through-wafer-diffused via after anodization. The fabricated prototypes show PS-dependent blocking capabilities. The possible impacts of the anodization conditions and the physical features of PS on the electrical characteristics are discussed in detail. Low leakage currents (<10 µA) have been demonstrated up to several hundred voltages for both bias polarities. The forward blocking voltage decreases with increasing PS thickness, while an opposite trend is observed for the reverse blocking voltage. This paper confirms the interest of PS as a potential insulating material for power device manufacture. [ABSTRACT FROM AUTHOR]

Conventionally, integrated drain-extended MOS (DeMOS) like high-voltage devices are designed while keeping only performance targets for a given application in mind. In this paper, for the first time, performance and reliability codesign approach using 3-D TCAD has been presented for various superjunction (SJ) type DeMOS devices. In this context, how to effectively utilize the SJ concept in a DeMOS device for System on Chip applications, which often has stringent switching and RF performance targets, is explored in detail in this paper. Moreover, design and reliability tradeoffs for switching and RF applications are discussed, while considering two unique sets, one with fixed breakdown voltage and other with fixed ON-resistance. Finally, hot carrier generation, safe operating area concerns, and electrostatic discharge physics are explored and compared using 3-D TCAD simulations. [ABSTRACT FROM PUBLISHER]

In this paper, we develop an explicit model to predict the dc electrical behavior in ultrathin surrounding gate junctionless (JL) nanowire field-effect transistors (FETs). The proposed model considers 2-D electrical and geometrical confinements of carrier charge density within few discrete subbands. Combining a parabolic approximation of the Poisson equation, the first-order perturbation theory for the Schrödinger subband energy eigen-values and the Fermi–Dirac statistics for the confined carrier density lead to an explicit solution of the dc characteristic in ultrathin JL devices. Validity of the model has been verified with technology computer-aided design simulations. The results confirm its validity for all regions of operation, i.e., from deep depletion to accumulation and from linear to saturation. This represents an essential step toward analysis of circuits based on JL nanowire devices. [ABSTRACT FROM AUTHOR]

This paper deals with the design of an ac switch structure for specific ac mains applications 230 V–50 Hz. The targeted power level is about a hundred watts, and the currently used converter circuits make use of bidirectional switches that are realized using anti-series connected MOS transistors. Despite the improvements in performance provided by some of these structures, their fabrication cost is still high and limits their widespread diffusion in a market shared with the triac. To replace the triac, an original current and voltage bidirectional bipolar device called a Bipolar ac (Bipac) is proposed, designed, realized, and characterized. It can be controlled both to turn-on and turn-off with respect to a single reference electrode. It exhibits a very low ON-state voltage drop that makes it interesting for specific mains applications with low load current (0.5 $\text{A}_{{\text {rms}}}$). The study of the Bipac structure is carried out using 2-D Sentaurus physical simulations. The Bipac structure is realized on n-type and on p-type substrates for two different wafer thicknesses. The operating modes of the monolithic bidirectional Bipac switch were validated through electrical characterizations. [ABSTRACT FROM AUTHOR]

In this paper, we have reported a renovated silicon-based tunnel field-effect transistor (TFET) structure with a channel length of 21 nm. The proposed structure has been optimized and analytically modeled. The broken gate TFET (BG-TFET) shows very low ambipolar current, good subthreshold swing (SS) and ON-currents comparable to the contemporary structures of similar dimensions. The surface potential and the electric field inside the device are modeled by solving the 2-D Poisson’s equation. The drain current is also modeled based on Kane’s generation rate. The results obtained from the analysis are validated against Synopsys Sentaurus TCAD nonlocal tunneling model-based simulations. [ABSTRACT FROM AUTHOR]

In this paper, we present analytical models which are valid in all regions of operation and can accurately predict the potential profile and the output, as well as the transfer characteristics of the gate-all-around heterojunction tunnel field-effect transistors. Our potential model takes into account the charge carriers in the channel, as well as the space charges in the depletion regions of the two reservoirs. Later, this potential model is utilized to calculate the band-to-band tunneling generation rates at any spatial coordinate in the tunneling volume. Next, these rates are integrated over tunneling volume to find the total tunneling current. This leads to an analytical model for the drain current. We validate our models against the data obtained via numerical simulations for several common heterojunction tunnel devices at various geometries and bias conditions. [ABSTRACT FROM AUTHOR]

An analytical model for junctionless double-gate FETs (JLDGFETs) in the subthreshold region is proposed in this paper. As the analytical models based on Young’s approximation demonstrate certain limitations due to the heavily doped channel of the JLDGFET, it is essential to model the electrical characteristics of a JLDGFET using alternative methods. Therefore, in this paper, by using the Fourier series and Green’s function, the potential distribution ( \phi ( {x} , {y} )) in the channel is solved, and the hot-carrier effects and random dopant fluctuation are modeled using localized trap charges and macroscopic analysis. Using the calculated \phi (x, y), {I} _{{\mathsf {DS}}} and {V} _{{\mathsf {th}}} are solved analytically with respect to various L and t {\mathsf {ox}} variations, subthreshold swing, the drain-induced barrier lowering, the localized trap charges, and a single impurity dopant. All results from the analytical model are verified through comparisons with commercially available 2-D ATLAS numerical simulation results. [ABSTRACT FROM PUBLISHER]

Superjunction has arguably been the most creative and important concept in the power device field since the introduction of the insulated gate bipolar transistor (IGBT) in the 1980s. It is the only concept known today that has challenged and ultimately proved wrong the well-known theoretical study on the limit of silicon in high-voltage devices. This paper deals with the history, device and process development, and the future prospects of Superjunction technologies. It covers fundamental physics, technological challenges as well as aspects of design and modeling of unipolar devices, such as CoolMOS. The superjunction concept is compared to other methods of enhancing the conductivity of power devices (from bipolar to employment of wide-bandgap materials) to derive its set of benefits and limitations. This paper closes with the application of the superjunction concept to other structures or materials, such as terminations, superjunction IGBTs, or silicon carbide Field Effect Transistors (FETs). [ABSTRACT FROM AUTHOR]

This paper demonstrates the existence of dark current blooming in pinned photodiode (PPD) CMOS image sensors (CISs) with the support of both experimental measurements and TCAD simulations. It is usually assumed that blooming can appear only under illumination, when the charge collected by a pixel exceeds the full well capacity (FWC) (i.e., when the photodiode becomes forward biased). In this paper, it is shownthat blooming can also appear in the dark by dark current leakage from hot pixels in reverse bias (i.e., belowthe FWC). The dark current blooming is observed to propagate up to nine pixels away in the experimental images and can impact hundreds of pixels around each hot pixel. Hence, it can be a major image quality issue for the state-of-the-art PPD CISs used in dark current limited applications, such as low-light optical imaging and should be considered in the dark current subtraction process. This paper also demonstrates that one of the key parameter for dark current optimization, the transfer gate bias during integration, has to be carefully chosen depending on the application because the optimum bias for dark current reduction leads to the largest dark current blooming effects. [ABSTRACT FROM AUTHOR]

Resistive switching memory (RRAM) features many optimal properties for future memory applications that make RRAM a strong candidate for storage-class memory and embedded nonvolatile memory. This paper addresses the cycling-induced degradation of RRAM devices based on a HfO2 switching layer. We show that the cycling degradation results in the decrease of several RRAM parameters, such as the resistance of the low-resistance state, the set voltage V\mathrm{ set} , the reset voltage V\mathrm{ reset} , and others. The degradation with cycling is further attributed to enhanced ion mobility due to defect generation within the active filament area in the RRAM device. A distributed-energy model is developed to simulate the degradation kinetics and support our physical interpretation. This paper provides an efficient methodology to predict device degradation after any arbitrary number of cycles and allows for wear leveling in memory array. [ABSTRACT FROM AUTHOR]

This paper studies on the RF MEMS switch based on flexible liquid crystal polymer (LCP) substrate and the influence of the LCP substrate bending characteristics on mechanical properties of the switch. Due to the excellent properties of flexible LCP materials, RF MEMS devices based on LCP substrates will be very suitable for microwave systems with high space requirements and wearable devices. Obviously, the deformation of flexible substrate will affect the performance of RF MEMS switch. Therefore, this paper proposes a modeling of the substrate bending to analyze it. The experimental results of the fabricated switches show that the pull-in voltage of the switch is $\sim 22$ V, the insertion loss is better than −0.6 dB, the isolation is better than −15 dB, and the return loss is better than −18 dB up to 20 GHz. According to the experiments, we can find that when the curvature of the substrate is increased from zero to 22.2 (1/m), then the measured pull-in voltage is increased from 22.1 to 23.9 V and when the curvature of the substrate is increased from 22.2 to 44.2 (1/m), then the measured pull-in voltage is decreased from 23.9 to 18.9 V. In conclusion, with the increase of substrate curvature, the switch pull-in voltage will increase at first and then decrease. The experimental results are in good agreement with the modeling. [ABSTRACT FROM AUTHOR]

In this response, we show that the paper by Kim et al. by our group has a different research purpose and uses different modeling processes, which was not described in the previous work by Ortiz-Conde et al. The comments issued by Ortiz-Conde et al., who claim that our paper corresponds to a particular case of their previous work, are in our opinion overgeneralized. Differences compared to Ortiz-Conde’s previous work are discussed in detail. We also explain how the problem on threshold voltage pointed out by Ortiz-Conde et al. can be solved through a semiempirical method from measured data. [ABSTRACT FROM AUTHOR]

This paper presents a new model for parasitic extension resistance considering the effect of the spacer dielectric constant on the nanoplate-field-effect transistor (NP-FET) structure. Unlike the previous model that considers the accumulation carriers under the gate overlap, the newly proposed model is developed based on the extension surface potential, which is dependent on the spacer dielectric constant. In addition, surface mobility is redefined by considering the change of the surface electric field with respect to the changes of spacer material. The accuracy of the model was validated by changing physical parameters such as nanoplate width, thickness, source and drain bulk doping concentration, and spacer materials, and it was found that the errors were within 5% of the 3-D technology computer-aided design device simulation results. [ABSTRACT FROM AUTHOR]

In this paper, we present a novel generalized multiparticle drift-diffusion (mp-DD) model capable to overcome some limitations imposed by the classic drift-diffusion model by taking into account multiple carrier populations. We demonstrate the model’s ability and flexibility in simulating systems from different application contexts. We conclude that the developed mp-DD model allows investigating a wide range of complex mechanisms, such as subband charge transport calculation or intersystem crossing (ISC), which are crucial for the understanding and design of organic and inorganic semiconductor devices largely employed for both photovoltaics and light emitting applications. [ABSTRACT FROM AUTHOR]

In spite of the apparent simplicity of the system under study, compact modeling of complementary resistive switching (CRS) devices, i.e., two antiserially connected memristive structures, is by no means straightforward. This requires a deep understanding of the voltage drops occurring across the circuit elements and correct treatment of the so-called snapback (SB) effect typical of the breakdown process of a thin dielectric film in an MIS or a MIM structure. The SB effect fundamentally consists in a sudden reduction of the device resistance caused by the formation of a filamentary path spanning the insulator. Beyond this point, the filament widens keeping the voltage drop across its extremes constant. The consequence of disregarding this effect is clearly distinguishable in the simulated curves: progressive openings of the on-state windows for both positive and negative voltages instead of abrupt ones. In this paper, a modification is introduced in the original memdiode model for memristive devices in order to account for this remarkable feature. Ta2O5-based CRS devices are considered to demonstrate the suitability of our approach. [ABSTRACT FROM AUTHOR]

A novel fast-switching lateral-insulated gate bipolar transistor (LIGBT) with double gates and integrated Schottky barrier diode (SBD) is proposed and studied in this paper by TCAD simulation. In order to reduce the turn-off time and maintain a low forward voltage drop, the proposed structure introduces an integrated SBD structure at the anode and an additional trench gate at the cathode. First, the integrated SBD provides an extra electron extraction path and the additional trench gate enhances the injection of the N+-cathode. Furthermore, the insulated oxide pillar between the N-buffer and integrated SBD further reduces the snapback voltage. Finally, the simulation results show that the turn-off time of the conventional LIGBT is 52.4% larger than that of trench/planar gate SBD (TP-SBD) LIGBT under the same forward voltage of 1.49 V. Moreover, the latch current density of TP-SBD LIGBT is increased by nearly 200% compared to that of the conventional LIGBT, while almost the same latch voltage is obtained, so the proposed TP-SBD LIGBT can improve the latch immunity. [ABSTRACT FROM AUTHOR]

In this paper, a super-junction p-type lateral diffused metal–oxide–semiconductor transistor (SJ-pLDMOS) utilizing electron to enhance the current capability is proposed. The proposed SJ-pLDMOS has an n-channel in the drain region and is controlled by an auto-generated voltage signal (${V}_{\mathrm {\textsf {Gn}}}$). The voltage signal ${V}_{\mathrm {\textsf {Gn}}}$ is generated during the ON- and OFF-state of the hole current which flows across an integrated resistor (${R}\text{p}$) implemented in the p-base region. Thus, the proposed SJ-pLDMOS utilizes both hole and electron currents to significantly enhance the current capability. Simulation results show that the current capability of the proposed SJ-pLDMOS without any conductivity modulation effect is comparable with that of a super-junction nLDMOS (SJ-nLDMOS). The total power loss of the proposed super-junction pLDMOS (SJ-pLDMOS) is reduced by about 26.7% and 18% compared with that of the SJ-nLDMOS and Triple Resurf nLDMOS (TR nLDMOS) at a rated load current density of $25~\mu \text{A}/\mu \text{m}$ , respectively. [ABSTRACT FROM AUTHOR]

In this paper, an analytical model has been proposed to evaluate the effect of temperature on gate-induced drain leakages (GIDL) in a dual-metal nanowire field-effect transistor. Surface potential, electric field ${E} _{z}$ , and GIDL current ${I}_{\text {GIDL}}$ have been formulated and analyzed by solving 2-D Poisson’s equation with appropriate boundary conditions. The calefaction effect has also been inspected for potential and hole concentration contour plot along with in depth analysis of conduction band energy and valence band energy. Drain-induced barrier lowering and electron velocity have also been examined. Furthermore, the effect of temperature on ${g} _{m}$ , ${g} _{d}$ , noise figure, and noise conductance has also been examined. [ABSTRACT FROM AUTHOR]

Near-interface traps (NITs) with energy levels aligned to the conduction band and spatially located close to the SiO2/SiC interface are responsible for significant degradation of the channel-carrier mobility in 4H-SiC MOSFETs. In this paper, we investigate fast trapping and detrapping of the conduction-band electrons by NITs with energy levels localized between 0.13 and 0.23 eV above the bottom of the conduction band. The trapping and detrapping times were estimated to be in the range between the resolution limit of tens of nanoseconds and $1~\mu \text{s}$ by measuring the current through n-type MOS capacitors in response to a ramped voltage in the accumulation region. [ABSTRACT FROM AUTHOR]

Silicon carbide (4H-SiC) devices experiencing avalanche conditions can reach temperatures above 1500 K. Simulation of impact ionization in devices should, therefore, include models valid up to such high temperatures. However, calibrations of impact ionization coefficients are available only up to 580 K, and simulations of switching show deviations from measurements at higher temperatures. In this paper, a more accurate model based on the underlying physics of high temperature and anisotropic avalanche generation is proposed. This model enables calibrations performed at room temperature along the ${c}$ -axis to be more precisely extrapolated to any temperature of interest in 2-D device simulations. The model provides an excellent fit to the measurements of breakdown voltages during unclamped inductive switching tests of power MOSFETs, enabling a more accurate prediction of ruggedness. The more comprehensive physics included in the model makes it also applicable to other wide bandgap semiconductors such as GaN, diamond, and Ga2O3, which also exhibit a high critical electric field. [ABSTRACT FROM AUTHOR]

In this paper, the carrier transport mechanisms in AlN nucleation layers grown by MOCVD on p-Si and p-silicon-on-insulator (SOI) substrates were investigated by using electrical characterizations at various electric fields and temperatures on Ni-Au/AlN/Si metal–insulator–semiconductor capacitors. For the case of the AlN on Si substrate, different contact schemes, i.e., top–bottom versus top–top, have been compared. It was found by capacitance–voltage measurements that an inversion channel related to the Shockley–Read–Hall (SRH) minority carrier generation in the silicon bulk and SOI substrates was formed. It showed that the AlN on p-SOI platform exhibited the same leakage mechanisms as for the AlN on the Si substrate. The contact scheme mainly affects the low forward and reverse bias characteristics, by adding a surface leakage contribution. At increasing the forward (positive) gate bias, the carrier transport process becomes in turn ohmic, variable-range hopping, SRH generation, and Fowler–Nordheim (FN) direct tunneling. Moreover, at the reverse bias, the carrier transportation is in turn dominated by the Schottky emission, Poole–Frenkel (PF) conduction, and FN direct tunneling with increasing bias. [ABSTRACT FROM AUTHOR]

In this paper, the effect of negative-capacitance (NC) on germanium FinFET (GeFinFET) with the presence of fixed trap charges (${N}_{\text {ftc}}$) has been studied. The analysis of various parameters of NCGeFinFET has shown that the positive trap charges improve the device characteristics whereas the negative trap charges (NTC) degrade the performance of devices. Therefore, we have optimized properties of ferroelectric (FE) to suppress the degradation caused by NTC. Furthermore, the impact of ${N}_{\text {ftc}}$ has been studied on the output characteristics of NCGeFinFET inverter, and it has been shown that the degradation due to NTC reduces by optimizing the FE properties. It has also been demonstrated that NCGeFinFET exhibits excellently improved characteristics as compared to GeFinFET. [ABSTRACT FROM AUTHOR]

This paper presents a design-oriented charge-based model for dc operation of AlGaAs/GaAs and AlGaN/GaN-based high-mobility field-effect transistors. The intrinsic model is physics-based and does not introduce any empirical parameter. The central concept is based on the linear approximation of the channel charge density with respect to the surface potential, leading to explicit and continuous expressions for charges and current in all the regions of operation, including subthreshold. In addition, an effective circuit design methodology based on the pinchoff surface potential, the pinchoff voltage and the key concept of inversion coefficient (IC) is proposed, likewise for silicon MOSFET circuits. [ABSTRACT FROM AUTHOR]

A small-size vertical device with field plate is designed and experimentally realized in this paper. The modulation effect of the field plate causes an enhanced bulk electric field (ENBULF) and improves the breakdown voltage ${V}_{\textsf {B}}$. A 2-D electric field model is developed to give the ENBULF condition corresponding to the maximum ${V}_{\textsf {B}}$ and the optimal specific ON-resistance ${R}_{ \mathrm{ON},\textsf {sp}}$. Based on the model, the minimum figure of merit (FOM) (gate charge ${Q}_{\textsf {g}}\times \mathrm{\scriptstyle ON}$ -resistance ${R}_{ \mathrm{ON}}$) is discussed for a typical ENBULF device, i.e., the shield-gate vertical double diffused metal–oxide–semiconductor (SG-VDMOS). The calculated results are in good agreement with the simulations. Furthermore, a 35-V SG-VDMOS is analytically designed and experimentally implemented, which obtains a ${R}_{ \mathrm{ON},\textsf {sp}}$ of 4.4 $\text{m}\Omega \cdot \textsf {mm}^{2}$ and a gate to drain charge ${Q}_{\textsf {gd}}$ of 11.3 nC, respectively. The experiment realizes the minimal FOM and a ${R}_{ \mathrm{ON},\textsf {sp}}$ reduced by 28.6% when compared with the conventional “silicon limit.” [ABSTRACT FROM AUTHOR]

In this paper, we develop an accurate analytical electrostatic potential model for both the n-type and p-type double-gate heterostructure tunnel field-effect transistors (H-TFETs). We solve the Poisson’s equation in four distinct regions inside the device, the depletion regions of the source, channel, and drain, and the drift-diffusion region of the channel, where the mobile charge carriers should be taken into account. It is shown that the model predicts the electrostatic potential profile of the various heterostructure devices with different material systems in all regions of the device operation accurately. The potential model is used for developing a model for the tunneling distance at the given energy level. Due to the physical nature of the models, the influence of the transistor parameters on the electrostatic characteristics of H-TFETs with desired heterojunction materials may be easily pursued. We show that the model results accurately predict the numerical simulation results for different device parameters. [ABSTRACT FROM AUTHOR]

In this paper, we analyze the impact of length scaling on the ON-state operation of the two classes of double-gate negative capacitance transistors: metal–ferroelectric–metal–insulator–semiconductor (MFMIS) and metal–ferroelectric–insulator–semiconductor (MFIS). We show that for long-channel structures, MFMIS configuration shows a higher ON current than the MFIS due to a lower drain saturation voltage of the latter. For short-channel cases, we compare these negative capacitance field effect transistors (NCFETs) under two scenarios: equal flat band voltages (iso- ${V}_{\textsf {FB}}$) and equal OFF currents (iso- ${I}_{ \mathrm{\scriptscriptstyle OFF}}$). In iso- ${V}_{\textsf {FB}}$ condition, a higher negative differential conductance (NDC) effect in the MFMIS suppresses its ON current below that of the MFIS. However, the MFMIS provides a higher ON current than the MFIS for all the channel lengths under iso- ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ condition. We further investigate the influence of quantum mechanical effects and velocity saturation of carriers on the electrical characteristics of short-channel NCFETs. We also explore the impact of inner and outer spacer fringings in NCFETs. We find that the ferroelectric voltage gain in NCFETs with spacers increases with the channel length scaling, which provides a further improvement in the ON current contrary to those without spacers. Moreover, increase in the spacer permittivity also boosts both the ON current and the NDC. [ABSTRACT FROM AUTHOR]

Leakage phenomena are increasingly affecting the performance of nanoelectronic devices, and therefore, advanced device simulators need to include them in an appropriate way. This paper presents the modeling and implementation of direct source-to-drain tunneling (S/D tunneling), gate leakage mechanisms (GLMs) accounting for both direct tunneling and trap-assisted tunneling, and nonlocal band-to-band tunneling (BTBT) phenomena in a multissubband ensemble Monte Carlo (MS-EMC) simulator along with their simultaneous application for the study of ultrascaled fully depleted silicon-on-insulator, double-gate silicon-on-insulator, and FinFET devices. We find that S/D tunneling is the prevalent phenomena for the three devices, and it is increasingly relevant for short-channel lengths. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the relationship between size, shape, and the performance of the voltage-controlled magnetic anisotropy (VCMA)-based magnetic tunnel junctions (MTJs) suitable for gigabit scale MRAMs with 10 years of retention time. A Fokker–Planck simulation framework is developed to model the magnetization dynamics in the presence of thermal noise. Here, we numerically show that the optimization of the MTJ geometry can significantly improve the performance of the VCMA-based MTJs. Using an elliptical MTJ with aspect ratio (AR) of 3 reduces the required supply voltage and energy consumption by 80.7% and 92%, respectively, compared to a circular MTJ when the minimum feature size is 50 nm. The design requirements on the VCMA coefficient, ${\xi }$ , are also reduced by 67%. However, the influence of AR is observed to diminish with reduction in the minimum feature size of the MTJ. For instance, when the minimum feature size is 20 nm, the required supply voltage and energy consumption reduce only by 60.29% and 65.30%, respectively. We, then, perform a comprehensive scaling analysis on the VCMA-based MTJs by varying size, geometry, and ${\xi }$ of the MTJs. The predicted scaling trends are then compared with those of the STT MTJs. [ABSTRACT FROM AUTHOR]

This paper analyses the influence of the GaN and Si3N4 passivation (or “cap”) layer on the top of the AlGaN barrier layer on the performance and reliability of Schottky barrier diodes with a gated edge termination (GET-SBDs). Both GaN cap and Si3N4 cap devices show similar dc characteristics but a higher density of traps at the SiO2/GaN interface or/and an increase of the total dielectric constant in the access region result in higher $R_{\mathrm{ON}}$ -dispersion in GaN cap devices. The leakage current at medium/low temperatures in both types of devices shows two low-voltage-independent activation energies, suggesting thermionic and field-emission processes to be responsible for the conduction. Furthermore, a voltage-dependent activation energy in the high-temperature range occurs from low voltages in the GaN cap devices and limits their breakdown voltage (${V}_{\mathsf {BD}}$). Time-dependent dielectric breakdown measurements show a tighter distribution in Si3N4 cap devices (Weibull slope $\beta = {3.3}$) compared to GaN cap devices ($\beta = 1.8$). Additional measurements in plasma-enhanced atomic layer deposition (PEALD)-Si3N4 capacitors with different cap layers and TCAD simulations show an electric field distribution with a strong peak within the PEALD-Si3N4 dielectric at the GET corner, which could accelerate the formation of a percolation path and provoke the device breakdown in GaN cap SBDs even at low-stress voltages. [ABSTRACT FROM AUTHOR]

Resistive random access memory (ReRAM), a new emerging nonvolatile memory technology based on changes in electrical resistivity of a dielectric film, offers promising advantages such as scalability, fast switching, and low operation voltage. However, for ReRAM to become a successful technology, it is necessary to accurately control the stochastic nature of the conductive nanoscale filaments (CNFs) that governs the resistive switching (RS) behavior of the device and limits its long-term stability and reliability. In this paper, we developed a highly scalable nanostructured/textured electrode that is composed of an array of Al nanotips based on an anodic aluminum oxide template. The nanotips improve the RS characteristics by intensifying the electric field at the apex of each nanotip which is demonstrated using numerical simulations. The localized electric field induces the repetitive nucleation/ formation/rupture of the CNFs in a more controlled fashion compared to a flat Al electrode. As a result, the nanotip sample exhibits uniform and reduced forming/reset voltages as low as 4.70 ± 0.98V/1.00 ± 0.19 V, stable endurance, and long-term retention. As a result, we were able to achieve ultralow-power and error-free operation of 100 cells covering a large area, significantly demonstrating improved uniformity and reliability compared to devices made using flat Al electrodes. This universal bottom-up strategy of self-organized nanostructured-electrodes provides a pathway toward large-scale, highly reliable, and RS memory devices. [ABSTRACT FROM AUTHOR]

In this paper, we propose a misaligned double-gate p-i-n impact ionization MOS (MIMOS) with a deliberate misalignment between the top and bottom gates. The presence of a misaligned bottom gate leads to band-to-band-tunneling of electrons at the source-intrinsic region interface and increases the number of carriers for impact ionization. The electric field redistribution provides a longer transport path for the carriers. Therefore, carriers gain higher kinetic energy, and the impact ionization rate is enhanced in the MIMOS. This results in a significantly lower avalanche breakdown voltage compared to conventional single-gate IMOS structure. Using calibrated 2-D simulations, we demonstrate that MIMOS exhibits a steep subthreshold slope (~6 mV/dec) at a significantly low-supply voltage of (${V}_{\text {DS}}= {0.59}$ V), which is ~48% lower than that of the corresponding single-gate IMOS (${V}_{\text {DS}}= {1.15}$ V). [ABSTRACT FROM AUTHOR]

A turn-OFF transient analysis of the superjunction (SJ) insulated-gate bipolar transistor (IGBT) based on an analytical model as a function of structural parameters is presented in this paper. The physical phenomenon dependent on the doping density of the n-/p-pillar of the SJ IGBT could be explained using the analytical model to predict the static and transient characteristics. From this model, tradeoff between turn-OFF loss and ON-state voltage has been obtained, as verified by the TCAD simulations with a good agreement. [ABSTRACT FROM AUTHOR]

In this paper, we have comprehensively studied the performance boosts of both nLDMOS and pLDMOS under the mechanical strain. The electrical properties of LDMOS under the uniaxial tensile and compressive strains along the channel direction are examined thoroughly. We find that the uniaxial tensile strain benefits the nLDMOS, and the uniaxial compressive strain benefits the pLDMOS. Because the mechanical strain affects carriers’ transportation in bulk Si and inverted channel distinctly, the strain effects are strongly correlated with the gate voltage, drain voltage, and devices’ dimensions. It is found that the LDMOS with the longer gate length is more preferred for the strain. The piezoresistance coefficients of both nLDMOS and pLDMOS under the uniaxial strain are evaluated for the first time. It is also shown that the mechanical strain can enhance the drain current without the degradation of the breakdown voltage, which suggests a downshift of the ON-resistance versus breakdown voltage curve. [ABSTRACT FROM AUTHOR]