151. 基于异构可重构计算的 AES 加密系统研究.
- Author
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聂 一, 郑博文, and 柴志雷
- Subjects
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HETEROGENEOUS computing , *DATA encryption , *BIG data , *ALGORITHMS , *GRAPHICS processing units , *HARDWARE , *ADAPTIVE computing systems - Abstract
With the development of big data and the increase of encryption scenarios, it 's difficult to meet the requirements of encryption performance with only software-run encryption methods, and FPGA/ ASIC encryption systems implemented using Verilog/VHDL methods have poor flexibility and difficult maintenance and upgrades problem. In response to the above problems, this paper designed and implemented an AES algorithm encryption system based on heterogeneous reconfigurable computing, including three mainstream modes of AES algorithm ECB, CBC, CTR, each mode realized 128 bit, 192 bit, 256 bit encryption of three key sizes. This paper realized the hardware acceleration of the module based on FPGA, and realized the dynamic switching of different modes and different bit width encryption modules based on the hardware reconfigurable mechanism. By implementing and verifying the system on Intel Stratix 10, the experimental results show that the throughput rates of AES-ECB, AES-CTR and AES-CBC in the system are 116.43 Gbps,60. 34 Gbps, and 4. 32 Gbps, respectively. The ECB mode compared with Intel Xeon E5-2650 V2 CPU and NVIDIA GeForce GTX 1080 GPU achieves 23.18 times and 1.43 times acceleration ratios respectively. Compared with the method just calling the CPU,the overall system has a computational acceleration ratio of 4.72. [ABSTRACT FROM AUTHOR]
- Published
- 2022
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