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This book focuses on how real-time task schedules for reconfigurable hardware-based embedded platforms may be affected due to the vulnerability of hardware and proposes self-aware security strategies to counteract the various threats. The emergence of Industry 4.0 has witnessed the deployment of reconfigurable hardware or field programmable gate arrays (FPGAs) in diverse embedded applications. These are associated with the execution of several real-time tasks arranged in schedules. However, they are associated with several issues. Development of fully and partially reconfigurable task schedules are discussed that eradicates the existing problems. However, such real-time task schedules may be jeopardized due to hardware threats. Analysis of such threats is discussed and self-aware security techniques are proposed that can detect and mitigate such threats at runtime.

Cryptographic solutions using software methods can be used for those security applications where data traffic is not too large and low encryption rate is tolerable. On the other hand, hardware methods offer high-speed solutions making them highly suitable for applications where data traffic is fast and large data is required to be encrypted in real time. VLSI (also known as ASIC), and FPGAs (Field Programmable Gate Arrays) are two alternatives for implementing cryptographic algorithms in hardware. FPGAs offer several benefits for cryptographic algorithm implementations over VLSI as they offer high flexibility. Due to its reconfigurable property, keys can be changed rapidly. Moreover, basic primitives in most cryptographic algorithms can efficiently be implemented in FPGAs. Since the invention of the Data Encryption Standard (DES), some 40 years ago, a considerable amount of cryptographic algorithm implementation literature has been produced both, for software and hardware platforms. Unfortunately, virtually there exists no book explaining how the main cryptographic algorithms can be implemented on reconfigurable hardware devices. This book will cover the study of computational methods, computer arithmetic algorithms, and design improvement techniques needed to implement efficient cryptographic algorithms in FPGA reconfigurable hardware platforms. The concepts and techniques to be reviewed in this book will make special emphasis on the practical aspects of reconfigurable hardware design, explaining the basic mathematics related and giving a comprehensive description of state-of-the-art implementation techniques. Thus, the main goal of this monograph is to show how high-speed cryptographic algorithms implementations can be achieved on reconfigurable hardware devices without posing prohibited high requirements for hardware resources.

To date, the most common form of simulators of computer systems are software-based running on standard computers. One promising approach to improve simulation performance is to apply hardware, specifically reconfigurable hardware in the form of field programmable gate arrays (FPGAs). This manuscript describes various approaches of using FPGAs to accelerate software-implemented simulation of computer systems and selected simulators that incorporate those techniques. More precisely, we describe a simulation architecture taxonomy that incorporates a simulation architecture specifically designed for FPGA accelerated simulation, survey the state-of-the-art in FPGA-accelerated simulation, and describe in detail selected instances of the described techniques. Table of Contents: Preface / Acknowledgments / Introduction / Simulator Background / Accelerating Computer System Simulators with FPGAs / Simulation Virtualization / Categorizing FPGA-based Simulators / Conclusion / Bibliography / Authors'Biographies

This book investigates the susceptibility of intrinsic physically unclonable function (PUF) implementations on reconfigurable hardware to optical semi-invasive attacks from the chip backside. It explores different classes of optical attacks, particularly photonic emission analysis, laser fault injection, and optical contactless probing. By applying these techniques, the book demonstrates that the secrets generated by a PUF can be predicted, manipulated or directly probed without affecting the behavior of the PUF. It subsequently discusses the cost and feasibility of launching such attacks against the very latest hardware technologies in a real scenario. The author discusses why PUFs are not tamper-evident in their current configuration, and therefore, PUFs alone cannot raise the security level of key storage. The author then reviews the potential and already implemented countermeasures, which can remedy PUFs'security-related shortcomings and make them resistant to optical side-channeland optical fault attacks. Lastly, by making selected modifications to the functionality of an existing PUF architecture, the book presents a prototype tamper-evident sensor for detecting optical contactless probing attempts.

To date, the most common form of simulators of computer systems are software-based running on standard computers. One promising approach to improve simulation performance is to apply hardware, specifically reconfigurable hardware in the form of field programmable gate arrays (FPGAs). This manuscript describes various approaches of using FPGAs to accelerate software-implemented simulation of computer systems and selected simulators that incorporate those techniques. More precisely, we describe a simulation architecture taxonomy that incorporates a simulation architecture specifically designed for FPGA accelerated simulation, survey the state-of-the-art in FPGA-accelerated simulation, and describe in detail selected instances of the described techniques. Table of Contents: Preface / Acknowledgments / Introduction / Simulator Background / Accelerating Computer System Simulators with FPGAs / Simulation Virtualization / Categorizing FPGA-based Simulators / Conclusion / Bibliography / Authors'Biographies

Opening with a detailed review of existing techniques for selective encryption, this text then examines algorithms that combine both encryption and compression. The book also presents a selection of specific examples of the design and implementation of secure embedded multimedia systems. Features: reviews the historical developments and latest techniques in multimedia compression and encryption; discusses an approach to reduce the computational cost of multimedia encryption, while preserving the properties of compressed video; introduces a polymorphic wavelet architecture that can make dynamic resource allocation decisions according to the application requirements; proposes a light-weight multimedia encryption strategy based on a modified discrete wavelet transform; describes a reconfigurable hardware implementation of a chaotic filter bank scheme with enhanced security features; presents an encryption scheme for image and video data based on chaotic arithmetic coding.

Dynamically Reconfigurable Systems is the first ever to focus on the emerging field of Dynamically Reconfigurable Computing Systems. While programmable logic and design-time configurability are well elaborated and covered by various texts, this book presents a unique overview over the state of the art and recent results for dynamic and run-time reconfigurable computing systems. Reconfigurable hardware is not only of utmost importance for large manufacturers and vendors of microelectronic devices and systems, but also a very attractive technology for smaller and medium-sized companies. Hence, Dynamically Reconfigurable Systems also addresses researchers and engineers actively working in the field and provides them with information on the newest developments and trends in dynamic and run-time reconfigurable systems.

A one-of-a-kind survey of the field of Reconfigurable Computing Gives a comprehensive introduction to a discipline that offers a 10X-100X acceleration of algorithms over microprocessors Discusses the impact of reconfigurable hardware on a wide range of applications: signal and image processing, network security, bioinformatics, and supercomputing Includes the history of the field as well as recent advances Includes an extensive bibliography of primary sources

This book explores the essential facets of security threats arising from the globalized IC supply chain. Contemporary semiconductor companies navigate a globalized IC supply chain, exposing them to various threats such as Intellectual Property (IP) piracy, reverse engineering, overproduction, and malicious logic insertion. Several obfuscation techniques, including split manufacturing, design camouflaging, and Logic Locking (LL), have been proposed to counter these threats. This book describes a new security method for the silicon industry, the Tunable Design Obfuscation Technique, which uses a reconfigurability feature in the chip to make it harder to understand and protect it from rogue elements.

This book is a compilation of scientific articles written by recognized researchers participating in the Fourth Conference on the Study of Complex Systems and their Applications (EDIESCA 2023), held in Monterrey, Mexico. EDIESCA arose from the need for academic and research groups that carry out this scientific research to disseminate their results internationally. The study and characterization of systems with non-linear and/or chaotic behavior has been of great interest to researchers around the world, for which many important results have been obtained with various applications. The dynamic study of chaotic oscillators of different models, such as Rössler, Lorenz, and Chua, has generated important advances in the understanding of chemical reactions, meteorological behavior, design of electronic devices, and other applications. Topics at the event included applications for communications systems by masking techniques, financial behavior, networks analysis, nonlinear lasers, numerical modeling, electronic design, and other interesting topics in the area of complex systems. Additionally, there are results on numerical simulation and electronic designs to generate complex dynamic behaviors.

This book provides a single-source reference to the state-of-the-art in emerging computer systems. The authors address the technological contributions and developments at various hardware levels of new systems that compute under novel operational paradigms such as stochastic, probabilistic/inexact, neuromorphic, spintronic, bio-inspired and in-memory computing. Coverage includes the entire stack, i.e., from circuit, architecture, up to system level. This book includes tutorials, reviews and surveys of current theoretical/experimental results, design methodologies and a range of applications.

This book provides a look into the future of hardware and microelectronics security, with an emphasis on potential directions in security-aware design, security verification and validation, building trusted execution environments, and physical assurance. The book emphasizes some critical questions that must be answered in the domain of hardware and microelectronics security in the next 5-10 years: (i) The notion of security must be migrated from IP-level to system-level; (ii) What would be the future of IP and IC protection against emerging threats; (iii) How security solutions could be migrated/expanded from SoC-level to SiP-level; (iv) the advances in power side-channel analysis with emphasis on post-quantum cryptography algorithms; (v) how to enable digital twin for secure semiconductor lifecycle management; and (vi) how physical assurance will look like with considerations of emerging technologies. The main aim of this book is to serve as a comprehensive and concise roadmap for new learners and educators navigating the evolving research directions in the domain of hardware and microelectronic securities. Overall, throughout 11 chapters, the book provides numerous frameworks, countermeasures, security evaluations, and roadmaps for the future of hardware security.

This is the first book that sums up test-related modeling of digital circuits and systems by a new structural-decision-diagrams model. The model represents structural and functional information jointly and opens a new area of research.The book introduces and discusses applications of two types of structural decision diagrams (DDs): low-level, structurally synthesized binary DDs (SSBDDs) and high-level DDs (HLDDs) that enable diagnostic modeling of complex digital circuits and systems.Topics and features:Provides the definition, properties and techniques for synthesis, compression and optimization of SSBDDs and HLDDsProvides numerous working examples that illustrate the key points of the textDescribes applications of SSBDDs and HLDDs for various electronic design automation (EDA) tasks, such as logic-level fault modeling and simulation, multi-valued simulation, timing-critical path identification, and test generationDiscusses the advantages of the proposed model to traditional binary decision diagrams and other traditional design representationsCombines SSBDDs with HLDDs for multi-level representation of digital systems for enabling hierarchical and cross-level solving of complex test-related tasksThis unique book is aimed at researchers working in the fields of computer science and computer engineering, focusing on test, diagnosis and dependability of digital systems. It can also serve as a reference for graduate- and advanced undergraduate-level computer engineering and electronics courses.Three authors are affiliated with the Dept. of Computer Systems at the Tallinn University of Technology, Estonia: Raimund Ubar is a retired Professor, Jaan Raik and Maksim Jenihhin are tenured Professors. Artur Jutman, PhD, is a researcher at the same university and the CEO of Testonica Lab Ltd., Estonia.

The book focuses on a very important area of Smart Grids - cyber security. It deals in particular with the tools and techniques for cyber security analysis of the Smart Grid control systems. This includes the standards and guidelines, detailed vulnerability assessment framework, attack detection strategies, and attack mitigation methods. The book is divided into three parts. The smart grid cyber-physical system is discussed in the first part. The second part introduces the attacks in the grid system and a vulnerability assessment framework followed by a tool that can be used to analyze the grid control systems using existing cyber security standards. In the third part, different forms of attack detection methods are discussed along with Python-based implementations for the same. The book also discusses attack mitigation methods with implementation. Detailed illustrations and tables are provided in each section. The book also includes case studies based on standard test systems thushelping students to implement the discussed methods. The case studies are based on MATLAB and Python implementations thus catering to a wide range of audiences. Outputs and screenshots of the tools and programs are included so students can compare their results and improve upon the discussed methods. The book will be useful to a wide variety of audiences such as students and researchers in Smart Grids, power system operators, and device manufacturers.

This book explores the complete system perspective, underlying theories, modeling, and applications of cyber-physical systems (CPS). Considering the interest of researchers and academicians, the editors present this book in a multidimensional perspective covering CPS at breadth. It covers topics ranging from discussion of rudiments of the system and efficient management to recent research challenges and issues. This book is divided into four sections discussing the fundamentals of CPS, engineering-based solutions, its applications, and advanced research challenges. The contents highlight the concept map of CPS including the latest technological interventions, issues, challenges, and the integration of CPS with IoT and big data analytics, modeling solutions, distributed management, efficient energy management, cyber-physical systems research, and education with applications in industrial, agriculture, and medical domains. This book is of immense interest to those in academia and industry.

This handbook presents the key topics in the area of computer architecture covering from the basic to the most advanced topics, including software and hardware design methodologies. It will provide readers with the most comprehensive updated reference information covering applications in single core processors, multicore processors, application-specific processors, reconfigurable architectures, emerging computing architectures, processor design and programming flows, test and verification. This information benefits the readers as a full and quick technical reference with a high-level review of computer architecture technology, detailed technical descriptions and the latest practical applications.

This book covers the foundations of hardware/software codesign, on-chip communication, debugging, and verification, for heterogenous SoCs. Its primary objective is to empower designers in making informed decisions, guiding them to strike the perfect balance between flexibility and performance for their SoC designs. Readers will benefit from a detailed exploration of the essential elements of the hardware and software codesign framework, accompanied by a discussion of the driving motivations behind this approach. The author also provides an in-depth review of various hardware design architectures, shedding light on different design possibilities. Furthermore, the book presents key concepts concerning hardware and software communication, unraveling the intricate interactions within an SoC. This book provides a holistic introduction to the methodologies underpinning SoC design and verification, making it an indispensable companion for both novice and experienced designers navigating the ever-evolving landscape of hardware/software codesign.

Written by two experts of the domain, this book presents the most recent advances in computer arithmetic hardware, with a focus on application-specific arithmetic beyond the classic operators and the standard precisions. It targets silicon designers who have to do better with less in the post-Moore era, and FPGA developers who want to exploit the full possibilities of reconfigurable computing platforms.

This book deals with formal and practical approaches for early fast modeling and verification of complex digital processor hardware and software using SystemC-based virtual prototypes. As a special focus, modeling approaches of instruction-level behavior of System-on-Chips and the connected off-chip digital devices are addressed. Featured verification approaches are based on symbolic execution of simulated hardware devices or on classical discrete execution of the whole system with dynamic data flow tracking. The approaches are accompanied by Case-Studies that develop and build on top of an open-source RISC-V SoC simulation.In Particular, this book:

This book provides a thorough overview of cutting-edge research on electronics applications relevant to industry, the environment, and society at large. It covers a broad spectrum of application domains, from automotive to space and from health to security, while devoting special attention to the use of embedded devices and sensors for imaging, communication, and control. The book is based on the 2023 ApplePies Conference, held in Genoa, Italy, in September 2023, which brought together researchers and stakeholders to consider the most significant current trends in the field of applied electronics and to debate visions for the future. Areas addressed by the conference included information communication technology; biotechnology and biomedical imaging; space; secure, clean, and efficient energy; the environment; and smart, green, and integrated transport. As electronics technology continues to develop apace, constantly meeting previously unthinkable targets, further attention needs tobe directed toward the electronics applications and the development of systems that facilitate human activities. This book, written by industrial and academic professionals, represents a valuable contribution in this endeavor.

The book is designed to serve as a textbook for courses offered to undergraduate and graduate students enrolled in electrical, electronics, and communication engineering. The objective of this book is to help the readers to understand the concepts of digital system design as well as to motivate the students to pursue research in this field. Verilog Hardware Description Language (HDL) is preferred in this book to realize digital architectures. Concepts of Verilog HDL are discussed in a separate chapter and many Verilog codes are given in this book for better understanding. Concepts of system Verilog to realize digital hardware are also discussed in a separate chapter. The book covers basic topics of digital logic design like binary number systems, combinational circuit design, sequential circuit design, and finite state machine (FSM) design. The book also covers some advanced topics on digital arithmetic like design of high-speed adders, multipliers, dividers, square root circuits, and CORDIC block. The readers can learn about FPGA and ASIC implementation steps and issues that arise at the time of implementation. One chapter of the book is dedicated to study the low-power design techniques and another to discuss the concepts of static time analysis (STA) of a digital system. Design and implementation of many digital systems are discussed in detail in a separate chapter. In the last chapter, basics of some advanced FPGA design techniques like partial re-configuration and system on chip (SoC) implementation are discussed. These designs can help the readers to design their architecture. This book can be very helpful to both undergraduate and postgraduate students and researchers.

This is the first book dedicated to hands-on hardware security training. It includes a number of modules to demonstrate attacks on hardware devices and to assess the efficacy of the countermeasure techniques. This book aims to provide a holistic hands-on training to upper-level undergraduate engineering students, graduate students, security researchers, practitioners, and industry professionals, including design engineers, security engineers, system architects, and chief security officers. All the hands-on experiments presented in this book can be implemented on readily available Field Programmable Gate Array (FPGA) development boards, making it easy for academic and industry professionals to replicate the modules at low cost. This book enables readers to gain experiences on side-channel attacks, fault-injection attacks, optical probing attack, PUF, TRNGs, odometer, hardware Trojan insertion and detection, logic locking insertion and assessment, and more.

This book provides a thorough overview of cutting-edge research on electronics applications relevant to industry, the environment, and society at large. It covers a broad spectrum of application domains, from automotive to space and from health to security, while devoting special attention to the use of embedded devices and sensors for imaging, communication and control. The book is based on the 2022 ApplePies Conference, held in Genoa, Italy in September 2022, which brought together researchers and stakeholders to consider the most significant current trends in the field of applied electronics and to debate visions for the future. Areas addressed by the conference included information communication technology; biotechnology and biomedical imaging; space; secure, clean and efficient energy; the environment; and smart, green and integrated transport. As electronics technology continues to develop apace, constantly meeting previously unthinkable targets, further attention needs to bedirected toward the electronics applications and the development of systems that facilitate human activities. This book, written by industrial and academic professionals, represents a valuable contribution in this endeavor.

This book includes high-quality research papers presented at the Fourth International Conference on Communication, Computing and Electronics Systems (ICCCES 2022), held at the PPG Institute of Technology, Coimbatore, India, on September 15–16, 2022. The book focuses mainly on the research trends in cloud computing, mobile computing, artificial intelligence and advanced electronics systems. The topics covered are automation, VLSI, embedded systems, optical communication, RF communication, microwave engineering, artificial intelligence, deep learning, pattern recognition, communication networks, Internet of things, cyber-physical systems and healthcare informatics.

This book provides an overview of current hardware security primitives, their design considerations, and applications. The authors provide a comprehensive introduction to a broad spectrum (digital and analog) of hardware security primitives and their applications for securing modern devices. Readers will be enabled to understand the various methods for exploiting intrinsic manufacturing and temporal variations in silicon devices to create strong security primitives and solutions. This book will benefit SoC designers and researchers in designing secure, reliable, and trustworthy hardware.Provides guidance and security engineers for protecting their hardware designs;Covers a variety digital and analog hardware security primitives and applications for securing modern devices;Helps readers understand PUF, TRNGs, silicon odometer, and cryptographic hardware design for system security.

Written by hundreds experts who have made contributions to both enterprise and academics research, these excellent reference books provide all necessary knowledge of the whole industrial chain of integrated circuits, and cover topics related to the technology evolution trends, fabrication, applications, new materials, equipment, economy, investment, and industrial developments of integrated circuits. Especially, the coverage is broad in scope and deep enough for all kind of readers being interested in integrated circuit industry. Remarkable data collection, update marketing evaluation, enough working knowledge of integrated circuit fabrication, clear and accessible category of integrated circuit products, and good equipment insight explanation, etc. can make general readers build up a clear overview about the whole integrated circuit industry. This encyclopedia is designed as a reference book for scientists and engineers actively involved in integrated circuit research and development field. In addition, this book provides enough guide lines and knowledges to benefit enterprisers being interested in integrated circuit industry.

This book explores new methods, architectures, tools, and algorithms for Artificial Intelligence Hardware Accelerators. The authors have structured the material to simplify readers'journey toward understanding the aspects of designing hardware accelerators, complex AI algorithms, and their computational requirements, along with the multifaceted applications. Coverage focuses broadly on the hardware aspects of training, inference, mobile devices, and autonomous vehicles (AVs) based AI accelerators

This book includes high-quality papers presented at Second International Conference on Computational Electronics for Wireless Communications (ICCWC 2022), held at National Institute of Technology, Surathkal, Karnataka, India, during June 9 – 10, 2022. The book presents original research work of academics and industry professionals to exchange their knowledge of the state-of-the-art research and development in computational electronics with an emphasis on wireless communications. The topics covered in the book are radio frequency and microwave, signal processing, microelectronics, and wireless networks.

Dieses Buch beschreibt eine neue, grobkörnige rekonfigurierbare Architektur (CGRA), genannt Blocks, und stellt sie in den Kontext von Computerarchitekturen und insbesondere von anderen CGRAs. Das Buch beginnt mit einer ausführlichen Bewertung historischer und bestehender CGRAs und deren Stärken und Schwächen. Dies führt auch zu einem besseren Verständnis und einer neuen Definition dessen, was CGRAs von anderen Architekturansätzen unterscheidet. Die Autoren stellen Blocks als einzigartig vor, da es über separate programmierbare Steuer- und Datenpfade verfügt, so dass leichtgewichtige Befehlsdekodiereinheiten über eine statisch konfigurierte Verbindung beliebig mit einer oder mehreren Funktionseinheiten (FUs) verbunden werden können. In der Diskussion wird erläutert, wie Architekturen modelliert werden können, was zu einem Flächen- und Energiemodell für Blöcke führt. Die Genauigkeit dieses Modells wird anhand vollständig implementierter Architekturen bewertet, wobei sich zeigt, dass die Fehlerspanne sehr akzeptabel ist, obwohl es um drei Größenordnungen schneller ist als die Synthese. Das Buch schließt mit einer Fallstudie zu einem echten System-on-Chip, einschließlich einer RISC-Architektur, der Blocks CGRA und Peripheriegeräten.

This book is an edited collection that explores the fundamental concepts of real-time simulation/hardware-in-the-loop testing using ‘Typhoon HIL'for complex electrical systems. Typhoon HIL has recently emerged as a powerful tool in the rapidly growing field of ultra-high-fidelity controller-hardware-in-the-loop (C-HIL) simulations for power electronics, microgrids, and distribution networks. The book integrates the coverage of underlying theory and acclaimed methodological approaches and high-value applications of real-time simulation and hardware-in-the-loop testing—all from the perspectives of eminent researchers around the globe utilizing Typhoon HIL. This book serves as a valuable resource for engineers, academicians, researchers, experienced professionals, and research scholars engaged in /becoming familiarized with the real-time simulation of complex electrical systems using Typhoon HIL with a specific focus on hardware-in-the-loop testing.

Quality Electronic Design (QED)'s landscape spans a vast region where territories of many participating disciplines and technologies overlap. This book explores the latest trends in several key topics related to quality electronic design, with emphasis on Hardware Security, Cybersecurity, Machine Learning, and application of Artificial Intelligence (AI). The book includes topics in nonvolatile memories (NVM), Internet of Things (IoT), FPGA, and Neural Networks.

This book addresses security of FPGA-accelerated cloud computing environments. It presents a comprehensive review of the state-of-the-art in security threats as well as defenses. The book further presents design principles to help in the evaluation and designs of cloud-based FPGA deployments which are secure from information leaks and potential attacks.

This book demonstrates the breadth and depth of IP protection through logic locking, considering both attacker/adversary and defender/designer perspectives. The authors draw a semi-chronological picture of the evolution of logic locking during the last decade, gathering and describing all the DO's and DON'Ts in this approach. They describe simple-to-follow scenarios and guide readers to navigate/identify threat models and design/evaluation flow for further studies. Readers will gain a comprehensive understanding of all fundamentals of logic locking.

This book is the second volume of a two-volume book set which introduces software-defined chips. In this book, the programming model of the software-defined chips is analyzed by tracing the coevolution of modern general-purpose processors and programming models. The enhancement in hardware security and reliability of the software-defined chips are described from the perspective of dynamic and partial reconfiguration. The challenges and prospective trends of software-defined chips are also discussed. Current applications in the fields of artificial intelligence, cryptography, 5G communications, etc., are presented in detail. Potential applications in the future, including post-quantum cryptography, evolutionary computing, etc., are also discussed. This book is suitable for scientists and researchers in the areas of electrical and electronic engineering and computer science. Postgraduate students, practitioners and professionals in related areas are also potentially interested inthe topic of this book.

Performance evaluation is at the foundation of computer architecture research and development. Contemporary microprocessors are so complex that architects cannot design systems based on intuition and simple models only. Adequate performance evaluation methods are absolutely crucial to steer the research and development process in the right direction. However, rigorous performance evaluation is non-trivial as there are multiple aspects to performance evaluation, such as picking workloads, selecting an appropriate modeling or simulation approach, running the model and interpreting the results using meaningful metrics. Each of these aspects is equally important and a performance evaluation method that lacks rigor in any of these crucial aspects may lead to inaccurate performance data and may drive research and development in a wrong direction. The goal of this book is to present an overview of the current state-of-the-art in computer architecture performance evaluation, with a special emphasis on methods for exploring processor architectures. The book focuses on fundamental concepts and ideas for obtaining accurate performance data. The book covers various topics in performance evaluation, ranging from performance metrics, to workload selection, to various modeling approaches including mechanistic and empirical modeling. And because simulation is by far the most prevalent modeling technique, more than half the book's content is devoted to simulation. The book provides an overview of the simulation techniques in the computer designer's toolbox, followed by various simulation acceleration techniques including sampled simulation, statistical simulation, parallel simulation and hardware-accelerated simulation. Table of Contents: Introduction / Performance Metrics / Workload Design / Analytical Performance Modeling / Simulation / Sampled Simulation / Statistical Simulation / Parallel Simulation and Hardware Acceleration / Concluding Remarks

This book introduces the concept of approximate computing for software and hardware designs and its impact on the reliability of embedded systems. It presents approximate computing methods and proposes approximate fault tolerance techniques applied to programmable hardware and embedded software to provide reliability at low computational costs. The book also presents fault tolerance techniques based on approximate computing, thus presenting how approximate computing can be applied to safety-critical systems.

This is the first book of a two-volume book set which introduces software defined chips. In this book, it introduces the conceptual evolution of software defined chips from the development of integrated circuits and computing architectures. Technical principles, characteristics and key issues of software defined chips are systematically analyzed. The hardware architecture design methods are described involving architecture design primitives, hardware design spaces and agile design methods. From the perspective of the compilation system, the complete process from high-level language to configuration contexts is introduced in detail. This book is suitable for scientists and researchers in the areas of electrical and electronic engineering and computer science. Postgraduate students, practitioners and professionals in related areas are also potentially interested in the topic of this book.

This book features selected high-quality papers from the Second International Conference on Innovation in Electrical Power Engineering, Communication, and Computing Technology (IEPCCT 2021), held at Siksha'O'Anusandhan (Deemed to be University), Bhubaneswar, India, on 24–26 September 2021. Presenting innovations in power, communication, and computing, it covers topics such as mini, micro, smart and future power grids; power system economics; energy storage systems; intelligent control; power converters; improving power quality; signal processing; sensors and actuators; image/video processing; high-performance data mining algorithms; advances in deep learning; and optimization methods.

This book gathers the proceedings of the Third International Conference on Computational Advancement in Communication Circuits and Systems (ICCACCS 2020), organized virtually by Narula Institute of Technology, Kolkata, India. The book presents peer-reviewed papers that highlight new theoretical and experimental findings in the fields of electronics and communication engineering, including interdisciplinary areas like advanced computing, pattern recognition and analysis, and signal and image processing. The respective papers cover a broad range of principles, techniques, and applications in microwave devices, communication and networking, signal and image processing, computations and mathematics, and control.

Machine learning is a potential solution to resolve bottleneck issues in VLSI via optimizing tasks in the design process. This book aims to provide the latest machine-learning–based methods, algorithms, architectures, and frameworks designed for VLSI design. The focus is on digital, analog, and mixed-signal design techniques, device modeling, physical design, hardware implementation, testability, reconfigurable design, synthesis and verification, and related areas. Chapters include case studies as well as novel research ideas in the given field. Overall, the book provides practical implementations of VLSI design, IC design, and hardware realization using machine learning techniques.Features: Provides the details of state-of-the-art machine learning methods used in VLSI design Discusses hardware implementation and device modeling pertaining to machine learning algorithms Explores machine learning for various VLSI architectures and reconfigurable computing Illustrates the latest techniques for device size and feature optimization Highlights the latest case studies and reviews of the methods used for hardware implementation This book is aimed at researchers, professionals, and graduate students in VLSI, machine learning, electrical and electronic engineering, computer engineering, and hardware systems.

This book provides a thorough overview of the state-of-the-art field-programmable gate array (FPGA)-based robotic computing accelerator designs and summarizes their adopted optimized techniques. This book consists of ten chapters, delving into the details of how FPGAs have been utilized in robotic perception, localization, planning, and multi-robot collaboration tasks. In addition to individual robotic tasks, this book provides detailed descriptions of how FPGAs have been used in robotic products, including commercial autonomous vehicles and space exploration robots.

This book states that a space-induced crisis is recognized as the cause of trouble that Moore's Law is currently facing. The contemporary practice of this empirical law can be considered as happening within a space-dominant paradigm. An alternative of exploiting potential in the dimension of time is identified as an emerging paradigm in microelectronics. The new practice is termed a time-oriented paradigm. It is justified as the turn of Moore's Law from space to time. The resultant Time-Moore strategy is envisioned as the next-generation enabler for continuing Moore's Law's pursuit of everhigher information processing power and efficiency. It also serves as the perpetuation of the spirit that Moore's law is nothing but a collective storied history of innovations. In the first part of this book, by following Thomas Kuhn's seminal work around the concepts of paradigm and scientific revolution, the argument for the Time-Moore strategy (Time-Moore: to use time more) and the paradigm shift from space to time is carried out heavily through philosophical persuasion rather than technical proof due to the difficult challenge of change-of-mindset. The second part of the book provides solid technical materials for supporting this transition from the old paradigm to the new one. In short, the goal of this book is to reevaluate the contemporary practice of microelectronics, identify the cause of the current crisis, advocate a change-of-mindset to circumvent the crisis, and ultimately point out a new route for advancing. After achieving so many unprecedented accomplishments through several decades of relentless endeavor, it's time for the big ship of Moore's Law (i.e., the art of microelectronic system design) to make a turn.

This book uses digital radios as a challenging design example, generalized to bridge a typical gap between designers who work on algorithms and those who work to implement those algorithms on silicon. The author shows how such a complex system can be moved from high-level characterization to a form that is ready for hardware implementation. Along the way, readers learn a lot about how algorithm designers can benefit from knowing the hardware they target and how hardware designers can benefit from a familiarity with the algorithm. The book shows how a high-level description of an algorithm can be migrated to a fixed-point block diagram with a well-defined cycle accurate architecture and a fully documented controller. This can significantly reduce the length of the hardware design cycle and can improve its outcomes. Ultimately, the book presents an explicit design flow that bridges the gap between algorithm design and hardware design.Provides a guide to basebandradio design for Wi-Fi and cellular systems, from an implementation-focused, perspective;Explains how arithmetic is moved to hardware and what the cost of each operation is in terms of delay, area and power;Enables strategic architectural decisions based on the algorithm, available processing units and design requirements.

The book is designed to serve as a textbook for courses offered to graduate and undergraduate students enrolled in electronics and electrical engineering and computer science. This book attempts to bridge the gap between electronics and computer science students, providing complementary knowledge that is essential for designing an embedded system. The book covers key concepts tailored for embedded system design in one place. The topics covered in this book are models and architectures, Executable Specific Languages – SystemC, Unified Modeling Language, real-time systems, real-time operating systems, networked embedded systems, Embedded Processor architectures, and platforms that are secured and energy-efficient. A major segment of embedded systems needs hard real-time requirements. This textbook includes real-time concepts including algorithms and real-time operating system standards like POSIX threads. Embedded systems are mostly distributed and networked for deterministic responses. The book covers how to design networked embedded systems with appropriate protocols for real-time requirements. Each chapter contains 2-3 solved case studies and 10 real-world problems as exercises to provide detailed coverage and essential pedagogical tools that make this an ideal textbook for students enrolled in electrical and electronics engineering and computer science programs.

This book explores the technological developments at various levels of abstraction, of the new paradigm of approximate computing. The authors describe in a single-source the state-of-the-art, covering the entire spectrum of research activities in approximate computing, bridging device, circuit, architecture, and system levels. Content includes tutorials, reviews and surveys of current theoretical/experimental results, design methodologies and applications developed in approximate computing for a wide scope of readership and specialists.Serves as a single-source reference to state-of-the-art of approximate computing;Covers broad range of topics, from circuits to applications;Includes contributions by leading researchers, from academia and industry.

The book covers a range of topics dealing with emerging computing technologies which are being developed in response to challenges faced due to scaling CMOS technologies. It provides a sneak peek into the capabilities unleashed by these technologies across the complete system stack, with contributions by experts discussing device technology, circuit, architecture and design automation flows. Presenting a gradual progression of the individual sub-domains and the open research and adoption challenges, this book will be of interest to industry and academic researchers, technocrats and policymakers.Chapters'Innovative Memory Architectures Using Functionality Enhanced Devices'and'Intelligent Edge Biomedical Sensors in the Internet of Things (IoT) Era'are available open access under a Creative Commons Attribution 4.0 International License via link.springer.com.

This book comprises select proceedings of the International Conference on Advances in Electrical and Computer Technologies 2021 (ICAECT 2021). The papers presented in this book are peer-reviewed and cover the latest research in electrical, electronics, communication, and computer engineering. Topics covered include smart grids, soft computing techniques in power systems, smart energy management systems, power electronics, feedback control systems, biomedical engineering, geographic information systems, grid computing, data mining, image and signal processing, video processing, computer vision, pattern recognition, cloud computing, pervasive computing, intelligent systems, artificial intelligence, neural network and fuzzy logic, broadband communication, mobile and optical communication, network security, VLSI, embedded systems, optical networks, and wireless communication. The book is useful for students and researchers working in the different overlapping areas of electrical, electronics, and communication engineering.

This book describes deep learning systems: the algorithms, compilers, and processor components to efficiently train and deploy deep learning models for commercial applications. The exponential growth in computational power is slowing at a time when the amount of compute consumed by state-of-the-art deep learning (DL) workloads is rapidly growing. Model size, serving latency, and power constraints are a significant challenge in the deployment of DL models for many applications. Therefore, it is imperative to codesign algorithms, compilers, and hardware to accelerate advances in this field with holistic system-level and algorithm solutions that improve performance, power, and efficiency. Advancing DL systems generally involves three types of engineers: (1) data scientists that utilize and develop DL algorithms in partnership with domain experts, such as medical, economic, or climate scientists; (2) hardware designers that develop specialized hardware to accelerate the components in the DL models; and (3) performance and compiler engineers that optimize software to run more efficiently on a given hardware. Hardware engineers should be aware of the characteristics and components of production and academic models likely to be adopted by industry to guide design decisions impacting future hardware. Data scientists should be aware of deployment platform constraints when designing models. Performance engineers should support optimizations across diverse models, libraries, and hardware targets. The purpose of this book is to provide a solid understanding of (1) the design, training, and applications of DL algorithms in industry; (2) the compiler techniques to map deep learning code to hardware targets; and (3) the critical hardware features that accelerate DL systems. This book aims to facilitate co-innovation for the advancement of DL systems. It is written for engineers working in one or more of these areas who seek to understand the entire system stack in order to better collaborate with engineers working in other parts of the system stack. The book details advancements and adoption of DL models in industry, explains the training and deployment process, describes the essential hardware architectural features needed for today's and future models, and details advances in DL compilers to efficiently execute algorithms across various hardware targets. Unique in this book is the holistic exposition of the entire DL system stack, the emphasis on commercial applications, and the practical techniques to design models and accelerate their performance. The author is fortunate to work with hardware, software, data scientist, and research teams across many high-technology companies with hyperscale data centers. These companies employ many of the examples and methods provided throughout the book.

This book covers technologies, applications, tools, languages, procedures, advantages, and disadvantages of reconfigurable supercomputing using Field Programmable Gate Arrays (FPGAs). The target audience is the community of users of High Performance Computers (HPC) who may benefit from porting their applications into a reconfigurable environment. As such, this book is intended to guide the HPC user through the many algorithmic considerations, hardware alternatives, usability issues, programming languages, and design tools that need to be understood before embarking on the creation of reconfigurable parallel codes. We hope to show that FPGA acceleration, based on the exploitation of the data parallelism, pipelining and concurrency remains promising in view of the diminishing improvements in traditional processor and system design. Table of Contents: FPGA Technology / Reconfigurable Supercomputing / Algorithmic Considerations / FPGA Programming Languages / Case Study: Sorting / Alternative Technologies and Concluding Remarks

This book reports on the design, fabrication and characterization of a set of flexible electronic components, including on-foil sensors, organic thin-film transistors and ultra-thin chips. The core of the work is on showing how to combine high-performance integrated circuits with large-area electronic components on a single polymeric foil, to realize smart electronic systems for different applications, such as temperature, humidity and mechanical stress sensors. The book offers an extensive introduction to Hybrid System-in-Foil technology (HySiF), and related on-chip/on-foil passive and active components. It presents six case studies designed to highlight key HySiF challenges, together with the methodology to address those challenges. Last but not least, it describes the development of a reconfigurable, energy-efficient Analog-to-Digital Converter for HySiF. All in all, this book provides readers with extensive information on the state of the art in the design and characterization of integrated circuits and hybrid electronic systems on flexible polymeric substrates. By describing significant advances in organic thin-film transistor technology, this work is expected to pave the way to future developments in the area of energy-efficient smart sensors and integrated circuits.