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th Welcome to the proceedings of PATMOS 2007, the 17 in a series of international workshops. PATMOS 2007 was organized by Chalmers University of Technology with IEEE Sweden Chapter of the Solid-State Circuit Society technical - sponsorship and IEEE CEDA sponsorship. Over the years, PATMOS has evolved into an important European event, where - searchers from both industry and academia discuss and investigate the emerging ch- lenges in future and contemporary applications, design methodologies, and tools - quired for the development of the upcoming generations of integrated circuits and systems. The technical program of PATMOS 2007 consisted of state-of-the-art te- nical contributions, three invited talks and an industrial session on design challenges in real-life projects. The technical program focused on timing, performance and power consumption, as well as architectural aspects with particular emphasis on m- eling, design, characterization, analysis and optimization in the nanometer era. The Technical Program Committee, with the assistance of additional expert - viewers, selected the 55 papers presented at PATMOS. The papers were organized into 9 technical sessions and 3 poster sessions. As is always the case with the PATMOS workshops, full papers were required, and several reviews were received per manuscript.

This textbook introduces readers to the fundamental hardware used in modern computers. The only pre-requisite is algebra, so it can be taken by college freshman or sophomore students or even used in Advanced Placement courses in high school. This book presents both the classical approach to digital system design (i.e., pen and paper) in addition to the modern hardware description language (HDL) design approach (computer-based). This textbook enables readers to design digital systems using the modern HDL approach while ensuring they have a solid foundation of knowledge of the underlying hardware and theory of their designs. This book is designed to match the way the material is actually taught in the classroom. Topics are presented in a manner which builds foundational knowledge before moving onto advanced topics. The author has designed the content with learning goals and assessment at its core. Each section addresses a specific learning outcome that the learner should be able to “do” after its completion. The concept checks and exercise problems provide a rich set of assessment tools to measure learner performance on each outcome. This book can be used for either a sequence of two courses consisting of an introduction to logic circuits (Chapters 1-7) followed by logic design (Chapters 8-14) or a single, accelerated course that uses the early chapters as reference material.

This textbook for courses in Digital Systems Design introduces students to the fundamental hardware used in modern computers. Coverage includes both the classical approach to digital system design (i.e., pen and paper) in addition to the modern hardware description language (HDL) design approach (computer-based). Using this textbook enables readers to design digital systems using the modern HDL approach, but they have a broad foundation of knowledge of the underlying hardware and theory of their designs. This book is designed to match the way the material is actually taught in the classroom. Topics are presented in a manner which builds foundational knowledge before moving onto advanced topics. The author has designed the presentation with learning Goals and assessment at its core. Each section addresses a specific learning outcome that the student should be able to “do” after its completion. The concept checks and exercise problems provide a rich set of assessment tools to measure student performance on each outcome.

This textbook introduces readers to the fundamental hardware used in modern computers. The only pre-requisite is algebra, so it can be taken by college freshman or sophomore students or even used in Advanced Placement courses in high school. This book presents both the classical approach to digital system design (i.e., pen and paper) in addition to the modern hardware description language (HDL) design approach (computer-based). This textbook enables readers to design digital systems using the modern HDL approach while ensuring they have a solid foundation of knowledge of the underlying hardware and theory of their designs. This book is designed to match the way the material is actually taught in the classroom. Topics are presented in a manner which builds foundational knowledge before moving onto advanced topics. The author has designed the content with learning goals and assessment at its core. Each section addresses a specific learning outcome that the learner should be able to “do” after its completion. The concept checks and exercise problems provide a rich set of assessment tools to measure learner performance on each outcome. This book can be used for either a sequence of two courses consisting of an introduction to logic circuits (Chapters 1-7) followed by logic design (Chapters 8-13) or a single, accelerated course that uses the early chapters as reference material.

This is a textbook for graduate and final-year-undergraduate computer-science and electrical-engineering students interested in the hardware and software aspects of embedded and cyberphysical systems design. It is comprehensive and self-contained, covering everything from the basics to case-study implementation.Emphasis is placed on the physical nature of the problem domain and of the devices used. The reader is assumed to be familiar on a theoretical level with mathematical tools like ordinary differential equation and Fourier transforms. In this book these tools will be put to practical use.Engineering Embedded Systems begins by addressing basic material on signals and systems, before introducing to electronics. Treatment of digital electronics accentuating synchronous circuits and including high-speed effects proceeds to micro-controllers, digital signal processors and programmable logic. Peripheral units and decentralized networks are given due weight. The properties of analog circuits and devices like filters and data converters are covered to the extent desirable by a systems architect. The handling of individual elements concludes with power supplies including regulators and converters.The final section of the text is composed of four case studies:• electric-drive control, permanent magnet synchronous motors in particular;• lock-in amplification with measurement circuits for weight and torque, and moisture;• design of a simple continuous wave radar that can be operated to measure speed and distance; and• design of a Fourier transform infrared spectrometer for process applications.End-of-chapter exercises will assist the student to assimilate the tutorial material and these are supplemented by a downloadable solutions manual for instructors. The “pen-and-paper” problems are further augmented with laboratory activities. In addition to its student market, Engineering Embedded Systems will assist industrial practitioners working in systems architecture and the design of electronic measurement systems to keep up to date with developments in embedded systems through self study.

The International Workshop on Power and Timing Modeling, Optimization, and Simulation PATMOS 2002, was the 12th in a series of international workshops 1 previously held in several places in Europe. PATMOS has over the years evolved into a well-established and outstanding series of open European events on power and timing aspects of integrated circuit design. The increased interest, espe- ally in low-power design, has added further momentum to the interest in this workshop. Despite its growth, the workshop can still be considered as a very - cused conference, featuring high-level scienti?c presentations together with open discussions in a free and easy environment. This year, the workshop has been opened to both regular papers and poster presentations. The increasing number of worldwide high-quality submissions is a measure of the global interest of the international scienti?c community in the topics covered by PATMOS. The objective of this workshop is to provide a forum to discuss and inves- gate the emerging problems in the design methodologies and CAD-tools for the new generation of IC technologies. A major emphasis of the technical program is on speed and low-power aspects with particular regard to modeling, char- terization, design, and architectures. The technical program of PATMOS 2002 included nine sessions dedicated to most important and current topics on power and timing modeling, optimization, and simulation. The three invited talks try to give a global overview of the issues in low-power and/or high-performance circuit design.

This book focuses on summarizing recent research trends for new beyond-CMOS and beyond-silicon devices, circuits, and architectures for computing. It reports the recent achievements in this field from leading research trends around the globe, specifically focusing on nanoscale beyond silicon materials and devices, functional nanomaterials, nanoscale devices, beyond-CMOS devices materials, and their opportunities and challenges. The book is devoted to the fast-evolving field of modern material science and nanoelectronics, particularly to the physics and technology of functional nanomaterials and devices.

This textbook introduces basic embedded machine learning methods by exploring practical applications on STM32 development boards. Covering traditional and neural network-based machine learning methods implemented on microcontrollers, the text is designed for use in courses on microcontrollers, microprocessor systems, and embedded systems. Following the learning by doing approach, the book will enable students to grasp embedded machine learning concepts through real-world examples that will provide them with the design and implementation skills needed for a competitive job market. By utilizing a programming environment that enables students to reach and modify low-level microcontroller properties, the material allows for more control of the developed system. Students will be guided in implementing machine learning methods to be deployed and tested on microcontrollers throughout the book, with the theory behind the implemented methods also emphasized. Sample codes and course slides are available for readers and instructors, and a solutions manual is available to instructors. The book will also be an ideal reference for practicing engineers and electronics hobbyists.

Neural network (NN) algorithms are driving the rapid development of modern artificial intelligence (AI). The energy-efficient NN processor has become an urgent requirement for the practical NN applications on widespread low-power AI devices. To address this challenge, this dissertation investigates pure-digital and digital computing-in-memory (digital-CIM) solutions and carries out four major studies. For pure-digital NN processors, this book analyses the insufficient data reuse in conventional architectures and proposes a kernel-optimized NN processor. This dissertation adopts a structural frequency-domain compression algorithm, named CirCNN. The fabricated processor shows 8.1x/4.2x area/energy efficiency compared to the state-of-the-art NN processor. For digital-CIM NN processors, this dissertation combines the flexibility of digital circuits with the high energy efficiency of CIM. The fabricated CIM processor validates the sparsity improvement of the CIM architecture for the first time. This dissertation further designs a processor that considers the weight updating problem on the CIM architecture for the first time. This dissertation demonstrates that the combination of digital and CIM circuits is a promising technical route for an energy-efficient NN processor, which can promote the large-scale application of low-power AI devices.

Written by two experts of the domain, this book presents the most recent advances in computer arithmetic hardware, with a focus on application-specific arithmetic beyond the classic operators and the standard precisions. It targets silicon designers who have to do better with less in the post-Moore era, and FPGA developers who want to exploit the full possibilities of reconfigurable computing platforms.

This textbook introduces basic and advanced embedded machine learning methods by exploring practical applications on Arduino boards. By covering traditional and neural network-based machine learning methods implemented on microcontrollers, the text is designed for use in courses on microcontrollers and embedded machine learning systems. Following the learning-by-doing approach, the book will enable students to grasp embedded machine learning concepts through real-world examples, providing them with the design and implementation skills needed for a competitive job market. By utilizing a programming environment that enables students to reach and modify microcontroller properties easily, the material allows for fast implementation of the developed system. Students are guided in implementing machine learning methods to be deployed and tested on microcontrollers throughout the book, with the theory behind the implemented methods also emphasized. Sample codes and real-world projects are available for readers and instructors. The book will also be an ideal reference for practicing engineers and electronics hobbyists.

This book is a practical reference for using Texas Instruments MSP430 microcontrollers. It provides a series of hands-on laboratory exercises. The labs may be completed in a traditional laboratory setting or at home using the Digilent Analog Discovery 2 Test Instrument. This book can be used as a reference for planning future projects using the MSP430 microcontroller. The authors focus on applications of the main peripheral modules available on the MSP430 microcontroller – CPU clock, Basic Input/Output, Timer, Analog-to-Digital Converter. They also provide examples of how to develop Pulse Width Modulation signals, and how to use Interrupts.

This textbook provides a starter's guide to VHDL. This book can be used in conjunction with a one-semester course in Digital Systems Design or on its own for designers who only need an introduction to the language. This book is designed to provide a bottoms-up approach to learning the VHDL language. This design supports a course in which foundational knowledge is covered before moving into advanced topics. However, this design also supports use as a reference manual. The author has designed the presentation with learning goals and assessment at its core. Each section addresses a specific learning outcome that the student should be able to “do” after its completion. The concept checks and exercise problems provide a rich set of assessment tools to measure student performance on each outcome.

This is an introductory textbook for courses in Synchronous Digital Design that enables students to develop useful intuitions for all of the key concepts of digital design. The author focuses this tutorial on the design flow, which is introduced as an iterative cycle of Analysis, Improvement, Modeling, and Synthesis. All the basic elements of digital design are covered, starting with the CMOS transistor to provide an abstraction upon which everything else is built. The other main foundational concepts introduced are clocked synchronous register-transfer level design, datapath, finite state machines and communication between clock domains.

This book discusses the acceleration of deep reinforcement learning (DRL), which may be the next step in the burst success of artificial intelligence (AI). The authors address acceleration systems which enable DRL on area-limited & battery-limited mobile devices. Methods are described that enable DRL optimization at the algorithm-, architecture-, and circuit-levels of abstraction.

This book describes the state-of-the-art of technology and research on In-Memory Computing Hardware Accelerators for Data-Intensive Applications. The authors discuss how processing-centric computing has become insufficient to meet target requirements and how Memory-centric computing may be better suited for the needs of current applications. This reveals for readers how current and emerging memory technologies are causing a shift in the computing paradigm. The authors do deep-dive discussions on volatile and non-volatile memory technologies, covering their basic memory cell structures, operations, different computational memory designs and the challenges associated with them. Specific case studies and potential applications are provided along with their current status and commercial availability in the market.

This book is an edited collection that explores the fundamental concepts of real-time simulation/hardware-in-the-loop testing using ‘Typhoon HIL'for complex electrical systems. Typhoon HIL has recently emerged as a powerful tool in the rapidly growing field of ultra-high-fidelity controller-hardware-in-the-loop (C-HIL) simulations for power electronics, microgrids, and distribution networks. The book integrates the coverage of underlying theory and acclaimed methodological approaches and high-value applications of real-time simulation and hardware-in-the-loop testing—all from the perspectives of eminent researchers around the globe utilizing Typhoon HIL. This book serves as a valuable resource for engineers, academicians, researchers, experienced professionals, and research scholars engaged in /becoming familiarized with the real-time simulation of complex electrical systems using Typhoon HIL with a specific focus on hardware-in-the-loop testing.

This book provides a state-of-the-art guide to Machine Learning (ML)-based techniques that have been shown to be highly efficient for diagnosis of failures in electronic circuits and systems. The methods discussed can be used for volume diagnosis after manufacturing or for diagnosis of customer returns. Readers will be enabled to deal with huge amount of insightful test data that cannot be exploited otherwise in an efficient, timely manner. After some background on fault diagnosis and machine learning, the authors explain and apply optimized techniques from the ML domain to solve the fault diagnosis problem in the realm of electronic system design and manufacturing. These techniques can be used for failure isolation in logic or analog circuits, board-level fault diagnosis, or even wafer-level failure cluster identification. Evaluation metrics as well as industrial case studies are used to emphasize the usefulness and benefits of using ML-based diagnosis techniques.

This book provides an easy-to-read introduction into quantum computing as well as classical simulation of quantum circuits. The authors showcase the enormous potential that can be unleashed when doing these simulations using decision diagrams—a data structure common in the design automation community but hardly used in quantum computing yet. In fact, the covered algorithms and methods are able to outperform previously proposed solutions on certain use cases and, hence, provide a complementary solution to established approaches. The award-winning methods are implemented and available as open-source under free licenses and can be easily integrated into existing frameworks such as IBM's Qiskit or Atos'QLM.

This textbook demonstrates new paradigms for the interface between CMOS circuits and the biological world. A deep theoretical description of such an interface is defined and discussed, while various real applications are demonstrated by also discussing several analog CMOS circuits. Electrochemical techniques are proposed in detail to learn how to design integrated biosensors. Biological materials are described to provide devices selectivity. Nanoscale materials are discussed to provide device sensitivity. CMOS circuits are analyzed to provide real applications. Extensive examples with solutions are provided, as well as exercises at the end of each chapter. This book introduces students to the state-of-the-art in Bio/CMOS interfaces, describing leading-edge research in CMOS design and VLSI development for applications requiring intimate integration of biological molecules onto the chip. It provides multidisciplinary content ranging from biochemistry to CMOS design in order to address Bio/CMOS interface co-design in biosensing applications.

This book presents various novel architectures for FPGA-optimized accurate and approximate operators, their detailed accuracy and performance analysis, various techniques to model the behavior of approximate operators, and thorough application-level analysis to evaluate the impact of approximations on the final output quality and performance metrics. As multiplication is one of the most commonly used and computationally expensive operations in various error-resilient applications such as digital signal and image processing and machine learning algorithms, this book particularly focuses on this operation. The book starts by elaborating on the various sources of error resilience and opportunities available for approximations on various layers of the computation stack. It then provides a detailed description of the state-of-the-art approximate computing-related works and highlights their limitations.

This textbook for courses in Embedded Systems introduces students to necessary concepts, through a hands-on approach. LEARN BY EXAMPLE – This book is designed to teach the material the way it is learned, through example. Every concept is supported by numerous programming examples that provide the reader with a step-by-step explanation for how and why the computer is doing what it is doing. LEARN BY DOING – This book targets the Texas Instruments MSP430 microcontroller. This platform is a widely popular, low-cost embedded system that is used to illustrate each concept in the book. The book is designed for a reader that is at their computer with an MSP430FR2355 LaunchPadTM Development Kit plugged in so that each example can be coded and run as they learn. LEARN BOTH ASSEMBLY AND C – The book teaches the basic operation of an embedded computer using assembly language so that the computer operation can be explored at a low-level. Once more complicated systems are introduced (i.e., timers, analog-to-digital converters, and serial interfaces), the book moves into the C programming language. Moving to C allows the learner to abstract the operation of the lower-level hardware and focus on understanding how to “make things work”. BASED ON SOUND PEDAGOGY - This book is designed with learning outcomes and assessment at its core. Each section addresses a specific learning outcome that the student should be able to “do” after its completion. The concept checks and exercise problems provide a rich set of assessment tools to measure student performance on each outcome.

This textbook provides a starter's guide to Verilog, to be used in conjunction with a one-semester course in Digital Systems Design, or on its own for readers who only need an introduction to the language. This book is designed to match the way the material is actually taught in the classroom. Topics are presented in a manner which builds foundational knowledge before moving onto advanced topics. The author has designed the presentation with learning goals and assessment at its core. Each section addresses a specific learning outcome that the student should be able to “do” after its completion. The concept checks and exercise problems provide a rich set of assessment tools to measure student performance on each outcome.Written the way the material is taught, enabling a bottom-up approach to learning which culminates with a high-level of learning, with a solid foundation;Emphasizes examples from which students can learn: contains a solved example for nearly every section in the book;Includes more than 200 exercise problems, as well as concept check questions for each section, tied directly to specific learning outcomes.

This book is a single-source solution for anyone who is interested in exploring emerging reconfigurable nanotechnology at the circuit level. It lays down a solid foundation for circuits based on this technology having considered both manual as well as automated design flows. The authors discuss the entire design flow, consisting of both logic and physical synthesis for reconfigurable nanotechnology-based circuits. The authors describe how transistor reconfigurable properties can be exploited at the logic level to have a more efficient circuit design flow, as compared to conventional design flows suited for CMOS. Further, the book provides insights into hardware security features that can be intrinsically developed using the runtime reconfigurable features of this nanotechnology.

Dieses Buch beschreibt eine neue, grobkörnige rekonfigurierbare Architektur (CGRA), genannt Blocks, und stellt sie in den Kontext von Computerarchitekturen und insbesondere von anderen CGRAs. Das Buch beginnt mit einer ausführlichen Bewertung historischer und bestehender CGRAs und deren Stärken und Schwächen. Dies führt auch zu einem besseren Verständnis und einer neuen Definition dessen, was CGRAs von anderen Architekturansätzen unterscheidet. Die Autoren stellen Blocks als einzigartig vor, da es über separate programmierbare Steuer- und Datenpfade verfügt, so dass leichtgewichtige Befehlsdekodiereinheiten über eine statisch konfigurierte Verbindung beliebig mit einer oder mehreren Funktionseinheiten (FUs) verbunden werden können. In der Diskussion wird erläutert, wie Architekturen modelliert werden können, was zu einem Flächen- und Energiemodell für Blöcke führt. Die Genauigkeit dieses Modells wird anhand vollständig implementierter Architekturen bewertet, wobei sich zeigt, dass die Fehlerspanne sehr akzeptabel ist, obwohl es um drei Größenordnungen schneller ist als die Synthese. Das Buch schließt mit einer Fallstudie zu einem echten System-on-Chip, einschließlich einer RISC-Architektur, der Blocks CGRA und Peripheriegeräten.

This book is the second volume of a two-volume book set which introduces software-defined chips. In this book, the programming model of the software-defined chips is analyzed by tracing the coevolution of modern general-purpose processors and programming models. The enhancement in hardware security and reliability of the software-defined chips are described from the perspective of dynamic and partial reconfiguration. The challenges and prospective trends of software-defined chips are also discussed. Current applications in the fields of artificial intelligence, cryptography, 5G communications, etc., are presented in detail. Potential applications in the future, including post-quantum cryptography, evolutionary computing, etc., are also discussed. This book is suitable for scientists and researchers in the areas of electrical and electronic engineering and computer science. Postgraduate students, practitioners and professionals in related areas are also potentially interested inthe topic of this book.

This book provides readers with an overview of the fundamental definitions and features of Multiple-Valued Logic (MVL). The authors include a brief discussion of the historical development of MVL technologies, while the main goal of the book is to present a comprehensive review of different technologies that are being explored to implement multiple-valued or beyond-binary memory circuits and systems. The discussion includes the basic features, prospects, and challenges of each technology, while highlighting the significant works done on different branches of MVL memory architecture, such as sequential circuits, random access memory, Flash memory, etc.

This is the first book of a two-volume book set which introduces software defined chips. In this book, it introduces the conceptual evolution of software defined chips from the development of integrated circuits and computing architectures. Technical principles, characteristics and key issues of software defined chips are systematically analyzed. The hardware architecture design methods are described involving architecture design primitives, hardware design spaces and agile design methods. From the perspective of the compilation system, the complete process from high-level language to configuration contexts is introduced in detail. This book is suitable for scientists and researchers in the areas of electrical and electronic engineering and computer science. Postgraduate students, practitioners and professionals in related areas are also potentially interested in the topic of this book.

This book describes the first comprehensive approach to the optimization of interconnect architectures in 3D systems on chips (SoCs), specially addressing the challenges and opportunities arising from heterogeneous integration. Readers learn about the physical implications of using heterogeneous 3D technologies for SoC integration, while also learning to maximize the 3D-technology gains, through a physical-effect-aware architecture design. The book provides a deep theoretical background covering all abstraction-levels needed to research and architect tomorrow's 3D-integrated circuits, an extensive set of optimization methods (for power, performance, area, and yield), as well as an open-source optimization and simulation framework for fast exploration of novel designs.

Today, computer-system optimization, at both the hardware and software levels, must consider the details of the memory system in its analysis; failing to do so yields systems that are increasingly inefficient as those systems become more complex. This lecture seeks to introduce the reader to the most important details of the memory system; it targets both computer scientists and computer engineers in industry and in academia. Roughly speaking, computer scientists are the users of the memory system and computer engineers are the designers of the memory system. Both can benefit tremendously from a basic understanding of how the memory system really works: the computer scientist will be better equipped to create algorithms that perform well and the computer engineer will be better equipped to design systems that approach the optimal, given the resource limitations. Currently, there is consensus among architecture researchers that the memory system is'the bottleneck,'and this consensus has held for over a decade. Somewhat inexplicably, most of the research in the field is still directed toward improving the CPU to better tolerate a slow memory system, as opposed to addressing the weaknesses of the memory system directly. This lecture should get the bulk of the computer science and computer engineering population up the steep part of the learning curve. Not every CS/CE researcher/developer needs to do work in the memory system, but, just as a carpenter can do his job more efficiently if he knows a little of architecture, and an architect can do his job more efficiently if he knows a little of carpentry, giving the CS/CE worlds better intuition about the memory system should help them build better systems, both software and hardware. Table of Contents: Primers / It Must Be Modeled Accurately /...\ and It Will Change Soon

Die Übersetzung der sechsten Auflage des Standardwerks zur Rechnerorganisation »Computer Organization and Design« bietet dem Leser neue Beispiele, Übungsaufgaben sowie Stoff über mobiles Computing und die Cloud. Die Inhalte wurden verbessert und mit der Vorstellung neuer Prozessoren aktualisiert. Das sechste Kapitel wurde um einen Abschnitt über domänenspezifische Architekturen erweitert, ein neuer Ansatz, der am Beispiel von Googles Tensor Processing Unit (TPU) ausführlich dargestellt wird. Abschnitte zur Beschleunigung demonstrieren am Beispiel der Matrixmultiplikation verschiedene Optimierungsschritte, die wichtige Architekturprinzipien ausnutzen. Sieben bedeutende Konzepte der Computerarchitektur werden eingeführt und diskutiert: Performanz durch Parallelität, Performanz durch Pipelining, Performanz durch Vorhersagen, Speicherhierarchien, Abstraktion zur Vereinfachung des Designs, das Beschleunigen des häufigen Falls und Zuverlässigkeit durch Redundanz. Wie bei den vorherigen Auflagen ist ein MIPS-Prozessor der Kern, der verwendet wird, um die Grundlagen von Hardwaretechnologien, Assemblersprache, Computerarithmetik, Pipelining, Speicherhierarchien und der Ein-/Ausgabe zu vermitteln.Z

This is the first book to focus on the problem of ensuring the correctness of floating-point hardware designs through mathematical methods. Formal Verification of Floating-Point Hardware Design, Second Edition advances a verification methodology based on a unified theory of register-transfer logic and floating-point arithmetic that has been developed and applied to the formal verification of commercial floating-point units over the course of more than two decades, during which the author was employed by several major microprocessor design companies. The theory is extended to the analysis of several algorithms and optimization techniques that are commonly used in commercial implementations of elementary arithmetic operations. As a basis for the formal verification of such implementations, high-level specifications of the basic arithmetic instructions of several major industry-standard floating-point architectures are presented, including all details pertaining to the handling of exceptional conditions. The methodology is illustrated in the comprehensive verification of a variety of state-of-the-art commercial floating-point designs developed by Arm Holdings. This revised edition reflects the evolving microarchitectures and increasing sophistication of Arm processors, and the variation in the design goals of execution speed, hardware area requirements, and power consumption. Many new results have been added to Parts I—III (Register-Transfer Logic, Floating-Point Arithmetic, and Implementation of Elementary Operations), extending the theory and describing new techniques. These were derived as required in the verification of the new RTL designs described in Part V.

This book is intended for designers with experience in traditional (clocked) circuit design, seeking information about asynchronous circuit design, in order to determine if it would be advantageous to adopt asynchronous methodologies in their next design project. The author introduces a generic approach for implementing a deterministic completion detection scheme for asynchronous bundled data circuits that incorporates a data-dependent computational process, taking advantage of the average-case delay. The author validates the architecture using a barrel shifter, as shifting is the basic operation required by all the processors. The generic architecture proposed in this book for a deterministic completion detection scheme for bundled data circuits will facilitate researchers in considering the asynchronous design style for developing digital circuits.

This book provides a thorough overview of the state-of-the-art field-programmable gate array (FPGA)-based robotic computing accelerator designs and summarizes their adopted optimized techniques. This book consists of ten chapters, delving into the details of how FPGAs have been utilized in robotic perception, localization, planning, and multi-robot collaboration tasks. In addition to individual robotic tasks, this book provides detailed descriptions of how FPGAs have been used in robotic products, including commercial autonomous vehicles and space exploration robots.

Most emerging applications in imaging and machine learning must perform immense amounts of computation while holding to strict limits on energy and power. To meet these goals, architects are building increasingly specialized compute engines tailored for these specific tasks. The resulting computer systems are heterogeneous, containing multiple processing cores with wildly different execution models. Unfortunately, the cost of producing this specialized hardware—and the software to control it—is astronomical. Moreover, the task of porting algorithms to these heterogeneous machines typically requires that the algorithm be partitioned across the machine and rewritten for each specific architecture, which is time consuming and prone to error. Over the last several years, the authors have approached this problem using domain-specific languages (DSLs): high-level programming languages customized for specific domains, such as database manipulation, machine learning, or image processing. By giving up generality, these languages are able to provide high-level abstractions to the developer while producing high-performance output. The purpose of this book is to spur the adoption and the creation of domain-specific languages, especially for the task of creating hardware designs. In the first chapter, a short historical journey explains the forces driving computer architecture today. Chapter 2 describes the various methods for producing designs for accelerators, outlining the push for more abstraction and the tools that enable designers to work at a higher conceptual level. From there, Chapter 3 provides a brief introduction to image processing algorithms and hardware design patterns for implementing them. Chapters 4 and 5 describe and compare Darkroom and Halide, two domain-specific languages created for image processing that produce high-performance designs for both FPGAs and CPUs from the same source code, enabling rapid design cycles and quick porting of algorithms. The final section describes how the DSL approach also simplifies the problem of interfacing between application code and the accelerator by generating the driver stack in addition to the accelerator configuration. This book should serve as a useful introduction to domain-specialized computing for computer architecture students and as a primer on domain-specific languages and image processing hardware for those with more experience in the field.

Originally developed to support video games, graphics processor units (GPUs) are now increasingly used for general-purpose (non-graphics) applications ranging from machine learning to mining of cryptographic currencies. GPUs can achieve improved performance and efficiency versus central processing units (CPUs) by dedicating a larger fraction of hardware resources to computation. In addition, their general-purpose programmability makes contemporary GPUs appealing to software developers in comparison to domain-specific accelerators. This book provides an introduction to those interested in studying the architecture of GPUs that support general-purpose computing. It collects together information currently only found among a wide range of disparate sources. The authors led development of the GPGPU-Sim simulator widely used in academic research on GPU architectures. The first chapter of this book describes the basic hardware structure of GPUs and provides a brief overview of their history. Chapter 2 provides a summary of GPU programming models relevant to the rest of the book. Chapter 3 explores the architecture of GPU compute cores. Chapter 4 explores the architecture of the GPU memory system. After describing the architecture of existing systems, Chapters 3 and 4 provide an overview of related research. Chapter 5 summarizes cross-cutting research impacting both the compute core and memory system. This book should provide a valuable resource for those wishing to understand the architecture of graphics processor units (GPUs) used for acceleration of general-purpose applications and to those who want to obtain an introduction to the rapidly growing body of research exploring how to improve the architecture of these GPUs.

This book introduces readers to emerging persistent memory (PM) technologies that promise the performance of dynamic random-access memory (DRAM) with the durability of traditional storage media, such as hard disks and solid-state drives (SSDs). Persistent memories (PMs), such as Intel's Optane DC persistent memories, are commercially available today. Unlike traditional storage devices, PMs can be accessed over a byte-addressable load-store interface with access latency that is comparable to DRAM. Unfortunately, existing hardware and software systems are ill-equipped to fully avail the potential of these byte-addressable memory technologies as they have been designed to access traditional storage media over a block-based interface. Several mechanisms have been explored in the research literature over the past decade to design hardware and software systems that provide high-performance access to PMs.Because PMs are durable, they can retain data across failures, such as power failures and program crashes. Upon a failure, recovery mechanisms may inspect PM data, reconstruct state and resume program execution. Correct recovery of data requires that operations to the PM are properly ordered during normal program execution. Memory persistency models define the order in which memory operations are performed at the PM. Much like memory consistency models, memory persistency models may be relaxed to improve application performance. Several proposals have emerged recently to design memory persistency models for hardware and software systems and for high-level programming languages. These proposals differ in several key aspects; they relax PM ordering constraints, introduce varying programmability burden, and introduce differing granularity of failure atomicity for PM operations.This primer provides a detailed overview of the various classes of the memory persistency models, their implementations in hardware, programming languages and software systems proposed in the recent research literature, and the PM ordering techniques employed by modern processors.

With growing interest in computer security and the protection of the code and data which execute on commodity computers, the amount of hardware security features in today's processors has increased significantly over the recent years. No longer of just academic interest, security features inside processors have been embraced by industry as well, with a number of commercial secure processor architectures available today. This book aims to give readers insights into the principles behind the design of academic and commercial secure processor architectures. Secure processor architecture research is concerned with exploring and designing hardware features inside computer processors, features which can help protect confidentiality and integrity of the code and data executing on the processor. Unlike traditional processor architecture research that focuses on performance, efficiency, and energy as the first-order design objectives, secure processor architecture design has security as the first-order design objective (while still keeping the others as important design aspects that need to be considered). This book aims to present the different challenges of secure processor architecture design to graduate students interested in research on architecture and hardware security and computer architects working in industry interested in adding security features to their designs. It aims to educate readers about how the different challenges have been solved in the past and what are the best practices, i.e., the principles, for design of new secure processor architectures. Based on the careful review of past work by many computer architects and security researchers, readers also will come to know the five basic principles needed for secure processor architecture design. The book also presents existing research challenges and potential new research directions. Finally, this book presents numerous design suggestions, as well as discusses pitfalls and fallacies that designers should avoid.

This book summarizes the landscape of cache replacement policies for CPU data caches. The emphasis is on algorithmic issues, so the authors start by defining a taxonomy that places previous policies into two broad categories, which they refer to as coarse-grained and fine-grained policies. Each of these categories is then divided into three subcategories that describe different approaches to solving the cache replacement problem, along with summaries of significant work in each category. Richer factors, including solutions that optimize for metrics beyond cache miss rates, that are tailored to multi-core settings, that consider interactions with prefetchers, and that consider new memory technologies, are then explored. The book concludes by discussing trends and challenges for future work. This book, which assumes that readers will have a basic understanding of computer architecture and caches, will be useful to academics and practitioners across the field.

This book provides a structured treatment of the key principles and techniques for enabling efficient processing of deep neural networks (DNNs). DNNs are currently widely used for many artificial intelligence (AI) applications, including computer vision, speech recognition, and robotics. While DNNs deliver state-of-the-art accuracy on many AI tasks, it comes at the cost of high computational complexity. Therefore, techniques that enable efficient processing of deep neural networks to improve key metrics—such as energy-efficiency, throughput, and latency—without sacrificing accuracy or increasing hardware costs are critical to enabling the wide deployment of DNNs in AI systems. The book includes background on DNN processing; a description and taxonomy of hardware architectural approaches for designing DNN accelerators; key metrics for evaluating and comparing different designs; features of DNN processing that are amenable to hardware/algorithm co-design to improve energy efficiency and throughput; and opportunities for applying new technologies. Readers will find a structured introduction to the field as well as formalization and organization of key concepts from contemporary work that provide insights that may spark new ideas.

The advent of multicore processors has renewed interest in the idea of incorporating transactions into the programming model used to write parallel programs. This approach, known as transactional memory, offers an alternative, and hopefully better, way to coordinate concurrent threads. The ACI (atomicity, consistency, isolation) properties of transactions provide a foundation to ensure that concurrent reads and writes of shared data do not produce inconsistent or incorrect results. At a higher level, a computation wrapped in a transaction executes atomically - either it completes successfully and commits its result in its entirety or it aborts. In addition, isolation ensures the transaction produces the same result as if no other transactions were executing concurrently. Although transactions are not a parallel programming panacea, they shift much of the burden of synchronizing and coordinating parallel computations from a programmer to a compiler, to a language runtime system, or to hardware. The challenge for the system implementers is to build an efficient transactional memory infrastructure. This book presents an overview of the state of the art in the design and implementation of transactional memory systems, as of early spring 2010. Table of Contents: Introduction / Basic Transactions / Building on Basic Transactions / Software Transactional Memory / Hardware-Supported Transactional Memory / Conclusions

Machine learning, and specifically deep learning, has been hugely disruptive in many fields of computer science. The success of deep learning techniques in solving notoriously difficult classification and regression problems has resulted in their rapid adoption in solving real-world problems. The emergence of deep learning is widely attributed to a virtuous cycle whereby fundamental advancements in training deeper models were enabled by the availability of massive datasets and high-performance computer hardware. This text serves as a primer for computer architects in a new and rapidly evolving field. We review how machine learning has evolved since its inception in the 1960s and track the key developments leading up to the emergence of the powerful deep learning techniques that emerged in the last decade. Next we review representative workloads, including the most commonly used datasets and seminal networks across a variety of domains. In addition to discussing the workloads themselves, we also detail the most popular deep learning tools and show how aspiring practitioners can use the tools with the workloads to characterize and optimize DNNs. The remainder of the book is dedicated to the design and optimization of hardware and architectures for machine learning. As high-performance hardware was so instrumental in the success of machine learning becoming a practical solution, this chapter recounts a variety of optimizations proposed recently to further improve future designs. Finally, we present a review of recent research published in the area as well as a taxonomy to help readers understand how various contributions fall in context.

This book describes deep learning systems: the algorithms, compilers, and processor components to efficiently train and deploy deep learning models for commercial applications. The exponential growth in computational power is slowing at a time when the amount of compute consumed by state-of-the-art deep learning (DL) workloads is rapidly growing. Model size, serving latency, and power constraints are a significant challenge in the deployment of DL models for many applications. Therefore, it is imperative to codesign algorithms, compilers, and hardware to accelerate advances in this field with holistic system-level and algorithm solutions that improve performance, power, and efficiency. Advancing DL systems generally involves three types of engineers: (1) data scientists that utilize and develop DL algorithms in partnership with domain experts, such as medical, economic, or climate scientists; (2) hardware designers that develop specialized hardware to accelerate the components in the DL models; and (3) performance and compiler engineers that optimize software to run more efficiently on a given hardware. Hardware engineers should be aware of the characteristics and components of production and academic models likely to be adopted by industry to guide design decisions impacting future hardware. Data scientists should be aware of deployment platform constraints when designing models. Performance engineers should support optimizations across diverse models, libraries, and hardware targets. The purpose of this book is to provide a solid understanding of (1) the design, training, and applications of DL algorithms in industry; (2) the compiler techniques to map deep learning code to hardware targets; and (3) the critical hardware features that accelerate DL systems. This book aims to facilitate co-innovation for the advancement of DL systems. It is written for engineers working in one or more of these areas who seek to understand the entire system stack in order to better collaborate with engineers working in other parts of the system stack. The book details advancements and adoption of DL models in industry, explains the training and deployment process, describes the essential hardware architectural features needed for today's and future models, and details advances in DL compilers to efficiently execute algorithms across various hardware targets. Unique in this book is the holistic exposition of the entire DL system stack, the emphasis on commercial applications, and the practical techniques to design models and accelerate their performance. The author is fortunate to work with hardware, software, data scientist, and research teams across many high-technology companies with hyperscale data centers. These companies employ many of the examples and methods provided throughout the book.

This book provides a structured introduction of the key concepts and techniques that enable in-/near-memory computing. For decades, processing-in-memory or near-memory computing has been attracting growing interest due to its potential to break the memory wall. Near-memory computing moves compute logic near the memory, and thereby reduces data movement. Recent work has also shown that certain memories can morph themselves into compute units by exploiting the physical properties of the memory cells, enabling in-situ computing in the memory array. While in- and near-memory computing can circumvent overheads related to data movement, it comes at the cost of restricted flexibility of data representation and computation, design challenges of compute capable memories, and difficulty in system and software integration. Therefore, wide deployment of in-/near-memory computing cannot be accomplished without techniques that enable efficient mapping of data-intensive applications to such devices, without sacrificing accuracy or increasing hardware costs excessively. This book describes various memory substrates amenable to in- and near-memory computing, architectural approaches for designing efficient and reliable computing devices, and opportunities for in-/near-memory acceleration of different classes of applications.

Hardware acceleration in the form of customized datapath and control circuitry tuned to specific applications has gained popularity for its promise to utilize transistors more efficiently. Historically, the computer architecture community has focused on general-purpose processors, and extensive research infrastructure has been developed to support research efforts in this domain. Envisioning future computing systems with a diverse set of general-purpose cores and accelerators, computer architects must add accelerator-related research infrastructures to their toolboxes to explore future heterogeneous systems. This book serves as a primer for the field, as an overview of the vast literature on accelerator architectures and their design flows, and as a resource guidebook for researchers working in related areas.

This book describes warehouse-scale computers (WSCs), the computing platforms that power cloud computing and all the great web services we use every day. It discusses how these new systems treat the datacenter itself as one massive computer designed at warehouse scale, with hardware and software working in concert to deliver good levels of internet service performance. The book details the architecture of WSCs and covers the main factors influencing their design, operation, and cost structure, and the characteristics of their software base. Each chapter contains multiple real-world examples, including detailed case studies and previously unpublished details of the infrastructure used to power Google's online services. Targeted at the architects and programmers of today's WSCs, this book provides a great foundation for those looking to innovate in this fascinating and important area, but the material will also be broadly interesting to those who just want to understand the infrastructure powering the internet. The third edition reflects four years of advancements since the previous edition and nearly doubles the number of pictures and figures. New topics range from additional workloads like video streaming, machine learning, and public cloud to specialized silicon accelerators, storage and network building blocks, and a revised discussion of data center power and cooling, and uptime. Further discussions of emerging trends and opportunities ensure that this revised edition will remain an essential resource for educators and professionals working on the next generation of WSCs.

General-purpose graphics processing units (GPGPU) have emerged as an important class of shared memory parallel processing architectures, with widespread deployment in every computer class from high-end supercomputers to embedded mobile platforms. Relative to more traditional multicore systems of today, GPGPUs have distinctly higher degrees of hardware multithreading (hundreds of hardware thread contexts vs. tens), a return to wide vector units (several tens vs. 1-10), memory architectures that deliver higher peak memory bandwidth (hundreds of gigabytes per second vs. tens), and smaller caches/scratchpad memories (less than 1 megabyte vs. 1-10 megabytes). In this book, we provide a high-level overview of current GPGPU architectures and programming models. We review the principles that are used in previous shared memory parallel platforms, focusing on recent results in both the theory and practice of parallel algorithms, and suggest a connection to GPGPU platforms. We aim to provide hints to architects about understanding algorithm aspect to GPGPU. We also provide detailed performance analysis and guide optimizations from high-level algorithms to low-level instruction level optimizations. As a case study, we use n-body particle simulations known as the fast multipole method (FMM) as an example. We also briefly survey the state-of-the-art in GPU performance analysis tools and techniques. Table of Contents: GPU Design, Programming, and Trends / Performance Principles / From Principles to Practice: Analysis and Tuning / Using Detailed Performance Analysis to Guide Optimization

To date, the most common form of simulators of computer systems are software-based running on standard computers. One promising approach to improve simulation performance is to apply hardware, specifically reconfigurable hardware in the form of field programmable gate arrays (FPGAs). This manuscript describes various approaches of using FPGAs to accelerate software-implemented simulation of computer systems and selected simulators that incorporate those techniques. More precisely, we describe a simulation architecture taxonomy that incorporates a simulation architecture specifically designed for FPGA accelerated simulation, survey the state-of-the-art in FPGA-accelerated simulation, and describe in detail selected instances of the described techniques. Table of Contents: Preface / Acknowledgments / Introduction / Simulator Background / Accelerating Computer System Simulators with FPGAs / Simulation Virtualization / Categorizing FPGA-based Simulators / Conclusion / Bibliography / Authors'Biographies

In this book we give an overview of modeling techniques used to describe computer systems to mathematical optimization tools. We give a brief introduction to various classes of mathematical optimization frameworks with special focus on mixed integer linear programming which provides a good balance between solver time and expressiveness. We present four detailed case studies -- instruction set customization, data center resource management, spatial architecture scheduling, and resource allocation in tiled architectures -- showing how MILP can be used and quantifying by how much it outperforms traditional design exploration techniques. This book should help a skilled systems designer to learn techniques for using MILP in their problems, and the skilled optimization expert to understand the types of computer systems problems that MILP can be applied to.

Shrinking feature size and diminishing supply voltage are making circuits sensitive to supply voltage fluctuations within the microprocessor, caused by normal workload activity changes. If left unattended, voltage fluctuations can lead to timing violations or even transistor lifetime issues that degrade processor robustness. Mechanisms that learn to tolerate, avoid, and eliminate voltage fluctuations based on program and microarchitectural events can help steer the processor clear of danger, thus enabling tighter voltage margins that improve performance or lower power consumption. We describe the problem of voltage variation and the factors that influence this variation during processor design and operation. We also describe a variety of runtime hardware and software mitigation techniques that either tolerate, avoid, and/or eliminate voltage violations. We hope processor architects will find the information useful since tolerance, avoidance, and elimination are generalizable constructs that can serve as a basis for addressing other reliability challenges as well. Table of Contents: Introduction / Modeling Voltage Variation / Understanding the Characteristics of Voltage Variation / Traditional Solutions and Emerging Solution Forecast / Allowing and Tolerating Voltage Emergencies / Predicting and Avoiding Voltage Emergencies / Eliminiating Recurring Voltage Emergencies / Future Directions on Resiliency