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Current control in inverter-driven machine systems is the inner most component of the hierarchy of control loops. If the control of current in the machine is not fast and accurate then it is difficult, if not impossible, to build a high-performance drive system. Unfortunately, the implementation of current control in power electronic systems is not ideal. Practical effects can have a significant influence on its performance. This paper examines one of these effects, dead time, and considers the influence it has on the performance of predictive current controllers (PCCs). The paper presents analysis that shows that a PCC implicitly compensates for voltage loss due to dead time. Also, a modified PCC is introduced that reduces the zero-current-clamp problem caused by dead time. Simulation and experimental results are presented to verify the analysis and confirm the performance of the new algorithm. [ABSTRACT FROM AUTHOR]

International standard bodies have specified an instrument capable of detecting and assessing the severity of lighting flicker, which is called a flickermeter. However, a deficiency with regard to flicker caused by high-frequency interharmonics has been reported in the recent literature. In this paper, another deficiency of the International Electrotechnical Commission (IEC) flickermeter with regard to low-frequency interharmonics, whose frequencies are below the difference between the fundamental frequency and the cutoff frequency of a bandpass filter of the IEC standard flickermeter, will be discussed and illustrated based on analysis and numerical experiments. A new approach based on down-up sampling in the discrete-time sample domain is also proposed to address the flicker-detection problem associated with interharmonics. We demonstrate the efficacy of the proposed method by a comparison with the current flickermeter standard in the presence of interharmonics. [ABSTRACT FROM AUTHOR]

Most electrostatic discharge (ESD) generators are built in accordance with the IEC 61000-4-2 specifications. It is shown, that the voltage induced in a small loop correlates with the failure level observed in an ESD failure test on the systems comprised of fast CMOS devices, while rise time and derivative of the discharge current did not correlate well. The electric parameters of typical ESD generators and ESD generators that have been modified to reflect the current and field parameters of the human metal reference event are compared and the effect on the failure level of fast CMOS electronics is investigated. The consequences of aligning an ESD standard with the suggestions of the first paper, of this two-paper series, are discussed with respect to reproducibility and test severity. [ABSTRACT FROM AUTHOR]

This paper describes a new design approach for a power amplifier (PA) of the highly efficient hybrid envelope elimination and restoration (H-EER) transmitter. Since the PA operates mostly at the average power region of the modulation signal, power-added efficiency (PAE) of the PA at the average drain voltage is very important for the overall transmitter PAE. Accordingly, the PA is designed to have a maximum PAE in that region. The performances of the proposed PA and a conventional PA under H-EER operation are evaluated via ADS and MATLAB simulations using a behavioral large-signal model of a silicon LDMOSFET, which verifies that the proposed PA has significant advantages for the H-EER transmitter in both PAE and output power. A saturated amplifier, inverse class F, has been implemented using a 5-W peak envelope power LDMOSFET for 3GPP forward-link single-carrier wideband code-division multiple-access at 1 GHz with a peak-to-average power ratio of 9.8 dB. An envelope amplifier is built that has an efficiency of above 68% and peak output voltage of 31 V for an interlock experiment. The overall PAE of the transmitter with a conventional PA is 35.5% at an output power of 29.2 dBm. On the other hand, the transmitter with the proposed PA delivers significantly improved performances: PAE increased by 4% and output power by 2.5 dB. The H-EER transmitter has been linearized by the digital feedback predistortion technique. The measured error vector magnitude is reduced to 1.47% from .6.4%. These results clearly show that the proposed architecture is a good candidate for efficient linear transmitters. [ABSTRACT FROM AUTHOR]

In this paper, the stability of self-consistent Monte Carlo (MC) device simulations is revised by developing a model that extends the existing ones by accounting for the effect of a carrier diffusion. Both the linear and the nonlinear Poisson schemes have been considered. The analysis of the linear Poisson scheme reveals that, consistently with (lie available model, the time step between two Poisson solutions must be short compared to a factor proportional to the scattering rate. On the other hand, it has been found that, contrary to the available stability models, the nonlinear Poisson scheme requires long lime steps in order to provide stable simulations. For this reason, the nonlinear scheme is advantageous when considering steady-state simulations. The model predictions have been verified by comparison with MC simulations implementing both schemes. [ABSTRACT FROM AUTHOR]

An international collaboration plans to measure the lifetime of the muon to a precision of 1 part per million [1]. The "MuLan" experiment wilt take place at the Paul Scherrer Institut (PSI) in Northern Switzerland. The MuLan experiment requires a fast beam line kicker, which can turn the beam on and off, to invoke an artificial time structure on the continuous beam which has a 50.6-MHz time microstructure. The kicker needs to run with a standard "on-off time cycle" or in a "Muon on Request" mode. The MuLan kicker consists of two pairs of deflector plates mechanically in series, driven by four modulators. Each modulator consists of two stacks of MOSFETs operating in push-pull mode. The specifications for the kicker demand that the rise and fall times of the deflector plate voltage do not exceed 45 ns. There is a requirement for an adjustable output voltage from 0 V to ± 12.5 kV per deflector plate, a minimum pulse duration of 200 ns, and adjustable repetition rate up to a maximum of 50 kHz, continuous. Short turn-on and turn-off delays are required for the "Muon on Request" mode; the measured propagation delay is 200 ns. The specifications also require that the polarity of the pulses on the plates be selectable, although not on a pulse-by-pulse basis. This paper describes the novel design of the kicker and presents both predictions and measurements. [ABSTRACT FROM AUTHOR]

Mechanical characterization of electronic devices is often quite uneasy; most of the techniques used require a contact with the sample under study. In this paper, we propose an optical noncontact interferometric imaging method to study the thermomechanical behavior of running devices, and In particular, to deduce the corresponding elastic strain energy. This analysis will permit us to localize the zones of fragility of the device. Results obtained on a power MOS transistor to detect the region of maximum elastic strain energy an presented. It is in particular adapted in microelectronics a applications to detect stress accumulation due to dilation coefficient mismatches when assembling microchips. [ABSTRACT FROM AUTHOR]

This paper shows that a reasonably accurate description of propagation loss in small urban cells can be obtained with a simple stochastic model based on the theory of random walks, that accounts for only two parameters: the amount of clutter and the amount of absorption in the environment. Despite the simplifications of the model, the derived analytical solution correctly describes the smooth transition of power attenuation from an inverse square Law with the distance to the transmitter, to an exponential attenuation as this distance is increased-as it is observed in practice. Our analysis suggests using a simple exponential path loss formula as an alternative to the empirical formulas that are often used for prediction. Results are validated by comparison with experimental data collected in a small urban cell. [ABSTRACT FROM AUTHOR]

We present a new method of performing high-resolution path delay testing on designs targeted to field- programmable gate arrays. Our built-in self-test (BIST) architecture uses an on-chip delay line element to set the launch time of each test pattern generator to its optimum point for stressing paths in the routed chip. The rising and falling edges of each test pattern are controllable with high precision, and consequently, our test architecture catches very small timing faults that exist in the path. For example, on Xilinx Virtex-4, we catch defects as small as 78 ps using the IDELAY delay line circuit that is available on that device. Our approach was validated on Virtex-4, and the same method can be applied to any device that supports on-chip delay lines that are adjustable at runtime. Furthermore, our architecture simultaneously tests multiple paths to reduce the overall test time. [ABSTRACT FROM AUTHOR]

In other to save energy, several countries -ecently made laws related to standby power consumption. To wccess this exertion, we should consider not only power -eduction of consumer electronics itself but also efficient ~utomatic control in networked home environment. In this 7aper, we present a design approach and implementation esult of control mechanism for standby power reduction. Proposed mechanism has the Host-Agent based structure and ~ises the IEEE 802.15.4 based ZigBee protocol for ~ommunication and security between Host and Agents. We verified reliability of proposed mechanism and reduction effect of standby power; also, we applied implemented device ~o scenario which is similar to user living pattern. Experimental results demonstrate that in the proposed ~echanism, standby power consumption of Agent which is connected to consumer electronics can be reduced by 203mW. [ABSTRACT FROM AUTHOR]

The effect of magnetic "preconditioning" on the recording performance of perpendicular media is investigated. Furthermore, the dependence of the magnetic write width (MWW) of shielded-pole heads (SPH) on soft-underlayer (SUL) type and thickness (tSUL) and the recording performance of perpendicular media with thin SULs are examined. The MWW dependence on SUL structure is influenced by the pole-to-trailing shield spacing. For a wide-gap (∼80 nm) SPH, thick single-layer, SULs are preferred. For a narrow-gap (∼50 mn) SPH, MWW is less sensitive to the SUL type. For both narrow and wide-gap SPH and for media with an antiferromagnetically-coupled SUL, MWW is reduced for tSUL < 100 nm. Comparable performance is achieved relative to media with tSUL 150 nm. [ABSTRACT FROM AUTHOR]

Electrostatic discharge (ESO) generators are used for testing the robustness of electronics toward ESD. Most generators are built in accordance with the IEC 61000-4-2 specifications. Using only a few parameters, this standard specifies the peak current, the rise lime and the falling edge. Lacking a transient field specification, test results vary depending on which generator is used, even if the currents are quite similar. Such a specification is needed to huprove the test repeatability. As for the current, the specification should be based on a reference human metal ESD event. While keeping the presently set peak current and rise time values, such a reference ESD (5 kV, 850-μm arc length) is identified and specifications for current derivative, fields, and induced voltages are derived. The reference event parameters are compared to typical ESD generators. [ABSTRACT FROM AUTHOR]

A monolithic lateral double diffused MOSFET (LD- MOST) based on the super junction (SJ) concept is proposed to significantly improve the device's on-state and off-state characteristics. The device structure features a split drift region made of two parts: 1) an SJ structure that extends over most of the drift region and 2) a terminating reduced surface field (RESURF) region occupying a portion of the drift region adjacent to the n+ drain. This structure suppresses substrate-assisted depletion effects and ensures complete depletion and near uniform electric field distribution over the entire drift region. In the on-state, the high conductivity of the SJ drift region results in a significant improvement in the specific on-resistance for a given breakdown voltage (BV) and, hence, a reduction in the on-state, switching, and gate-drive losses. In the off-state, the RESURF region, located near the n+ drain, effectively neutralizes the substrate-assisted depletion effects and results in high BV. [ABSTRACT FROM AUTHOR]

The dynamic response of an electronically shuttered charge-coupled device (CCD) imager to nanosecond voltage pulses has been investigated. Measurements show that the shutter can be dynamically opened and closed in nanosecond times. For the shutter opening, simulations indicate that the collection of photo-electrons occurs in times much shorter than that needed to form the steady-state depletion region under the CCD well. In addition, the shutter closing occurs faster than the reconstitution of the p-buried (shutter) layer. Simulations further indicate that electric fields created in the neutral substrate by the shutter clocks enable photogenerated charge collection/rejection on nanosecond time scales despite the fact that the depletion-region formation and collapse take much longer times. [ABSTRACT FROM AUTHOR]