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Chaotic systems contain nonlinear functions that have received much attention. This paper introduces a new four-dimensional chaotic system with multi-winged attractors, containing hyperbolic sinusoidal functions with unique quadratic curves that cause the attractors to change dramatically. When the single parameter is changed, single, double and quadruple wing chaotic attractors will be generated. The dynamical behavior of chaotic systems is analyzed and it is found that the system has coexistent attractors. Based on preparing the error system asymptotically stable at the origin, an adaptive control method is derived to achieve chaotic synchronization with unknown parameters. A new electronic circuit for chaotic systems is designed and implemented in FPGA hardware to illustrate the accuracy and validity of its existence. [ABSTRACT FROM AUTHOR]

With the rapid development of modern information technology represented by the Internet, cloud computing and big data, education and teaching have gradually realized the deep integration of the Internet, which has changed people's way of life, study and work to a certain extent. Intelligence + education provides a new information-based teaching method for the development of education. From the perspective of improving the accuracy of data fusion results, this paper proposes a new multi-source data fusion method based on a set pair analysis connection degree for the situation that multiple sensors with unknown prior knowledge detect the same target feature parameters multiple times. By using the advantages of the set pair analysis feature function, the degree of opposition, the identity and difference between the measurement data are mined to adjust the degree of connection between the data. According to the existing signal-to-noise ratio weighting method in the fusion process, the weight of the measurement data is reasonably allocated to realize the weighted fusion of multi-source data, and the effectiveness and reliability of the algorithm are verified through simulation experiments. Through the summary of the questions, it can be seen that the learners are very satisfied with the mobile piano learning mode based on the intelligent teaching system, and they believe that this learning mode is conducive to the learner's mastery of the basic knowledge of piano, and effectively improves the learners' learning ability. It also improves the individual's self-directed learning ability and academic performance. Through the research, it is concluded that the students' piano mobile learning mode based on the intelligent teaching system is more conducive to the learner's mastery of knowledge, and improves the learning interest and academic performance. [ABSTRACT FROM AUTHOR]

Solar photovoltaic (PV) systems have gained significant attention due to their easy implementation and availability, where proper energy management should be highly concentrated for a successful PV power utilization. In the traditional works, various controlling techniques have been developed for reactive power compensation. But, it lacks with the issues of reduced system performance, increased loss, and high harmonics. Hence, this paper aims to develop a new controlling methodology, named the Synthesis Segmental Multilevel Converter (SSMC) for reactive power compensation in a three-phase grid system. Initially, it extracts the maximum amount of power from the solar PV systems by using an Enhanced Perturb and Observe (EPO) method. Then, the panel separation is performed and the three-phase power input is given to the SSMC converter, where the synchronization and switching pulse generation processes are performed. During synchronization, integrated techniques such as Proportional Integral (PI), Fuzzy Logic Controller (FLC), and Improved Artificial Neural Network (IANN) are utilized to maintain the voltage, magnitude and phase angle in the same level. Consequently, the Inductance Capacitance (LC) filtering technique is applied to reduce the harmonics distortion in the signal. After that, the Park transformation is used to perform the dq0 to abc transformation, which is implemented for reducing the high volume of error. Finally, the error-free signal is fed to the three-phase grid system with reduced harmonics. During experimentation, both the simulation and analytical results have been taken for analyzing the performance of the proposed technique. Moreover, it is compared to the existing algorithms for proving the betterment of the proposed methodology. [ABSTRACT FROM AUTHOR]

Phase Locked Loop (PLL) is an on-chip clock generator for timing-centric electronic systems. Voltage Controlled Oscillator (VCO) is the key element for high-performance PLLs. A detailed qualitative explanation has been given to describe VCO operation. It is shown from simulation results that the variation of small signal transconductance ( g m ) is the main dominant source of frequency and gain ( K VCO ) variation in a VCO. In this work, simulation results for the conventional ring oscillator are presented which demonstrates ≈ 3 times variation in K VCO across Process Voltage Temperature (PVT) corners. Such huge sensitivity to PVT is undesirable for high bandwidth PLL design. To mitigate this sensitivity, a constant-gm bias circuit is proposed in this paper, with a detailed mathematical analysis. A prototype of 4-stage ring oscillator with center frequency of 5 GHz is developed in 65 nm TSMC CMOS technology, and post-layout simulation results are carried out. Results show that maximum K VCO variation of 28% and frequency variation of 17% at a given control voltage. Temperature sensitivity has been decreased from 19.3% to 7% using the proposed biasing technique. Proposed solution consumes 2.4 mW power from 1 V power supply. [ABSTRACT FROM AUTHOR]

A simple circuit based on modified extra-X second-generation current conveyor (MEXCCII), which is capable of realizing the following grounded immittance functions: a lossless capacitor, a lossy capacitor, a lossy inductor and a lossy frequency-dependent negative conductance, is introduced in this paper. The circuit employs one MEXCCII and three passive components. The use of single active block makes the circuit structure simpler. No component's matching constraint is needed in the proposed circuit. The nonideal study of the proposed grounded immittance circuit is also included. The circuit's performance is examined using 0.18- μ m technology-based PSPICE simulations. Experimental results which are performed using off-the-shelf integrated circuits (ICs) and bread board are also included. The proposed circuit is negligibly affected by the temperature variation and process variation. A single pole high-pass filter as an application of the realized lossy capacitor and a band-pass filter as an application of the realized lossy inductor are also presented in this paper. The realized filters offer the feature of ease of cascadability. [ABSTRACT FROM AUTHOR]

Real-time and fast recognition of all kinds of traffic participants in intelligent driving has always been a major difficulty in the research of internet of vehicles. With the advent of edge computing, we try to deploy an image recognition algorithm directly to the intelligent vehicles. However, the original image recognition algorithm is difficult to be directly deployed on the vehicles due to limited edge device resources. Based on this, a fast recognition model of vulnerable traffic participants based on depthwise separable convolutional neural network (DSCYOLO) is proposed in this paper. The algorithm can significantly reduce the convolutional parameter quantity and computing load, making it suitable for deployment on the vehicle-mounted edge embedded devices. In order to validate the effectiveness of the proposed method, its simulation results are compared with the main target detection models Faster R-CNN, SSD and YOLOv3. The results show that the recognition time of the proposed model is reduced by 80.28%, 66.80% and 86.74%, respectively, on the basis of a relatively high recognition precision. The model can realize real-time detection and fast recognition of vulnerable traffic participants, so as to avoid a large number of traffic accidents. It has significant social and economic benefits. [ABSTRACT FROM AUTHOR]

In this paper, a second-order discrete-time (DT) modulator for 8-channel Incremental Sigma-Delta analog-to-digital converter (IADC) is presented for biomedical applications ranging from kHz. The proposed DT modulator with input bandwidth of 25 kHz on each channel is sampled at 51.2 MHz, with oversampling ratio of 128 implemented at 180 nm technology. The proposed IADC has high resolution, multichannel A/D conversion, simple architecture, low offset, low gain error and low area over the standard ADCs available. Measured results show that the SNR, DR, ENOB, power consumption and chip area of the proposed IADC are 63.9 dB, 62.2 dB, 10.11 bits, 0.832 mW and 0.032 mm2, respectively, at 1.8V power supply. For testing purpose, the noncoherent sampling is done to get the FFT plot of the output signal. For further validation, the proposed second-order IADC was also designed and compared in MATLAB/Simulink. [ABSTRACT FROM AUTHOR]

Images play an important role in transmitting visual information in our life. It could lead to severe consequences if images are manipulated or tampered maliciously. Digital forensics is an important research area to secure multimedia information. Many forensics technologies are applied to protect our community from the abuse of digital information. In many cases, after tampering, attackers could apply operations such as resampling, JPEG compression, blurring, etc. to cover the traces of tampering. Therefore, it is necessary to detect these manipulations in image forensics before exposing forgeries. In this paper, we propose to employ the prediction error filters, ConvNeXt blocks and convolution modules to classify images with different compression quality factors and resampling rates. By tracing the inconsistencies of resampling rates and compression quality factors, it could provide supplementary information for forensics researchers to expose possible forgeries. The proposed method could achieve great classification performance regardless of the interpolation algorithms. Also, it is highly robust against JPEG compression. In addition, the proposed method can be applied for estimating quality factors of JPEG compression. [ABSTRACT FROM AUTHOR]

To accurately predict the wind power and adopt methods to balance the fluctuation of power grid, an improved long short-term memory (LSTM) neural network wind power forecast algorithm based on noise reduction by threshold empirical modal decomposition (TEMD) is proposed. First, the actual operation and maintenance data of wind farms are normalized and divided into a training set and a test set. Then, an LSTM structure is designed and a Sub-Grid Search (SGS) algorithm is proposed to optimize the hyperparameters of the LSTM network. Finally, the power data are decomposed and noise-reduced using TEMD is improved by the variable-point technique and the TEMD-LSTM power forecast model is constructed to predict the power in time. The predicted values obtained are restored and evaluated by the original size. The results show that compared with five other algorithms of the same kind, the proposed algorithm in this paper has a root mean square error (RMSE) of 30.40, a trend accuracy (TA) value of 67.23% and a training time of 886 s, with the best overall performance. [ABSTRACT FROM AUTHOR]

In this paper, we present a monolithic microwave-integrated circuit (MMIC) asymmetric Doherty power amplifier (ADPA) using 0.25 μ m gallium-nitride (GaN) process with a compact chip size of 2.9 mm × 1.9 mm in wireless transmitters. Two different power amplifiers are adopted to solve the contradiction between the output power and efficiency of the conventional Doherty power amplifier (CDPA). In addition, phase compensation and low Q impedance inverting network (IIN) technology are used in the input and output matching networks, respectively, to expand the bandwidth of the entire ADPA. The post-layout simulation results show that the designed ADPA has a saturation output power 42.5 dBm with 800 MHz bandwidth from 6.6 to 7.4 GHz. The ADPA demonstrates 36.8–41.8% power-added efficiency (PAE), whereas 44–54% drain efficiency (DE) is achieved at saturation power. [ABSTRACT FROM AUTHOR]

As a novel means of high-speed transportation, the Hyperloop can proceed at an ultra-high speed (more than 1000 km/h) in the long and narrow pipelines. In this paper, the channel characteristic of the Hyperloop wireless communication systems is the main objective. Based on the geometric scattering theories, a novel nonstationary channel model is proposed to investigate the channel characteristics for Hyperloop train-to-ground communications. According to this model, the channel impulse response (CIR) is obtained, and the closed-form expressions of the multi-link spatial-temporal correlation functions, including the spatial cross-correlation function (CCF) and the temporal autocorrelation function (ACF) are derived and analyzed. Simulation results show that a high correlation between the multi-link channels in vacuum tube scenario can be observed. The relevant research results will contribute to the design of future Hyperloop wireless communication system. [ABSTRACT FROM AUTHOR]

The explosive growth of video applications has produced great challenges for data storage and transmission. In this paper, we propose a new ROI (region of interest) encoding solution to accelerate the processing and reduce the bitrate based on the latest video compression standard H.265/HEVC (High-Efficiency Video Coding). The traditional ROI extraction mapping algorithm uses pixel-based Gaussian background modeling (GBM), which requires a large number of complex floating-point calculations. Instead, we propose a block-based GBM to set up the background, which is in accord with the block division of HEVC. Then, we use the SAD (sum of absolute difference) rule to separate the foreground block from the background block, and these blocks are mapped into the coding tree unit (CTU) of HEVC. Moreover, the quantization parameter (QP) is adjusted according to the distortion rate automatically. The experimental results show that the processing speed on FPGA has reached a real-time level of 22 FPS (frames per second) for full high-definition videos (1 , 9 2 0 × 1 , 0 8 0), and the bitrate is reduced by 10% on average with stable video quality. [ABSTRACT FROM AUTHOR]

This paper presents a method for generating optimum multi-level implementations of Boolean functions based on Satisfiability (SAT) and Pseudo-Boolean Optimization (PBO) problems solving. The method is able to generate one or enumerate all optimum implementations, while the allowed target gate types and gates costs can be arbitrarily specified. Polymorphic circuits represent a newly emerging computation paradigm, where one hardware structure is capable of performing two or more different intended functions, depending on instantaneous conditions in the target operating environment. In this paper we propose the first method ever, generating provably size-optimal polymorphic circuits. Scalability and feasibility of the method are documented by providing experimental results for all NPN-equivalence classes of four-input functions implemented in AND–Inverter and AND–XOR–Inverter logics without polymorphic behavior support being used and for all pairs of NPN–equivalence classes of three-input functions for polymorphic circuits. Finally, several smaller benchmark circuits were synthesized optimally, both in standard and polymorphic logics. [ABSTRACT FROM AUTHOR]

In this paper, based on the combination scheme of dual-sampling and adaptive predictive PID control, a digital controller for improving the transient performance of Buck DC–DC converters is designed. Due to the inherent loop delay in analog-to-digital (A/D) conversion, the calculation process of the digital controller and digital pulse width modulator (DPWM) of conventional digitally-controlled Buck DC–DC converters limits the system bandwidth and this makes the transient response lower. The designed digital controller can reduce the delay time in analog-to-digital converter (ADC), the digital controller and DPWM of digitally-controlled Buck DC–DC converters. Adaptive predictive control is used to eliminate the delay time of ADC and the digital controller, while dual-sampling scheme is used to reduce the delay time of DPWM in this paper. These are two new control schemes, and they show better performance in improving the transient response than other existing control schemes. Both simulation and experimental results demonstrate that the designed digital controller based on dual-sampling and adaptive predictive PID control is effective in improving the transient performance of Buck DC–DC converters. During experimental verification, for a load step between 0.5 A and 1.0 A, the fastest transient recovery time and the overshoot voltage are found to be 102 μ s and 120 mV, respectively. Compared with the conventional digital PID controller, the transient recovery time and the overshoot voltage of the digital controller designed in this paper are decreased by 40.0% and 27.3%, respectively. [ABSTRACT FROM AUTHOR]

Passive network synthesis, as an important part of circuit and system theory, has been well developed in integer-order circuits. With the development of fractional-order calculus and fractional-order elements, the problem of using fractional-order passive networks to realize fractional-order immittance functions has drawn much attention. In this paper, the realization of a fractional-order biquadratic immittance function is considered. First, the form of a fractional-order biquadratic function and some theorems that could promote later research are introduced. Second, a detailed study for the realization of a fractional-order biquadratic immittance function is shown. Finally, through summarizing the realizability conditions of each network, we have obtained the scope of fractional biquadratic impedance functions that can be realized by this paper. [ABSTRACT FROM AUTHOR]

In this paper, a novel dual-band monopole planar antenna is presented. The antenna is operated in 28/38 GHz and has a bandwidth of 0.5/0.7 GHz to operate in 5G frequency bands. Additionally, it exhibits a stable omni-directional radiation pattern with high gain characteristics, which helps to improve the performance of future 5G communication devices. The radiation efficiency achieved more than 94% throughout its operating bands. The numerical analysis has been carried out using a three-dimensional (3D) full-wave electromagnetic solver (ANSYS HFSS). In order to validate the numerical analysis, the proposed antenna has been fabricated and shows a good agreement with simulated results. The antenna has been designed and fabricated on Roger RT/Duroid 5880 dielectric substrate. This paper paves a new idea to design dual-band, simple and miniaturized single-element monopole planar antennas, which would be a good candidate for future millimeter-wave 5G communication systems. [ABSTRACT FROM AUTHOR]

This paper deals with the designing of low-power transconductance–capacitance-based loop filter. The folded cascode-based operational transconductance amplifier (OTA) is designed in this paper with the help of quasi-floating bulk MOSFET that achieved the DC gain of 88.61 dB, unity gain frequency of 97.86 MHz and power consumption of 430.62 μ W. The proposed OTA is compared with the exiting OTA structure which showed 19.50% increase in DC gain and 15.11% reduction in power consumption. Further, the proposed OTA is used for the designing of transconductance–capacitance-based loop filter that has been operated at − 3 dB cut-off frequency of 30.12 MHz with the power consumption of 860.90 μ W at the supply voltage of ± 1. 5 V. The transistor-level simulation has been done in 0.18 μ m CMOS process. [ABSTRACT FROM AUTHOR]

In this paper, we consider a covert communication system with a multi-antenna full-duplex (FD) receiver to enhance covert performance. More precisely, the receiver Bob (i.e., multiple antennas) selects the best antenna to receive the covert message, and then it sends artificial noise (AN) to the warden Willie causing uncertainty by utilizing an antenna among the remaining antennas. In order to take full advantage of multi-antenna technology, we consider two cases: (1) Willie does not know which antenna Bob chooses to send AN, and Willie knows only part of the channel information. (2) Willie knows which antenna Bob chooses to send AN, and Willie knows all the channel information. Based on the analysis of the optimal detection threshold, we derive the minimum detection error probability of the two cases. Furthermore, given the pre-determined convert constraints, the closed-form expression of the maximum effective convert rate is derived. When the power of AN sent by Bob is greater than that of covert message sent by the sender Alice, surprised research results are shown: (1) the detection error rate of case 1 is higher than that of case 2. (2) the effective covert rate of case 1 is always lower than that of case 2. The simulation results show that the proposed scheme is more conducive to sending covert messages for Alice; in addition, the numerical results imply that the maximum effective covert rate of the system using the multi-antenna FD receiver is significantly higher than that of the traditional dual-antenna FD receiver system. [ABSTRACT FROM AUTHOR]

The objective of this paper was to propose a second generation voltage conveyor (VCII)-based new voltage mode biquad, equivalent to Kerwin–Huelsman–Newcomb (KHN) biquadratic circuit. The proposed circuit helped to efficiently add and subtract voltages by exploiting the virtual ground at one of the terminals of VCII, and without compromising on the features of the filters, such as the independent tuning of the quality factor (Q) and characteristic frequency ( ω o ). The proposed circuit's viability has been verified through LTspice simulations. The paper also presented the nonideal, the sensitivity, distortion, linearity and Monte Carlo analysis of the filters of the proposed circuit. [ABSTRACT FROM AUTHOR]

Optical character recognition (OCR) is a computer vision technique that enables computers to recognize text from images. Text detection and computer vision have made significant advancements, leading to the development of various OCR technologies. However, selecting the most suitable OCR system for a specific purpose has become a challenging task. This research paper aims to explain the theoretical concepts and mathematical formulas underlying OCR engines, providing a better understanding of their functioning and performance. The analysis covers various aspects, including the theories, algorithms, and techniques employed by OCR engines. This paper presents experiments conducted on five different image categories: vehicle number plates, receipts, handwriting, symbols and plain text images. Evaluation metrics such as Character Error Rate (CER), Word Error Rate (WER), Insertion Error Rate (IER), Deletion Error Rate (DER), End-to-end recognition rate (EEER), Word Error Rate (WER), Recall, Precision, and F1-score were utilized. The findings reveal that OCR systems perform well on plain documents, with recall and F1-score values exceeding 0.85 and 0.8, respectively. However, there are still areas for improvement in OCR, which are discussed in detail in this paper. This research provides valuable insights for researchers, developers, and practitioners interested in employing OCR technology for their commercial projects. [ABSTRACT FROM AUTHOR]

This paper presents an innovative cross-coupled differential drive rectifier for dual-band Radio frequency identification (RFID) tags. A self-compensating rectifier with enhanced power-conversion efficiency (PCE) at low and high RF power is proposed. The proposed rectifier utilizes a self-compensating circuit, the extra two cross-couple transistors, to increase the gate voltage of transistors to control the conduction of the rectifying transistors. In order to adapt high frequency (HF) and ultrahigh frequency (UHF) rectification, the matching circuit is designed with parasitic cancellation technology. Moreover, the cascading power management circuits are added to generate a stable output voltage. The multi-standard rectifier is designed and simulated in 0. 1 8 μ m CMOS process. The simulated result shows that the proposed three-stage rectifier achieves a PCE 74% (at 5 0 0 k Ω load) when receiving a 915 MHz signal with average power of − 2 5 dBm. Moreover, the maximum efficiency achieves 56% at HF 13.56 MHz, and the final output voltage can be stabilized at a specific voltage of 1.052 V. [ABSTRACT FROM AUTHOR]

Comfort is an important consideration in passenger vehicles provided by a suspension system. The suspension system must be associated with the vehicle body to improve comfort for the passenger. The active suspension system (ASS) has been introduced to perform this task. Moreover, the sliding mode controller (SMC) is well known for its continuous control signals. This paper proposes the Bayesian-based proportional resonant sliding mode controller (B-PRSMC) and two degrees of the freedom-proportional resonant controller (2d-f-PR) to stabilize passenger and ride comfort. The B-PRSMC is used for examining system states under varying road disturbances based on the Bayesian theorem. After examining the system state, the system performance is controlled by the 2d-f-PR controller. The proposed method is performed on Matlab, and the results are taken regarding body acceleration, body travel and suspension deflection. The mastery of proposed method is estimated under different road profiles. The comparative analysis demonstrates that the suggested controller enhances ride and passenger comfort in varied road profiles due to the combination of B-PRSMC and 2d-f-PR controllers. [ABSTRACT FROM AUTHOR]

Deep neural networks are vulnerable to adversarial examples. While there are many methods for generating adversarial examples using neural networks, creating such examples with high perceptual quality and improved training remains an area of active research. In this paper, we propose the Iterative Training Attack (ITA), a black-box attack based on a perturbation generative network for generating adversarial examples. ITA generates such examples by randomly initializing the perturbation generative network multiple times, iteratively training and optimizing a refined loss function. Compared to other neural network-based attacks, our proposed method generates adversarial examples with higher attack rates and within a small perturbation range even when the advanced defense is employed. Despite being a black-box attack, ITA outperforms gradient-based white-box attacks even under basic standards. The authors evaluated their method on a TRADES robust model trained with the MNIST dataset and achieved a robust accuracy of 92.46%, the highest among the evaluated methods. [ABSTRACT FROM AUTHOR]

Heart failure is one of the major diseases endangering human life. As a transitional support treatment before heart transplantation, the left ventricular assist device (LVAD) has significantly improved the quality of life and survival rate of patients with end-stage heart failure. In the automatic detection of electrocardiogram (ECG), the detection of QRS wave groups is the most critical aspect, which affects the correctness and accuracy of subsequent data analysis and processing. The paper used the data from the MIT-BIH database and the data collected from human ECG as the original number of samples for further processing. It processed the data through a high-order finite impulse response (FIR) low-pass filter and Shannon energy algorithm, and added the use of a high-order adaptive median filter algorithm on a field programmable gate array (FPGA) to minimize the noise of the processed real-time data. Finally, the tested ECG R-wave was used to drive the LVAD. After successful simulation by MATLAB and Modelsim software, the scheme of the real-time ECG signal controlling blood pump system was realized on the FPGA platform. The experiment showed that the method proposed could accurately extract the R-wave and control the LVAD to pump blood simultaneously. [ABSTRACT FROM AUTHOR]

In recent times, the virtual power plant (VPP) is gaining more attention in power system engineering due to its tremendous potential in enhancing sustainable urbanism, in which, it supplies clean energy from distributed generators. Electricity is deemed a basic requirement for future automotive and ultra-modern technologies. The deficiency of traditional energy resources and their complex generation process make the production cost of electricity increase dramatically. Moreover, traditional power distribution systems are encountering issues in distributing electrical energy to fulfill customer demands. Therefore, this paper proposes a novel power management system named 'the hybrid genetic local binary knowledge (HGLBK) algorithm' to manage power distribution in the transmission lines and to optimize the total operation cost of the network. The hybrid optimization algorithm effectively controls the load by supplying the surplus power load to the adjacent feeders thereby optimally selecting and placing the distributed energy resource (DER). The proposed concept is implemented at Kayathar, Tamil Nadu in India, and their real-time data are utilized for modeling the VPP. The proposed VPP concept is implemented in the IEEE-9 bus system and the performance of VPP is simulated using the MATLAB software. The performance of the proposed HGLBK algorithm is assessed by comparing its effectiveness with the existing approaches. [ABSTRACT FROM AUTHOR]

This paper presents a new electronically tunable differential difference current conveyor (EDDCC) using the commercially available operational transconductance amplifiers (OTAs). Unlike the conventional DDCC, the proposed EDDCC offers current gain that can be electronically controlled. The EDDCC can be used to realize a new electronically tunable fully differential difference second-generation current conveyor (EFDCCII). Therefore, the current gain of the proposed EFDCCII can be electronically controlled. To show the advantages of the proposed EDDCC and EFDCCII, the EDDCC has been used to realize a quadrature oscillator and the EFDCCII has been used to realize a current-mode universal filter. The proposed circuits have been investigated by simulation and experimental tests using the commercially available LM13700 OTAs. [ABSTRACT FROM AUTHOR]

Droplet routing is a critical phase in the biochemical synthesis using digital microfluidic biochip. The goal is to transport droplets from one module to another, maintaining fluidic constraint at every instant. In this paper, we proposed a new flooding-based droplet routing protocol. It uses multiple copies of scout packets to flood the whole biochip and discover multiple routes. The explored routes are then validated by hello packets. Route length defines the priority order among droplets. The routes are mapped using a new heuristic number of shared cells. In the compaction phase, generate the parallel moving sequence for droplets. The simulation result shows 12.25% and 20.5% improvement in the latest arrival time for free and virtual topology, respectively. [ABSTRACT FROM AUTHOR]

Light emitting diodes (LEDs) have become an effective lighting solution because of the characteristics of energy efficiency, flexible controllability and extended lifetime. They find use in numerous lighting systems for residents, industries, enterprises and street lighting applications. The efficiency and trustworthiness of the LED systems considerably based on the thermal mechanical loading improved several degradation schemes and respective interfaces. The complication of the LED systems limits the theoretic interpretation of the core reasons for the luminous variation or the formation of the direct correlation among the thermal aging loading and the luminous output. Therefore, this paper designs a new hybrid Henry gas solubility optimization with deep learning (HHGSO-DL) algorithm for LED driver system design. The presented HHGSO-DL technique mainly concentrates on the derivation of empirical relationships among the design parameters, thermal aging loading and luminous outcomes of the LED product. In the presented HHGSO-DL technique, bidirectional long short-term memory (BiLSTM) algorithm is executed for examining the empirical relationship and its hyperparameters can be tuned by the HHGSO algorithm. In this work, the HHGSO algorithm is derived by the integration of traditional HGSO algorithm with oppositional-based learning (OBL) concept. The performance of the HHGSO-DL technique can be investigated on LED chip packaging and LED luminaire with thermal aging loading. The extensive results demonstrate the promising performance of the HHGSO-DL technique over other state-of-the-art approaches. [ABSTRACT FROM AUTHOR]

Most of the existing static analysis-based detection methods adopt one or few types of typical static features for avoiding the problem of dimensionality and computational resource consumption. In order to further improve detecting accuracy with reasonable resource consumption, in this paper, a new Android malware detection model based on multiple features with feature selection method and feature vectorization method are proposed. Feature selection method for each type of features reduces the dimensionality of feature set. Weight-based feature vectorization method for API calls, intent and permission is designed to construct feature vector. Co-occurrence matrix-based vectorization method is proposed to vectorize opcode sequence. To demonstrate the effectiveness of our method, we conducted comprehensive experiments with a total of 30,000 samples. Experimental results show that our method outperforms state-of-the-art methods. [ABSTRACT FROM AUTHOR]

In this paper, a new three-dimensional chaotic system with two exponential nonlinearities is presented. The analysis of fixed points of the proposed system suggests existence of one hyperbolic index-2 spiral saddle-type fixed point. The proposed system fulfils Shilnikov criterion and nature of the chaos is found to be dissipative. Bifurcation diagrams, maximum Lyapunov exponents and Kaplan–Yorke dimension are examined through numerical simulations to investigate dynamics of proposed system. The hardware feasibility of the proposed system is illustrated through current feedback operational amplifier (CFOA)-based circuit implementation. The proposed circuit uses six CFOAs, two diodes to establish nonlinearity, eleven resistors and three capacitors. The absence of analog multiplier in the proposed circuit makes it superior to the existing counterpart in the sense that it does not require area and power-consuming active building block. To confirm the chaotic nature of the proposed circuit, LTspice simulations are done to obtain phase portraits which are found to be strange attractors and are topologically different from the shape of the existing attractors. Moreover, we have investigated the synchronization of the proposed chaotic system using adaptive control scheme and proposed CFOA-based complete circuit design of the adaptively synchronized system. Also, the effect of the tolerance of passive components and temperature on the behavior of the proposed chaotic circuit and the complete synchronization circuit has also been studied. It is found that the circuit is sensitive to the value of resistors and temperature to an extent and can work properly within their limits. [ABSTRACT FROM AUTHOR]

This paper aims to bring a voltage differencing inverting buffered amplifier (VDIBA)-based current-mode (CM) proportional integral derivative (PID) controller circuit. This CM PID controller is designed with a single VDIBA, three resistors, and two grounded capacitors. The proposed circuit is easy to design, and the control parameters can be tuned without changing the design configuration. A sensitivity analysis of the control parameters to electronic components has been conducted. The Simulation Program with Integrated Circuit Emphasis (SPICE) simulation has been performed using Taiwan Semiconductor Manufacturing Company (TSMC) 0. 1 8 μ m complementary metal-oxide semiconductor (CMOS) technology parameters. An application circuit example is given to demonstrate the reliability of the proposed PID design. A comparison table of the PID controllers previously reported in the literature is also presented. [ABSTRACT FROM AUTHOR]

Many researchers are actively working on developing a fast-performing static random-access memory (SRAM) cell with low-power consumption and high stability. This study also introduces one such new and all-round excellent SRAM cell. In this paper, an SRAM cell with eleven transistors (11T) developed using carbon nanotube field effect transistor (CNTFET) is introduced. This new 11T CNTFET SRAM cell is another variant of the Schmitt-trigger (ST)-based SRAM cell. This new SRAM cell structure is achieved by incorporating a single-ended write mode, a feed-back cutting technique and a single-ended read approach into a Schmitt-trigger (ST)-based SRAM cell. The WSNM of the proposed 11T CNTFET SRAM cell is increased by using single-ended writing scheme and feed-back cutting method in the cell. The single ended read approach of 11T CNTFET SRAM cell increases the RSNM as the storage nodes are not disturbed. The write power, hold power, read power, WSNM, HSNM, RSNM, write delay and read delay of this 11T CNTFET SRAM cell are 2.1538e-10 W, 1.7077e-09 W, 1.4524e-08 W, 423.61 mV, 402.20 mV, 425.56 mV, 1.2932e-10s and 5.5225e-12s, respectively. The parameters of the proposed cell are compared with 6T SRAM [M. Elangovan and K. Gunavathi, Stability analysis of 6T CNTFET SRAM cell for single and multiple CNTs, 2018 4th Int. Conf. Devices, Circuits Syst., Coimbatore, India, 16–17 March 2018, vol. 2, pp. 63–67], 8T SRAM [M. Elangovan, A novel Darlington based 8T CNTFET SRAM cell for low, J. Circuits Syst. Comput.30 (2021) 2150213], 12T SRAM [S. Pal, S. Bose, W. H. Ki and A. Islam, Half-select-free low-power dynamic loop-cutting write assist SRAM cell for space applications, IEEE Trans. Electron Dev. 67 (2020) 80–89, doi:10.1109/TED.2019.2952397], 12T SRAM [N. Yadav, A. P. Shah and S. K. Vishvakarma, Stable, reliable, and bit-interleaving 12T SRAM for space applications: A device circuit co-design, IEEE Trans. Semicond. Manuf. 30 (2017) 276–284, doi:10.1109/TSM.2017.2718029], 12T SRA-M [P. Sharma, S. Gupta, K. Gupta and N. Pandey, A low power subthreshold Schmitt Trigger-based 12T SRAM bit cell with process-variation-tolerant write-ability, Microelectron. J. 97 (2020) 104703, doi:10.1016/j.mejo.2020.104703] and 12T SRAM [P. Sharma, S. Gupta, K. Gupta and N. Pandey, A low power subthreshold Schmitt Trigger based 12T SRAM bit cell with process-variation-tolerant write-ability, Microelectron. J. 97 (2020) 104703, doi:10.1016/j.mejo.2020.104703] cells to understand the performance of the proposed SRAM cell. From the comparative study, it is observed that the proposed cell is more stable than the other cells considered for the comparison and consumes less power in all write, read and hold modes. Also, the read time of the introduced cell is much less than the others. This study also recorded the information on how the performance of an SRAM cell varies as the CNTFET parameters change. The simulation is done with the HSPICE simulation tool using the Stanford University 32 nm CNTFET model. [ABSTRACT FROM AUTHOR]

The new-generation Sunway supercomputer has ultra-high computing capacity. But due to the unique heterogeneous architecture of the supercomputer, the open-source versions of basic linear algebra subprograms (BLAS) are insufficient for performance or compatibility. In addition, due to the update of the architecture, BLAS based on the previous Sunway could not fully exploit the performance of the successor. To address the challenges, we propose an optimized BLAS on the new-generation Sunway supercomputer in this paper. Specially, for achieving efficient computation, a parallel optimization method based on the new-generation Sunway for the Level-1 BLAS computing between vectors and the Level-2 BLAS computing between vectors and matrices is first proposed. Then, an adaptive scheduling algorithm for various data sizes is proposed, which is used to balance the tasks of core groups. Finally, to achieve highly efficient general matrix multiplication (GEMM) kernels, a parallel optimization method based on the new-generation Sunway for the Level-3 BLAS computing between matrices is proposed, which includes source-level optimization as well as assembly-level optimization. Experimental results show that the memory bandwidth utilization of the optimized Level-1/2 BLAS exceeds 95%, and the computational efficiency of the optimized GEMM kernel exceeds 94%. [ABSTRACT FROM AUTHOR]

Soft errors are the most common aspect of errors that are incurred in the memory devices during transmission. The common and fundamental reason of these soft errors is radiation that produces leakage of current and results in misleading information which is sent to various transmission stations via satellite and microwave communication. In this paper, the real-time embedded system is designed and implemented to mitigate the soft error using hybrid Hamming code. The work also develops the hardware system for soft error mitigation. The designed system is compared with the other coding schemes that are commonly available for error mitigation. The performance of real-time embedded system for soft error mitigation is carried out using signal-to-noise ratio and other performance metrics. The timing diagram analysis is the key metrics of the paper that defined the performance of the designed soft error mitigation design using the proposed technique. Furthermore, the results of the designed systems are demonstrated using bit error probability, Pb and channel symbol error probability (CSEP). The impact of the designed system will be that from now onwards using the proposed system, the soft error produced due to radiation and other reasons would not affect too much on transmission and reception of important data via satellite and microwave communication. [ABSTRACT FROM AUTHOR]

The battery pack powers the electric motor in a battery-operated electric vehicle. To achieve the required power, the cells are connected in series and parallel combinations to form a battery pack. The battery pack is monitored using the battery management system. During the charging and discharging process, imbalance occurs in the cells due to intrinsic and extrinsic properties of the battery chemistry. This cell imbalance induces problems, such as an under-discharge, over-charge, increase in charging time and reduction in battery lifecycle. The passive and active balancing technique is employed to balance the individual cells in the battery pack. In this paper, the adaptive passive cell balancing is performed for a battery pack of six series-connected Li-ion cells of rating 3.6 V, 4 Ah under ideal, charging, discharging and drive cycle conditions using MATLAB/Simscape. In this proposed adaptive passive cell balancing methodology, a dynamic resistance is selected based on the threshold values to balance the individual cells in the battery pack. For this battery pack, the proposed design achieves 34% reduction in balancing time, 17% reduction in energy loss, and 14% reduction in power loss under ideal conditions. The experimental verification is also done and shows that the balancing time is about 2400 s. The capacity fade factor of the battery pack is also analyzed. [ABSTRACT FROM AUTHOR]

Micro-Electro-Mechanical System (MEMS)-based pressure sensors operating on the principle of piezoresistivity have found profound application in various fields like automobile, aerospace, aviation, biomedical and consumer electronics. Various research studies have been conducted to optimize the design of MEMS-based pressure sensors to meet specific requirements of different fields. Modification in the structure of the piezoresistors placed on these sensors has shown great effect in this regard. However, most of these improvements have been validated through fabrication and measurement, but there has been a lack of significant studies developing analytical models to explain these improvements. This paper studies the performance of a single-turn piezoresistor design on a square silicon diaphragm. The analytical model relates the dimensions of the single-turn piezoresistor on a square diaphragm to the output voltage, and hence, sensor sensitivity is laid out. The correctness of the relation is also validated through Finite Element Analysis (FEA) performed using COMSOL Multiphysics software. Hence, an optimized single-turn design is presented which achieves a sensitivity of 203.57 mV/V/MPa over a pressure range of 0–1 MPa. These results are then compared to work from existing literature. The comparison shows an improved performance which was achieved by optimizing the design through its derived analytical model. The proposed sensor can be utilized in disposable blood pressure measurement system where high sensor sensitivity is required. [ABSTRACT FROM AUTHOR]

The increasing sophistication of cyberattacks on blockchain systems has significantly disrupted security experts from gaining immediate insight into the security situation. The Cybersecurity Knowledge Graph (CKG) currently provides a novel technical solution for blockchain system situational awareness by integrating massive fragmented Cyber Threat Intelligence (CTI) about blockchain technology. However, the existing literature does not provide a solution for building CKG appropriate for blockchain systems. Therefore, designing a method to construct a CKG for blockchain systems by efficiently extracting information from the CTI is mandatory. This paper proposes PipCKG-BS, a pipeline-based approach that builds CKG for blockchain systems. The PipCKG-BS incorporates contextual features and Pre-trained Language Models (PLMs) to improve the performance of the information extraction process. Precisely, we develop the Named Entity Recognition (NER) and Relation Extraction (RE) models for cybersecurity text in PipCKG-BS. In the NER model, we apply the prompt-based learning paradigm to cybersecurity text by constructing prompt templates. In the RE model, we employ external features and prior knowledge of sentences to improve entity relationship extraction accuracy. Several experimental results demonstrate that PipCKG-BS is better than advanced methods in extracting CTI information and is an appealing solution to build high-quality CKG for blockchain systems. [ABSTRACT FROM AUTHOR]

In this paper, the implementation of the Fuzzy Sliding Mode Controller (FSMC) in the inner loop of the cascaded control structure of the DC–DC Boost Converter is presented. On account of nonlinearity and nonminimum phase nature, switched-mode DC–DC converters show a poor response in their dynamic characteristics. In most of the works, the inner loop is served by SMC/FLC, and the outer loop by PI. In this study, the proposed FSMC, which is the combination of SMC and FLC is recommended in the inner current loop which reduces the chattering phenomena and improves the robustness against uncertainties, disturbances and varying circuit parameters with the reaching law. The Lyapunov approach is considered to study the stability of the proposed controller. A comparative analysis is made with the results obtained from the proposed FSM controller, Fuzzy and SMC control. The effectiveness of the FSMC controller is validated by observing its system performance. [ABSTRACT FROM AUTHOR]

In public-key cryptography, the RSA algorithm is an inevitable part of hardware security because of the ease of implementation and security. RSA Cryptographic algorithm uses many modular arithmetic operations that decide the overall performance of the architecture. This paper proposes VLSI architecture to implement an RSA public-key cryptosystem driven by the Residue Number System (RNS). Modular exponentiation in the RSA algorithm is executed by dividing the entire process into modular squaring and multiplication operations. Based on the RNS employment in modulo-exponential operation, two RSA architectures are proposed. A Verilog HDL code is used to model the entire RSA architecture and ported in Zynq FPGA (XC7Z020CLG484-1) for Proof of Concept (PoC). The Cadence Genus Synthesizer tool characterizes a system's performance for TSMCs standard Cell library. Partial RNS (Proposed-I)- and Fully RNS (Proposed-II)-based RSA architectures increase the operation speed by 13% and 35%, respectively, compared with the existing RSA. Even though there is an increase in parameters like area, power and PDP for a smaller key size, the improvement in area utilization and encryption/ decryption speed of RSA for a larger key size is evident from the analysis. [ABSTRACT FROM AUTHOR]

It is crucial to correctly assess whether a potential borrower can repay the loan in the credit scoring model. The credit loan data has a serious data imbalance because the number of defaulters is far less than the nondefaulters. However, most current methods for dealing with data imbalance are designed to improve the classification performance of minority data, which will reduce the performance of majority data. For a financial institution, the economic loss caused by the decrease in the classification performance of nondefaulters (majority data) cannot be ignored. This paper proposes an ensemble learning method based on one-class and binary classification (EMOBC) for credit scoring. The purpose is to improve the classification accuracy of the minority class while mitigating the loss of classification accuracy of the majority class as much as possible. EMOBC uses undersampling for the majority class (nondefault samples in credit scoring) and perform binary-class learning on the balanced data to improve the classification accuracy of the minority. To alleviate the decline in classification performance of the majority class, EMOBC uses one-class and binary collaborative classification to train classifiers. The classification result is determined by the average of one-class and binary-class classifiers. The experimental results show that EMOBC has good comprehensive performance compared with the existing methods. [ABSTRACT FROM AUTHOR]

In this paper, the performance of dual-material stacked gate oxide-source dielectric pocket-tunnel field-effect transistor (DMSGO-SDP-TFET) has been investigated by considering fixed interface trap charges (ITCs) at the Si–SiO2 interface. During the analysis, both types of trap charges, positive (donor) and negative (acceptor), have been considered to investigate their effect on the DC, analog/ radio frequency, linearity and harmonic distortion performance parameters in terms of the carrier concentration, electric field, band-to-band tunneling rate, transfer characteristics, transconductance ( g m ), unity gain frequency ( f T ), gain–bandwidth product, device efficiency ( g m / I DS ), transconductance frequency product, transit time (τ), second- and third-order transconductance and voltage intercept points ( g m 2 , g m 3 , VIP2 and VIP3), third-order Input Intercept Point and Intermodulation Distortion (IIP3, IMD3), second-, third-order and total harmonic distortions (HD2, HD3 and THD), respectively. Further, the impact of temperature variations from 2 0 0 K to 5 0 0 K in the presence of ITCs is investigated and the results are compared with conventional DMSGO-TFET. In terms of percentage variation, DMSGO-SDP-TFET depicts lower variation than conventional DMSGO-TFET, indicating that the proposed device is more immune to trap charges and can be used for energy-efficient, high-frequency and linearity applications at elevated temperatures. [ABSTRACT FROM AUTHOR]

Micro-Electro-Mechanical System (MEMS) capacitive accelerometers have received extensive attention in recent years due to their excellent performance indicators; especially in the fields of noise, power consumption, and bias instability, great development and progress have been made. In the field of noise, effective noise reduction is achieved by introducing oversampling modulation technology combined with digital noise reduction technology. In power consumption, the power consumption of the accelerometer is effectively reduced by using the successive approximation structure in the interface circuit and using the finite state machine for precise control. In bias instability, the effects of temperature offset and zero-point drift are suppressed by using a hybrid topology connection structure in the interface circuit, and an effective reduction of bias instability is achieved. In this paper, the research and progress of MEMS capacitive accelerometer in the field of noise, power consumption and bias instability are reviewed, and the articles published in recent years are listed and summarized and prospected. [ABSTRACT FROM AUTHOR]

A constant voltage AC-DC converter based on the digital assistant technology is proposed in this paper, which has the advantage of high output precision. In this paper, a novel digital exponential wave generator is adopted in Constant Voltage (CV) mode to replace the normal triangle waveform to obtain a wider range of switching frequency, increasing the accuracy of output voltage under light load. The control chip is implemented based on NEC 1m 5V/40V HVCMOS process, and a 5V/1.2A prototype has been built to verify the proposed control method. In PFM mode the deviation of output voltage is within % and the load regulation is %. Meanwhile, when the load jumps from light to heavy, the minimum output voltage could be maintained above 4.16V. [ABSTRACT FROM AUTHOR]

This paper presents a two-stage enhanced gain bulk-driven floating gate OTA (EG-BDFG OTA) using flipped voltage follower (FVF). The gain of the OTA is increased with the help of a self-biased summing stage followed by a conventional common-source stage. To ensure the stability of the proposed two-stage OTA, cascode compensation technique is used. The circuit is designed and simulated in Cadence Virtuoso tool using UMC 0.18- μ m CMOS technology library. The simulation results indicate that the proposed design has an improved voltage gain of 59 dB that is 3.5 times more than that of the single-stage BDFG-FVF OTA. The linearity of the proposed OTA is almost maintained while enhancing the gain by 42 dB. The circuit delivers − 65 dB of HD3 and − 56 dB of THD when a 0.2-Vpp differential input signal of 1-MHz frequency is applied. The circuit is also verified for process variations at different corners with the aid of Monte Carlo and Corner analyses. The layout of the proposed EG-BDFG OTA is also drawn and presented in the paper. [ABSTRACT FROM AUTHOR]

In this paper, a new true random number generator (TRNG) based on a new variable differential ring oscillator has been presented. In this structure, the ring oscillator's jitter is considered a random phenomenon. The jitter of the proposed ring oscillator is driven by thermal noise and flicker noise so that the generated jitter is random. In this paper, a new variable differential ring oscillator has been designed. The stage of this ring oscillator is changed randomly in order to create random jitter. A new differential delay cell has been proposed to boost the speed of TRNG and random jitter. The proposed random number generator (RNG) is robust against temperature variations of − 40–120 ∘ C and voltage variations from 0.8 to 1.8 V. The proposed system's bitrate is 50 MB/s and its efficiency is 30.03 Mb/mJ. This process has been implemented in the 0.18 um CMOS process. Simulation results have been presented in Hspice software and cadence. The output bit images have been displayed by Matlab software. [ABSTRACT FROM AUTHOR]

Battlefield of Things (BoT) is a modern defense network that connects smart military devices to strategic networks. Cybersecurity plays a vital role in maintaining the security of BoT networks and provides encrypted communication networks with combat devices on an end-to-end or peer-to-peer basis. This paper proposes approaches to BoT networks that operate on a three-tier architecture, starting with an application and service layer, a network and cybersecurity layer, and finally, a battlefield layer; implements CNN-YOLO-based target detection; and also formulates information security policies, privacy, and IT laws to maintain algorithmic data access and authorization. It connects a battlefield combat equipment network to a command data center's ground base station wireless, Bluetooth, sensor, radio, and ethernet cable. This paper analyzes prior Internet of Things (IoT) device attack strategies by collecting data sets of IoT security breaches from external sources. How the system security works, what breach techniques an attacker can use, how to avoid these, and how our systems can be strengthened to protect us from future attacks are discussed in detail. [ABSTRACT FROM AUTHOR]

The lightning current dispersion process through the steel bar inside the concrete pile foundation of the transmission line tower is impeded by the high concrete resistivity. In order to improve the current dispersion performance of the pile foundation, this paper proposes a method to place flexible graphite grounding electrode along the shaft wall of the tower foundation and verified its feasibility. Both single-pile and four-pile foundations are applied to build vertical grounding models of transmission line tower with three different grounding structures, respectively, including flexible graphite grounding line, flexible graphite grounding fabric and combined graphite electrode. The effect of three grounding structures on the current dispersion and resistance reduction is studied by finite-element method. Simulation results indicate that by applying the above three grounding structures on the vertical pile foundation can significantly improve the current density distribution of the excavated pile foundation and reduce the grounding resistance. When the grounding resistance is 2 0 0 Ω ⋅ m , the resistance reduction efficiencies of the above three methods can reach 48.56%, 53.86% and 54.53%, respectively. Considering the limited construction area, this paper compares the foundation that is placed combined graphite grounding electrode with square-ray grounding grid, and it can be seen that by placing vertical grounding electrode can save the land area of 295.99 m2. This paper can provide reference for the design of excavation pile foundation grounding structure under limited construction area. [ABSTRACT FROM AUTHOR]

Online crowdfunding, an innovative model based on " Internet + Finance ", is a hot spot for financing via Internet. Crowdfunding based on blockchain is an emerging economic phenomenon and becomes one of the most advanced risk financing strategies. However, crowdfunding transactions face security threats due to identity leaks, quantum attacks and the untraceable nature of blind signatures, which facilitate criminal activity. Different from the previous works, which ignored the importance of traceability, in this paper, we establish a blockchain-empowered secure crowdfunding architecture and propose an anti-quantum partially blind signature algorithm based on the verifiable identity of both sides. Specially, for one thing, the private key decided by user identity is generated by lattice-based sample matrix, and the privacy of user identity can be ensured and traced by the rejection sampling theorem. For another thing, we design an improved krill herd algorithm (IKHA) to increase the credit factor of fundraisers for dealing with project investment issues. The simulation evaluates the correctness and effectiveness of our theoretical analyses. Compared with the current popular schemes, the proposed IKH algorithm has a higher convergence speed and can optimize investment efficiency. [ABSTRACT FROM AUTHOR]

With the continuous development of encryption technology, the share of encrypted traffic in the network is increasing, which brings great challenges to the traditional methods of rule-based traffic identification. Deep learning is becoming an inspiring methodology to solve the problem. Previous studies have confirmed that time characteristics play an important role in Tor traffic classification. We find that there is a similarity of time characteristics among different programs. This paper proposes an end-to-end classification framework: the temporal sequence of data fluctuation network (TSDFN). It first extracts the temporal sequence of data fluctuation in the original flow and then uses the GRU network to learn the hidden temporal features. Experiments on public data sets validate the effectiveness of our proposal over other methods. [ABSTRACT FROM AUTHOR]

Existing Bayesian network (BN) structure learning algorithms based on dynamic programming have high computational complexity and are difficult to apply to large-scale networks. Therefore, this paper proposes a Dynamic Programming BN structure learning algorithm based on Mutual Information, the MIDP (Dynamic Programming Based on Mutual Information) algorithm. The algorithm uses mutual information to build the maximum spanning tree and M -order matrix, and introduces a penalty coefficient d based on the matrix-based node removal strategy, so as to reduce the number of scoring calculations and time consumption of the algorithm. Simulation results show that, compared with DP, SMDP and MEDP algorithms, the MIDP algorithm can reduce the calculation times and time consumption of algorithm scores while maintaining the accuracy of the algorithm when selecting the appropriate d value. [ABSTRACT FROM AUTHOR]