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In this paper, a portable low-power low dropout regulator (LDO) with no output capacitance has been designed in 0.18- μ m CMOS technology. In this paper, a PMOS power transistor is used and combined with an overshoot and undershoot suppression circuit to improve the transient response of the circuit. A modified Class-AB operational transconductance amplifier (OTA) is used to reduce power consumption and act as an error amplifier to eliminate low frequency poles. At the same time, a super source follower and a Miller capacitor are used for frequency compensation of the system. Finally, the system can provide a stable voltage for a load step from 0.2 to 25 mA in 500 ns edge-time for 140 pF-load capacitance. The test results show that the circuit achieves a good voltage regulation rate and high transient response. [ABSTRACT FROM AUTHOR]

This paper proposes a novel approach for low-power applications for the fast estimation of filter capacitor value and the output performance parameters such as average, and Root Mean Square (RMS) values for the voltage and current considering single-phase full-wave, three-phase half-wave and three-phase full-wave rectifier circuits. For this aim, the novel equations in this work are derived for the average output voltage and rms ripple voltage separately for each of the above-mentioned three rectifier types. Then % ripple factors for each rectifier type are calculated using newly derived equations and plotted versus the newly introduced Normalized Time Constant (NTC). Besides, considering the peak supply voltage as the base voltage, the Per Unit (p.u.) output average voltage and rms ripple voltage for each of the rectifier circuits are computed and plotted versus NTC. These graphs will be normalized graphs since the output values of these graphs have turned into independent of both supply voltage amplitude and supply frequency. Normalized graphs are set up only once for each type of the rectifier circuit. Then, and for a pre-selected ripple factor value, the corresponding NTC value is obtained by straightforward reading from the graphs set up between the % ripple factor and NTC. Once the NTC value has been acquired, using the formula of NTC leads to finding the capacitor value required for the pre-selected ripple factor with one simple step calculation. Furthermore, the p.u. values of the average output voltage and rms ripple voltage values that correspond to the same NTC value are obtained by reading them from the set-up graphs directly. Finally, the efficiency of the proposed method is demonstrated through design examples for each type of rectifier circuit. The three design examples highlight how the output performance values can be obtained easily, accurately and swiftly. Furthermore, the viability of the graphical approach is verified by the experimental results which demonstrate the suitability of the derived equations in the proposed method. [ABSTRACT FROM AUTHOR]

First-order allpass filters are analog filters with a unit magnitude response, but they change the phase shift between input and output signals at various frequencies. This paper presents the transadmittance-mode first-order allpass filters based on the modified current-controlled current differencing transconductance amplifier (M-CCCDTA). The proposed filters utilize a single M-CCCDTA and a grounded capacitor with no external resistors, making them well suited for implementation in an integrated circuit. The gain and phase response of the proposed filters can be adjusted electronically and separately. Also, the high output impedance of the proposed filters at both the input voltage node and the output current node makes cascading easy without the need for buffer devices. A quadrature sinusoidal oscillator based on the proposed first-order allpass filter has been designed as an example of an application. The PSpice simulation and actual experiments are utilized to validate the functionality of the proposed filters. The simulation and experimental results are consistent with the idea of anticipation. [ABSTRACT FROM AUTHOR]

In this paper, a differential-input plus-type differential voltage current conveyor-based first-order universal filter is designed. This voltage-mode filter uses a grounded capacitor. In addition, it can provide all the noninverting and inverting first-order universal filter responses. The circuit provides high common-mode rejection ratio of about 76.5 dB. Nevertheless, it needs a single matching problem and comprises two floating resistors. Quadrature oscillator (QO) design is obtained using this filter as an application example. The designed filter and QO circuits are simulated through the SPICE program, and some experimental studies are carried out using AD844 ICs to verify the theory. [ABSTRACT FROM AUTHOR]

A simple circuit based on modified extra-X second-generation current conveyor (MEXCCII), which is capable of realizing the following grounded immittance functions: a lossless capacitor, a lossy capacitor, a lossy inductor and a lossy frequency-dependent negative conductance, is introduced in this paper. The circuit employs one MEXCCII and three passive components. The use of single active block makes the circuit structure simpler. No component's matching constraint is needed in the proposed circuit. The nonideal study of the proposed grounded immittance circuit is also included. The circuit's performance is examined using 0.18- μ m technology-based PSPICE simulations. Experimental results which are performed using off-the-shelf integrated circuits (ICs) and bread board are also included. The proposed circuit is negligibly affected by the temperature variation and process variation. A single pole high-pass filter as an application of the realized lossy capacitor and a band-pass filter as an application of the realized lossy inductor are also presented in this paper. The realized filters offer the feature of ease of cascadability. [ABSTRACT FROM AUTHOR]

In this paper, an efficient frequency compensation method is investigated for a four-stage CMOS amplifier. The frequency compensation network includes two sets of capacitors at the differential block output. The proposed compensated amplifier is described symbolically to obtain the transfer function. Meanwhile, the proposed configuration is designed at the circuit level and is simulated via 0.18 μ m CMOS technology. Compared to the other existing methods, the proposed amplifier satisfies the figure of merits considerably. This stems from the fact that lower capacitor values are used to perform compensation, leading to lower die occupation, and reach boosted gain bandwidth products. Leveraging both the configuration and design procedure, a high-performance four-stage is presented in this paper. [ABSTRACT FROM AUTHOR]

This paper presents a background calibration method assisted with noise-shaping, for a 10-b bridged SAR ADC. It proposes calibrating the mismatches from the MSB capacitors using the LSBs. First-order noise-shaping has been employed to facilitate the calibration as well as the analog-to-digital conversion. Since noise-shaping is able to shape both the comparator input and quantization noise, it is expected to improve the calibration effects as well as the SNR, for the SAR ADC. Measurement results show, upon the proposed calibration, the SAR's INL and SNR are improved by 3 LSB and 9 dB, respectively, compared to when the noise shaping is off. Fabricated using a 55 nm CMOS MOMCAP technology and tested with a −2.5 dB sinewave input, the bridged SAR ADC achieves an SNR of 62.2 dB and an INL better than 1 LSB, when consuming a power of 7 2 μ W , at a supply voltage of 1.2 V and sampling frequency of 50 kHz. The ADC's active area is 3 0 0 × 3 8 0 μ m 2 . [ABSTRACT FROM AUTHOR]

Capacitor mismatch plays an important part in the spurious-free dynamic range (SFDR) performance of high-resolution successive approximation register (SAR) analog-to-digital converters (ADCs). This paper presents a symmetric group control dynamic element matching (SGCDEM) method aiming at enhancing SFDR of SAR ADCs applied in biomedical applications. The proposed scheme symmetrically divides the capacitor array into four sub-DACs, using quantization results corresponding to each sub-DAC as rotary control codes to symmetrically control the rotation of the capacitors. In order to improve the energy efficiency and save chip area, the proposed method replaces the pseudo-random number generator (PRNG) with quantization results of ADC as the rotary control code. Moreover, split rotator technology is applied in the proposed scheme to reduce the number of multiplexers (MUX) used in the rotator, which introduces a low logic depth. The proposed architecture has been implemented on a 12-bit SAR ADC model in MATLAB in order to verify its performances. After taking a standard deviation of 1% for the unit capacitance into consideration, this method achieves above 77.3 dB SFDR, enabling to correct the SFDR by more than 23.6 dB compared with the structure without DEM. [ABSTRACT FROM AUTHOR]

This paper presents a floating meminductor emulator circuit using a voltage differencing inverted buffered amplifier (VDIBA), current follower (CF), and two grounded capacitors. The parasitic resistance at the input terminal of the current follower has been utilized. The idea of implementing a meminductor emulator is simple and works on the principle of putting memory inside the active inductor circuit. A capacitor (memory element) has been charged by the current flowing through the active inductor circuit. Therefore, the proposed meminductor emulator can be viewed as an active inductor circuit having memory inside it. The proposed floating meminductor emulator works over a significant range of frequencies and satisfies all the characteristics of a meminductor. The meminductor emulator has been realized and simulated in the LTspice simulation tool using TSMC's 180-nm CMOS technology parameters. A chaotic oscillator circuit has been realized using the proposed meminductor emulator to verify its performance. The results obtained for the chaotic oscillators are found to be satisfactory and thus verify the performance of the proposed meminductor emulator. [ABSTRACT FROM AUTHOR]

This paper suggests a new operational transconductance amplifier (OTA) based electronically tunable transimpedance-mode first-order universal filter (FOUF). The suggested FOUF produces all-pass (AP), high-pass (HP) and low-pass (LP) filter responses simultaneously. It employs three OTAs, two grounded resistors and only one grounded capacitor. Owing to use of grounded passive elements, the suggested FOUF is suitable for integrated circuit implementation. It operates at low power supply voltages. Additionally, the resonance frequency of the suggested AP filter can be adjusted in a wide frequency range. However, the suggested FOUF consists of only one matching condition. Moreover, a sinusoidal quadrature oscillator (QO) application that is derived from the suggested FOUF topology is given. The suggested FOUF and its QO application are simulated by using 0.18- μ m TSMC technology parameters in the SPICE program to validate the presented theory. Finally, an experimental test is performed to demonstrate workability of the suggested AP filter. [ABSTRACT FROM AUTHOR]

A newly designed third-order mixed-mode orthogonally tuned quadrature oscillator, generating sinusoidal voltage and current waveforms, is introduced in this paper. The reported circuit is realized using two dual-X current conveyor transconductance amplifiers (DXCCTAs), two active MOS-based grounded resistors and three grounded capacitors. MOS-C realization of the proposed oscillator with all grounded capacitors is the best choice for modern integration. In this study, the ideal and non-ideal analyses and frequency stability aspect of the circuit are elucidated. The proposed third-order oscillator circuit has the advantages of orthogonally controllable frequency of oscillation & condition of oscillation, very good operating frequency (34.25 MHz) and low total harmonic distortion (within 1.8%). The theoretical analyses have been validated by both pre-layout and post-layout simulations using general process design kit 0.18 μ m technology and the results have been compared with relevant state-of-the-art works. Layout of the used active block, DXCCTA, is developed with Cadence Virtuoso that measures an area of 38 μ m × 2 1 μ m. [ABSTRACT FROM AUTHOR]

This paper deals with the realization of two first-order all-pass filter (APF) structures. First structure provides both inverting and non-inverting voltage-mode APF functions. This structure utilizes one differential difference dual- X second generation current conveyor (DD-DXCCII) without Z terminals, one active resistor and one capacitor only. The use of active resistor makes the proposed structure electronically tunable. Therefore, the attributes such as use of single DD-DXCCII without Z terminals and electronic tunability make the proposed structure simple and attractive. Conversely, second proposed circuit structure of first-order APF enriches the quality of this paper as both inverting and non-inverting APF functions in both voltage and current forms are available simultaneously within the same circuit structure. This circuit is realized with the help of one DD-DXCCII, three active resistors and one capacitor. The second circuit structure also enjoys gain controllability feature along with electronically tunable pole frequency that proves to be very essential in many of the applications. Additionally, the proposed APF structures provide the demanding feature of cascadability along with chip fabrication support. Furthermore, the performance of proposed circuits is less affected by the non-idealities and parasitic of DD-DXCCII. PSPICE simulations are provided to validate the theoretical presumptions. [ABSTRACT FROM AUTHOR]

This paper introduces four new resistorless, third-order, electronically tunable, quadrature sinusoidal oscillators using three operational transconductance amplifiers (OTAs) and three capacitors. The proposed third-order quadrature sinusoidal oscillators (TOQSOs) provide noninteracting control of the oscillation condition (OC) and oscillation frequency (OF) by changing the transconductance of different OTAs, to produce sustained oscillations and offer quadrature output voltages and currents. Two of the proposed quadrature oscillator circuits have capacitor control of OF, a feature, useful in capacitive transducers. The presented TOQSO structures have good frequency stability and exhibit low active and passive sensitivities. PSPICE simulations using CMOS OTAs along with hardware results (using off-the-shelf available OTA IC LM13700) have also been provided to confirm the workability of the presented circuits. [ABSTRACT FROM AUTHOR]

In this paper, a single-phase 13-level switching capacitor multilevel boost inverter (SCMLBI) with less switches and a voltage boost gain of six times is presented. The main focus of this work is to present a single DC source SCMLBI topology, which can provide an AC output voltage with low harmonic distortion by suitable sinusoidal pulse modulation (SPWM) technique. The given SCMLBI boost topology is designed to provide 13 output voltage levels utilizing a single DC source and 14 power electronic switches, and it includes intrinsic capacitor self-voltage balancing. The presented SCMLBI inverter does not require any magnetic elements like inductors which do not make the system complex in IC fabrication. In this work, the DC source is provided with a solar PV array with maximum power point tracking (MPPT) algorithm. The proposed SCMLBI topology provides an output voltage larger than the input voltage by appropriately converting the capacitors in series and parallel combinations. Sinusoidal PWM technique is used to control the switches in SCMLBI. A solar PV array of 100 W with incremental and conductance MPPT algorithm is used in this work. The verification of the presented SCMLBI topology is simulated on MATLAB software. Hardware results are also presented for the validation of SCMLBI topology. [ABSTRACT FROM AUTHOR]

This paper presents a low-distortion and low-power multi-stage noise-shaping (MASH) architecture Sigma-Delta (Σ Δ) modulator with double-sampling. The modulator uses a cascade of integrator feed-forward (CIFF) structure as a cascaded modulator in a MASH architecture. Since the CIFF structure provides a feedforward path from the input signal to the quantizer, the input signal is directly transmitted to the output without loop processing, relaxing the linearity requirement of the modulator, reducing performance requirements for the OTA and harmonic distortion. Double-sampling technique is adopted in the first integrator to double the sampling rate, improving the accuracy of the modulator without the increase of power consumption. In order to eliminate the influence of capacitor mismatch in the sampling network, a fully floating differential switched capacitor (SC) feedback digital-to-analog (DAC) is used in the integrator. The simulation results show that the Σ Δ modulator achieves 113 dB signal-to-noise and distortion ratio (SNDR) and the power consumption is 3.15 mW from a 5 V power supply. [ABSTRACT FROM AUTHOR]

This paper deals with the experimental realization of square/triangular wave generator using commercially available ICs. A prototype of extra-X second generation current conveyor and five passive components are used in the experimental setup. The proposed generator provides both square and triangular waveforms simultaneously in voltage-mode. The circuit enjoys the feature of independent controllability of oscillation frequency via grounded resistor/grounded capacitor. A range of oscillation frequency from 3 Hz to 250 Hz is easily achieved via variation in one of the grounded resistors for a fixed value of capacitor. Moreover, a range of oscillation frequency from 19.8 Hz to 19.2 kHz can be achieved through the variation in grounded capacitor. The experimental results show that the performance of the proposed generator is good at operating frequency as low as at 19.8 Hz and as high as 19.2 kHz. Therefore, the proposed circuit can operate well from extra-low-frequency range to very-low-frequency range. Furthermore, the maximum nonlinearity of oscillation frequency is found to be 4% only. [ABSTRACT FROM AUTHOR]

In this paper, a new mixed-mode first-order universal filter configuration is presented that employs three operational transconductance amplifiers (OTAs) and one grounded capacitor (eminently suitable for IC chip fabrication). All three first-order generic filter functions, namely low pass filter (LPF), high pass filter (HPF) and all pass filter (APF) in all the four possible modes, namely voltage mode (VM), current mode (CM), transresistance mode (TRM) and transconductance mode (TCM) can be realized. The proposed configuration offers high input impedance and high output impedance. The pole frequency of the filter can be controlled electronically by varying a single transconductance. Nonideal analysis of the proposed filter structure has also been carried out and the results have been compared with those obtained from ideal analysis. The performance of the presented filter configuration has been corroborated through PSPICE simulations as well as experimental results. The various simulation and experimental results validate the practical viability of the proposed configurations. [ABSTRACT FROM AUTHOR]

In this paper, two new first-order voltage-mode all-pass filters (APFs) are proposed. Each of the proposed APFs comprises a single modified DDCC-, and has high input impedance. The first and second APFs can provide first-order noninverting and inverting APF responses, respectively. As passive elements, the first APF comprises two grounded capacitors, and a floating resistor while the second one uses a grounded resistor, a floating resistor and a grounded capacitor. However, both of the APFs suffer from a matching problem. Two quadrature oscillators (QOs) obtained from the APFs are presented. Simulations of the APF and QO circuits are fulfilled via the SPICE program. Besides, diverse experiments for the APFs are made to verify the performances. [ABSTRACT FROM AUTHOR]

The realization of capacitance multiplier using the versatile active building block, namely voltage differencing differential difference amplifier (VDDDA) is presented in this paper. The realized capacitance multiplier is very simple consisting of one VDDDA, one MOS resistor ( R M) and one grounded capacitor which is attractive for integration. The multiplication factor (KC) of the realized circuit can be electronically controlled via the bias current ( I B) and control voltage ( V C) without the need of any matching condition of active and passive element. Moreover, the multiplication factor can be adjusted to be more or less than one. The performances of the presented capacitance multiplier are verified through Pspice simulation using CMOS VDDDA in 0.18 μ m TSMC technology with ± 0. 9 V power supplies. The multiplication factor is designed to be K C = 2 by choosing V C = 0. 8 5 V, I B = 5 0 μ A and C = 3 0 pF. The simulated multiplication factor is around 1.98. The simulated operational frequency range is around three decades (6.16 kHz–8.91 MHz). The performances of the proposed circuit are also verified by the experiment using VDDDA implemented from the commercial ICs, AD830 and LM13700 with ± 5 V power supplies. The experiment is conducted under the same multiplication factor ( K C = 2) as the simulation by choosing R M = 0. 2 7 k Ω (1% passive resistor), I B = 9 6. 2 μ A and C = 1 nF. The experimental multiplication factor is around 2.06. The experimental operational frequency range is around three decades (1 kHz–1.25 MHz). By adjusting the bias current from 17.67 μ A to 400 μ A, the experimental multiplication factor is controllable from 11.47 to 0.48. The percent deviation of the theoretical and experimental multiplication factor is lower than 5% when the value of bias current is greater than 39 μ A. These deviations stem from the effect of the parasitic capacitance and resistance in VDDDA. Moreover, the application example of the presented capacitance multiplier as the sinusoidal oscillator is presented. The performances of the presented oscillator verified via the experiment are well consistent with theoretical anticipation. [ABSTRACT FROM AUTHOR]

This paper describes a technique to detect blood cell levels based on the time-period modulation of a relaxation oscillator loaded with an Inter-Digitated Capacitor (IDC). A digital readout circuit has been proposed to measure the time-period difference between the two oscillators loaded with samples of healthy and (potentially) unhealthy blood. A prototype circuit was designed in 65-nm CMOS technology and post-layout simulations show 15.25-aF sensitivity. The total circuit occupies 2,184- μ m2 silicon area and consumes 216 μ A from a 1-V power supply. [ABSTRACT FROM AUTHOR]

This paper presents electrolytic capacitorless AC/DC LED driver. It adopts Boost–Buck topology, through modulation of the conduction time T on and the change of input current reference, to reduce the instantaneous input and output power difference, so a smaller film capacitor can be used instead of the electrolytic capacitor. Therefore, LED driver power life has been effectively improved. The Buck converter operates in the inductor current discontinuous conduction mode to achieve constant output current by controlling the peak current. The control IC is fabricated in TSMC 0.35- μ m 5-V/650-V CMOS/LDMOS process, and verified in a 72-V/150-mA circuit prototype. The test results show that when the range of input voltage is 175–264 Vac, the efficiency of the system is 83%, the voltage linear regulation is ± 1 %, the load regulation is ± 0. 5 %, and the electrolytic capacitor is replaced by 470-nF CBB capacitor under the condition that the power factor is above 0.7. Therefore, the design of the control chip in the LED driver has a very good application prospect. [ABSTRACT FROM AUTHOR]

An extra-X second-generation current conveyor (EXCCII) based first-order current-mode all-pass frequency selective structure is presented through this paper. A grounded resistor and a grounded capacitor are used as passive components. Single active element based realization directly correlates with the circuit's simplicity. The grounded nature of passive components is advantageous from IC fabrication aspects. The proposed circuit offers cascadability support through low input impedance and high output impedance. The ability of the presented idea to deliver the desired output without meeting any stringent component matching condition further simplifies the circuit's operation. Sensitivity performance of the proposed circuit is good. The quality performance at high frequency is another value addition to the circuit's signal processing attributes. Analyses showing the circuit's behavior under non-ideal conditions are also described in detail. Validation of theoretical analyses is supported by simulations carried out on PSPICE at 0.25 μ m technology. [ABSTRACT FROM AUTHOR]

This paper investigates a time-to-digital converter (TDC) that employs interpolation and time stretching techniques for digitizing the time interval between the rising edges of two input signals as well as increasing the resolution. In the proposed TDC, interpolation is performed based on a dual-slope conversion. The proposed converter eliminates the comparator offset voltage error and the comparator parasitic capacitor error compared with the TDCs that have been proposed previously. The features of the converter consist of the high accuracy and high resolution due to elimination of errors and usage of the analog interpolation structure. Moreover, it does not use gated delay lines in its structure and has the advantage of low sensitivity to the temperature, power supply and process (PVT) variations. For validation, the proposed TDC is designed in TSMC 0.18 μ m CMOS technology and simulated by Hspice simulator. The comparison between the theoretical and simulation results confirms the benefits of the proposed TDC operation. The results prove that it can be employed for high speed and resolution applications. [ABSTRACT FROM AUTHOR]

Simulation of inductors has been a very popular area of analog circuit research and the alternative choice for realizing inductor-based circuits in integrated circuits. In this paper, lossless, grounded and floating inductor topologies using current-controlled-current-feedback amplifier (CC-CFA) with single grounded capacitor are presented. The proposed topologies can be tuned electronically by changing the biasing current of the CC-CFA. Two topologies for grounded inductor simulator employ two CC-CFA and one grounded capacitor. One topology for floating inductor simulator employs three CC-CFA and one grounded capacitor. The performance of the grounded and floating inductor simulators are demonstrated on resonant circuits. The theoretical analysis is verified by PSPICE simulation results. [ABSTRACT FROM AUTHOR]

This paper presents an N-path filter with high out-of-band rejection using feed-forward technique. The structure utilizes two four-path filters, one as the main-path and the other as auxiliary-path, and two TIAs to increase the order of the filter from two to four. As a result of this, and due to using two series resistors in the main path, the out-of-band rejection is significantly improved. Analysis and simulations show that the series resistors can be chosen such that the NF degradation is below 2 dB while the out-of-band rejection is improved by about 20 dB. Therefore, the trade-off between the insertion-loss and out-of-band rejection is relaxed compared to conventional N-path filter. Also, it is shown that decreasing the size of baseband capacitors improves the NF of the filter. The effect of clock phase-noise on NF of the filter in the presence of strong out-of-band blocker is modeled and simulated. [ABSTRACT FROM AUTHOR]

In this paper, we presented Multi-Output Operational Transconductance Amplifier (MO-OTA)-based floating memristor emulator circuit. The designed memristor circuit has only one MO-OTA and one grounded capacitor which is attractive for an integrated circuit. It does not consist of any multiplication circuit block to obtain nonlinear behavior of memristor. It is difficult to obtain the hard-switching voltage–current relationship than the smooth-switching voltage–current relationship of memristor but we obtained hard-switching voltage–current characteristics using single floating memristor circuit. The complete memristor circuit is laid by using Cadence Environment using TSMC 0.18 μ m process parameters. The layout area of MO-OTA occupies an area of 34 μ m × 14 μ m. Its post-layout simulation results are given to demonstrate the performance of the presented memristor emulator in different operating frequencies, process corner and radical temperature changes. All post-layout simulations agree well with theoretical analyses. As application examples, different connections such as serial, parallel and single of memristor emulator are investigated to test its connectivity. [ABSTRACT FROM AUTHOR]

Due to the absence of commercially available fractional-order capacitors and inductors, their implementation can be performed using fractional-order differentiators and integrators, respectively, combined with a voltage-to-current conversion stage. The transfer function of fractional-order differentiators and integrators can be approximated through the utilization of appropriate integer-order transfer functions. In order to achieve that, the Continued Fraction Expansion as well as the Oustaloup’s approximations can be utilized. The accuracy, in terms of magnitude and phase response, of transfer functions of differentiators/integrators derived through the employment of the aforementioned approximations, is very important factor for achieving high performance approximation of the fractional-order elements. A comparative study of the accuracy offered by the Continued Fraction Expansion and the Oustaloup’s approximation is performed in this paper. As a next step, the corresponding implementations of the emulators of the fractional-order elements, derived using fundamental active cells such as operational amplifiers, operational transconductance amplifiers, current conveyors, and current feedback operational amplifiers realized in commercially available discrete-component IC form, are compared in terms of the most important performance characteristics. The most suitable of them are further compared using the OrCAD PSpice software. [ABSTRACT FROM AUTHOR]

This paper presents a new and simple frequency compensation scheme for multistage CMOS operational transconductance amplifiers (OTAs). In this work, by applying a differential block frequency compensation (DBFC) technique to a compensation network of three-stage OTA, the dominant pole is drastically improved independent from the DC gain path. The DBFC introduces amplified signal directly to the second-stage output through the compensation capacitor. The signal injection increases operational frequency range while just a single and small value capacitor is used as the Miller capacitor, which leads to considering the proposed configuration as a low die area occupation and high-speed amplifier. The simulation results show with the same capacitive load and power dissipation the gain bandwidth (GBW) frequency can be improved considerably compared to conventional nested Miller compensation. The presented circuit is simulated in a 0.18 μ m CMOS technology with a 1.8 V supply voltage. According to the results, the proposed circuit shows 102 dB, 105 MHz, and 343 μ W as the DC gain, GBW, and power consumption, respectively. [ABSTRACT FROM AUTHOR]

This paper presents six different meminductor emulator circuits based on operational amplifiers. Five circuits of meminductor emulators have been proposed using two operational amplifiers, one memristor, three resistors and one capacitor, whereas the sixth circuit uses two operational amplifiers, two memristors, one resistor and two capacitors. All circuits of the proposed meminductor emulators are very simple over most of the realizations of meminductor emulators in the literature. The behaviors of meminductor emulators are satisfactory over a wide range of frequencies. The proposed configurations of meminductor emulators have been simulated by the LTspice tool. The SPICE models of both operational amplifier (AD711) and memristor have been used for simulation. The workability of the proposed meminductor emulators has also been verified using the basic and well-known structure of operational amplifier. In addition, the pinched hysteresis loop obtained by the simulation results of meminductor emulator has been achieved by the experimental results as well. Chaotic oscillator has been designed using the proposed meminductor emulator to prove the worthiness of the design. [ABSTRACT FROM AUTHOR]

The paper presents a two-phase interleaved boost converter (IBC) providing higher step-up conversion ratio compared to the conventional IBC. The circuit consists of a crossly connected diode-capacitor cell which provides the extra boost up. The two identical capacitors of the cell are charged in parallel and discharged in series providing high voltage gain at considerably low duty ratio. Switching operations, ripple and average currents through inductors are analyzed in continuous conduction mode (CCM). Ripple in input current is also improved. The voltage stress across the semiconductor devices is less in the proposed converter. Also, boundary load condition is derived. Small-signal modeling is carried out and a control circuit is enabled in the voltage mode control framework. Power losses are analyzed and 96.53 % efficiency is achieved. Finally, the proposed converter is designed and implemented, and experimental results are provided. [ABSTRACT FROM AUTHOR]

In this paper, we present second generation current-controlled conveyor (CCCII)-based simple memristor circuit which exhibits a hard-switching voltage-current relationship. The proposed memristor circuit contains only single CCCII and single grounded capacitor that are attractive for the integrated circuit designers. The proposed memristor emulator has four main advantages: hard-switching behavior, not utilizing multiplier circuit, biasing current or voltage source (excluding DC current or voltage source), and being free of body effect for all transistors. Cadence Spectre Analog Environment with TSMC 0.18 μ m process parameters is used for all simulations. The memristive chip occupies only 81.85 μ m × 8 7. 7 6 μ m area. All simulation results are presented to demonstrate the performance of the proposed circuit by changing some parameters such as frequency, temperature, DC power supply voltages and process variations. Also, the robust performance of the proposed memristor is confirmed via Monte Carlo simulations. The simulation results for designed memristor are in accordance with theoretical memristive behavior. [ABSTRACT FROM AUTHOR]

Two new simple and effective voltage mode frequency selective structures that pass all signals are proposed and explored in this paper. The proposed structures use a single active element and three passive components in each. Dual-X second generation current conveyor (DXCCII) is employed as an active element along with two resistors and a capacitor as passive elements. The capacitor is grounded which goes well with the IC fabrication requirements. Both the structures offer low active and passive sensitivities. The presented structures also exhibit the feature of high input impedance. A comprehensive study of device non-idealities and parasitic is also included to highlight the non-ideal performance of the presented ideas. In addition, to prevent the use of passive resistors, resistor less realizations of proposed structures are also explored by replacing the passive resistors with MOS-based active resistors. A quadrature oscillator is also presented as one of the possible applications of the proposed frequency selective structures. Simulations results are in match with the theoretically analyzed performance. [ABSTRACT FROM AUTHOR]

This paper proposes an output-capacitorless low-dropout (LDO) regulator with ultra-low quiescent power. It applies an adaptive error amplifier to improve the bandwidth and transient response during heavy load, and a second gain stage to improve the stability during light load. Furthermore, an overshoot and undershoot reduction circuit is used to shorten the settling time when output load is changed. The LDO is fabricated in 0.18m CMOS process and occupies a chip area of 0.06mm2. The LDO is measured to output a stable voltage at 1.6V with a quiescent power of 1.8W. The experimental results also show a good transient response. [ABSTRACT FROM AUTHOR]

The memristor has drawn the worldwide attention since it has been discovered at HP laboratory on 1 May 2008. Since then many researchers are taking efforts to find its applications in various areas. In this paper, we study the filter characteristics of first-order low pass and high pass filters employing memristor with a capacitor. The paper provides a comparative analysis between low pass and high pass filter circuits that utilizing ordinary resistor or memristor with a capacitor. The theoretical analyzes are verified with SPICE simulation results using a memristor SPICE model with nonlinear dopant drift and MATLAB environment. The effect of change of the input frequency and initial resistance value of memristor on the cut-off frequencies of the presented low pass and high pass filters are investigated. The memory effect of memristor is represented by simulation results. [ABSTRACT FROM AUTHOR]

This paper approximates the behavior of low-pass Bessel filter in fractional domain using the Interior search algorithm (ISA). A detailed analysis has been done with sensitivity analysis, W-plane stability and absolute percentage error (gain and cut-off frequency) to study the low-pass fractional order filter. The work focuses on the analysis and design of fractional filter with two cases. In the first case, the design and simulation of (1 + α) order low-pass Bessel filter has been done using MATLAB for α value ranging from 0.1 to 0.9. SPICE simulation of 1.2, 1.5 and 1.9 order low-pass Bessel filter using fractional order capacitor of order α with Tow–Thomas biquad have been performed. In the second case, low-pass (α + β) order Bessel filter has been simulated and designed using MATLAB, where α and β are two fractional order elements of a different order. SPICE simulation for different values of α and β have been done using two fractional order capacitors of α and β order with Tow–Thomas biquad. [ABSTRACT FROM AUTHOR]

In non-isolated bidirectional DC-DC converters (NIBIDC), voltage output of buck/boost mode is incongruous at lower and higher end due to the existing gain. In this paper, a novel NIBIDC is designed in such a way that it enhances the gain in both buck and boost mode of operation. The proposed NIBIDC is employed with four power switches (MOSFET) with an anti-parallel diode embodied, four inductors and three capacitors used as passive elements. The current flow in parallel connected inductor improves the circuit competence. Voltage gain of NIBIDC in buck operation is lower than conventional cascaded bidirectional buck/boost converter (CCBBC) whereas the voltage gain is higher than CCBBC in boost mode. The switching stress is same while the efficiency of NIBIDC is more than CCBBC. The topology structure of the NIBIDC is simple and easy to control. The performance analysis under steady-state condition of the novel converter is carried out and a detailed comparison with CCBBC is done in connection to switching stress, converter efficiency and duty ratios to output power, etc. The operation details for proposed NIBIDC in both mode is verified/validated by experimenting with 20 V input for different duty ratios in charging and discharging state of a battery and the results infer to be identical with theoretical analysis. [ABSTRACT FROM AUTHOR]

A novel electronically adjustable square/triangular waveform generator has been introduced in this paper. The proposed circuit employs one active element, the multi-output current-controlled current conveyor transconductance amplifier, and one passive component grounded capacitor only. The resistorless realization of the presented generator provides a good advantage in terms of integrated circuit fabrication. In the offered circuit, the frequency and amplitude of the output square wave are electronically tunable by means of relevant bias currents. Additionally, the upper and lower threshold levels are electronically controllable by the respective bias current. On the contrary, electronically adjusting of the duty cycle of output waveform is possible via the external DC current. The generator circuit is simulated with TSMC 0.18 μ m technology parameters and SPICE. Moreover, the introduced circuit is implemented by using commercially available active devices and thus it is also verified experimentally. [ABSTRACT FROM AUTHOR]

In this paper, a new second-order current-mode universal filter using only two plus-type differential voltage current conveyors, three resistors and two grounded capacitors is proposed. The proposed circuit with two identical inputs and three outputs can simultaneously provide second-order high output impedance low-pass, band-pass and notch filter responses. Also, it can realize high-pass and all-pass filter responses with interconnection of relevant output currents. It can be easily tuned electronically. It can be operated properly at high frequencies. A number of simulations based on SPICE program and an experimental test are achieved in order to demonstrate the performance of the proposed filter. [ABSTRACT FROM AUTHOR]

In this paper, two new second-order voltage-mode universal filters are proposed. Both of the proposed filters use only two differential voltage current conveyors (DVCCs), four resistors and two grounded capacitors which are advantageous from integrated circuit technology point of view. They can simultaneously provide second-order low-pass, high-pass, band-pass, notch and all-pass responses. They offer orthogonal control of angular resonance frequency and quality factor. However, they have a single matching condition for only all-pass responses. A number of simulations based on SPICE program are accomplished in order to demonstrate the performance of both filters. [ABSTRACT FROM AUTHOR]

A high efficiency self-powered rectifier for piezoelectric (PE) energy harvesting systems is proposed. The rectifier in this paper increases the harvested power from the PE transducer by using two switches to reset the transducer capacitor when appropriate. The control circuit for the proposed rectifier is simple and does not require an external supply voltage. Furthermore, the passive diode of the conventional full-bridge (FB) rectifier is replaced by active diode to reduce the voltage drop along the conduction path and thereby increases the power extraction and conversion capability. Based on SMIC 0.18m standard CMOS technology, the simulation results show the voltage conversion efficiency can reach up to 98.9% and the maximum power efficiency is 93.1% when the input current source A in parallel with internal capacitor nF and internal resistor M. [ABSTRACT FROM AUTHOR]

A fully cascadable (i.e., low/high input impedance for current/voltage input signals and high/low output impedance for current/voltage output signals) mixed-mode (input and output signals can be voltage or current) universal filter biquad by using three differential difference current conveyors (DDCCs), three grounded resistors, and two grounded capacitors is presented in this paper. The proposed biquad can realize the inverting, non-inverting, and differential types universal filtering responses (lowpass, highpass, bandpass, notch, and allpass) from the voltage and current output terminals without changing the filter topology. The proposed circuit is suitable for cascading in all the four possible modes (i.e., voltage, current, transresistance, and transconductance modes). Moreover, the proposed mixed-mode biquad still enjoys (i) using only grounded passive components, (ii) no need of extra inverting and non-inverting amplifiers for special input signals, and (iii) low active and passive sensitivities. This paper also shows how analytical synthesis can be used to produce the proposed mixed-mode filter circuit. H-Spice simulation results confirm the theory. [ABSTRACT FROM AUTHOR]

In this paper, eight new Frequency Dependent Negative Resistance (FDNR) circuits using two current conveyors or inverting current conveyors or a combination of the two types are introduced. The proposed circuits are canonic and they use two grounded capacitors and one floating resistor. The generation of grounded capacitor minimum passive component oscillators from the FDNR circuits is also considered. It is found that two of the recently reported attractive oscillators are among the family of the generated oscillator circuits. Additional six new oscillator circuits based on the FDNR circuits are introduced in this paper. Spice simulation results using technology: SCN 05 feature size 0.5 μm, MOSIS Vendor: AGILENT to demonstrate the practicality of the proposed oscillators are included. [ABSTRACT FROM AUTHOR]

An ultra-low power consumption high-linearity switching scheme for successive approximation register (SAR) analog-to-digital converter (ADC) is presented with a mixed switching method. Based on the combination of C-2C dummy capacitors, the charge sharing technique and monotonic switching method, the proposed switching method achieves high-energy saving and high linearity. Compared with the conventional SAR ADC, the proposed method consumes no reset energy and achieves 98.9% less switching energy and 87.2% reduction in capacitor area. Moreover, the proposed scheme obtains good performance in linearity. Furthermore, the common-mode voltage variation of the proposed scheme is smaller than other published schemes, which is important for decreasing input-dependent offset of the comparator. [ABSTRACT FROM AUTHOR]

In this paper, a new active element namely Dual-X current conveyor differential input transconductance amplifier (DXCCDITA) is proposed. The DXCCDITA is utilized in designing four minimum component fully cascadable all pass filter (APF) structures. The designed all pass filters require only single active element and one/two passive elements for realization thus making them a minimum component implementation. Two among the four presented all pass structures require only a single capacitor for implementation. A scheme for realizing nth order all pass filter is also suggested and a fourth order voltage mode (VM) filter is developed from the proposed scheme. The effect of non-idealities on the proposed all pass filters is also studied. A simple oscillator is also developed using one of the all pass filter structure. The oscillator required only one DXCCDITA, two capacitors and one resistor for implementation. The DXCCDITA is implemented in 0.35 μ m TSMC CMOS technology parameters and tested in Tanner EDA. Sufficient numbers of simulations are provided to establish the functionality of all pass structures. The experimental results using commercially available integrated circuits (ICs) are also provided. [ABSTRACT FROM AUTHOR]

This paper proposes an area-efficient CMOS amplifier for neural recording applications. The proposed neural amplifier takes advantage of indirect negative feedback to realize a rather low upper − 3-dB cutoff frequency. As a result, the capacitance needed to realize the cutoff frequency is so small that can be easily implemented on-chip. Moreover, the proposed circuit also employs attenuators in the same feedback loop in order to further reduce the silicon area consumed by the capacitors and at the same time to increase the input impedance of the circuit. Designed based on a two-stage configuration, the amplifier provides tunable lower cutoff frequency and digitally-programmable upper cutoff frequency and voltage gain. The circuit is designed in a 0.18- μ m technology, and consumes 0.022 mm2 and 0.27 mm2 of chip areas for single- and eight-channel designs, respectively. Operated with a supply voltage of 1.8 V, power consumption of the proposed amplifier is 36.7 μ W with the simulated input-referred noise of 4 μ V rms over 1 Hz–10 kHz for each channel. The amplifier also provides an output swing of 0.95 Vpp with a total harmonic distortion of − 50 dB at the frequency of 1 kHz. [ABSTRACT FROM AUTHOR]

This paper presents a new floating memristor emulator (FME) consisting of only a single current backward transconductance amplifier (CBTA) as the active element and two grounded capacitors. The proposed FME-based on CBTA enjoys some advantages that include minimum active and passive elements without using an analog multiplier circuit and grounded passive elements which are attractive for the integrated circuit. In addition, excluding the DC power supply voltage, it does not use bias voltage and/or bias current. The designed memristor circuit provides incremental and decremental characteristics without changing circuit topology or using a switching mechanism and it is implemented with a minimum of circuit elements. All simulation results for the memristor emulator were obtained as expected when compared with fabricated memristors. [ABSTRACT FROM AUTHOR]

A novel switching scheme for successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. Based on the asymmetric capacitor array and splitted MSB capacitor, the proposed scheme achieves 99.09% and 93.41% reductions in the average switching energy and capacitor area, respectively, over the conventional scheme. Moreover, the proposed SAR ADC obtains a moderate linearity performance with max(INL-RMS) less than 0.112 LSB, max(DNL-RMS) less than 0.160 LSB and consumes zero reset energy. [ABSTRACT FROM AUTHOR]

From the nodal admittance matrix (NAM) expansion approach and 16 pathological patterns of the voltage differencing transconductance amplifier (VDTA), two different categories, namely sort A and sort B, of the quadrature sine-wave oscillators-employed VDTAs and grounded capacitors in the current mode are synthesized. In all, four quadrature sine-wave oscillators with two sets of quadrature current outputs are attained. Because canonic number is used for component quantity, the oscillators are appropriate to integrated circuit realization and also provide electronic, linear, and orthogonal adjustments between the oscillation criterion and frequency by means of tuning bias currents of the VDTAs. The paper-and-pencil and simulation analyses as well as experimental analysis have been carried out to check the utilized synthesis approach. [ABSTRACT FROM AUTHOR]

In this paper, an approach to estimate signal to noise ratio (SNR) and effective number of bits (ENOB) in nonideal multi-bit stages of pipelined analog to digital converters (ADCs) is presented. The most significant error sources in multistage ADCs are the capacitor mismatch and the finite and imprecise gain of amplifier. Output voltage of each stage in pipelined ADC is modeled by an ideal and a nonideal output, where nonideal output is the error due to circuit imperfections in each stage. Using an appropriate model, the SNR and ENOB due to circuit nonidealities and in terms of standard deviation of random errors are calculated. Simulation results show the accuracy of the analytical proposed approach in estimation of SNR and ENOB in multi-bit per stage pipelined converters. [ABSTRACT FROM AUTHOR]

The energy-harvesting radio frequency (RF) can be an attractive alternative energy capable of replacing all or some of the board batteries. The RF waves are present in several high frequencies (∼ GHz) and at low power (a few μ W). An energy-harvesting circuit designed must provide 1 V voltage at minimum that is able to operate an actuator or a sensor. The RF-DC rectifier is the main component of an energy-harvesting circuit. This paper presents a new design RF-DC rectifier circuit using the MOSFET transistors, the capacitors and the inductors. Our proposed circuit is a combination of an Inductor–Capacitor–Inductor–Capacitor (LCLC) serie-parallel resonant tank (SPRT) and rectifier cascade using the Dynamic threshold Voltage Cancellation (DVC) and the technique of the Internal threshold Voltage Cancellation (IVC). Our proposed circuit operates in dual frequencies f 1 = 2. 5 4 3 GHz and f 2 = 4 GHz with a low input power P in = 4. 3 7 μ W (− 2 3. 6 dbm) and P in = 5. 0 1 μ W (− 2 3 dbm), respectively. This circuit gives a Power Conversion Efficiency (PCE) of 56.9% and an output voltage V DC _ out = 1. 7 2 7 V for the frequency 2.543 GHz and a PCE of 62.6% and an output voltage V DC _ out = 1. 7 7 1 V for the frequency 4 GHz. The pre-layout simulations were performed using the Advanced Design System (ADS) and the technology used is CMOS 0.18 μ m from TSMC. The simulations were performed on the proposed circuit composed by three stages. [ABSTRACT FROM AUTHOR]