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Differentially 4-uniform permutations onwith high nonlinearity are often chosen as substitution boxes in block ciphers. Recently, Quet al.used the powerful switching method to construct permutations with low differential uniformity from the inverse function [Quet al., Constructing differentially 4-uniform permutations over via the switching method, IEEE Trans. Inform. Theory 59(7) (2013), pp. 4675–4686, Quet al., More constructions of differentially 4-uniform permutations on, Des. Codes Cryptogr. DOI 10.1007/s10623-014-0006-x] and proposed a sufficient but not necessary condition for these permutations to be differentially 4-uniform. In this paper, a sufficient and necessary condition is presented. We also give a compact estimation for the number of constructed differentially 4-uniform permutations. Comparing with those constructions in [11,12], the number of functions constructed here is much bigger. As an application, a new class of differentially 4-uniform permutations is constructed. The obtained functions in this paper may provide more choices for the design of substitution boxes. [ABSTRACT FROM AUTHOR]

The pay-TV industry seeks to extend its reach to portable display devices. At the same time, it seeks to ensure a horizontal market by making interoperable the Conditional Access Systems (CASs) employed to protect content. To achieve interoperability for such devices, this paper proposes a form of selective encryption for video that allows simultaneous distribution of a small percentage of video data on a per-CAS basis, allowing sharing of the unencrypted video between the CASs. The bitrate overhead for each additional CAS enabled is found to be on average 7.41 %, whereas the computational overhead amounts to no more than 40 ms for the benchmark sequences tested. Adaptation of CAS to transparent encryption of scalable video is also demonstrated in this paper. [ABSTRACT FROM AUTHOR]

Cloud computing is the present technology which is gaining greater attentions. Nowadays, among all the technologies that includes the network security, data protections, virtualization security, application integrity and identity management, the cloud is the most essential and key aspect. Among all the above mentioned issues, data protection is one of the most important security element because organizations cannot transfer their data to the remote machines as there is no guarantee of data protection by the cloud service providers. Many techniques are already available to protect the data in cloud. Though there are many number of techniques implemented to have focus on security of data but still some challenges persist. Cloud computing solves not only the computing problems but also caters loads of data with software updates etc. The user will be confident in utilising the cloud sources only if there is an appropriate collaboration between cloud client and cloud service provider. The most popular security techniques include SSL (Secure Socket Layer) Encryption, Algorithms like AES, Blowfish, DES, RSA, Cloud Computing, and Data Security. This paper mainly focus on how to analyse and evaluate the most important security encryption algorithms for data protection in cloud computing. Furthermore, this paper also discusses about some of the new security techniques for data protection which will be recommended in order to have improved security in cloud computing. [ABSTRACT FROM AUTHOR]

This paper presents an efficient approach to verifying higher-degree Galois-field (GF) arithmetic circuits. The proposed method describes GF arithmetic circuits using a mathematical graph-based representation and verifies them by a combination of algebraic transformations and a new verification method based on natural deduction for first-order predicate logic with equal sign. The natural deduction method can verify one type of higher-degree GF arithmetic circuit efficiently while the existing methods require an enormous amount of time, if they can verify them at all. In this paper, we first apply the proposed method to the design and verification of various Reed-Solomon (RS) code decoders. We confirm that the proposed method can verify RS decoders with higher-degree functions while the existing method needs a lot of time or fail. In particular, we show that the proposed method can be applied to practical decoders with 8-bit symbols, which are performed with up to 2,040-bit operands. We then demonstrate the design and verification of the Advanced Encryption Standard (AES) encryption and decryption processors. As a result, the proposed method successfully verifies the AES decryption datapath while an existing method fails. [ABSTRACT FROM AUTHOR]

A large number of studies are there for Advanced Encryption Standard (AES) fault attack analysis, but less for fault recognition. This paper presents a recognition method for single‐byte fault which is induced in the last three rounds of AES. Studying the differential characteristics of Sbox, the single byte fault induced in ninth round or tenth round will be identified respectively with 9.3 and 9.1 ciphertexts. For the fault induced in eighth round, the fault value can be obtained with 188.5 ciphertexts by analyzing the differential features of two Sboxes and MixColumns. As an auxiliary means for fault attacks, this method is used to realize the byte or bit level physical positioning of confidential data in the encryption chip, which is beneficial to reduce the blindness of the attacker's experiments and obtain the sensitive area of fault attack. [ABSTRACT FROM AUTHOR]

Symmetric cryptography is widely used in information exchange and storage. The advanced encryption standard (AES) is one of the most important symmetric ciphers. Based on the AES algorithm, this paper designs a new symmetric cipher, called unified algorithm. In the unified algorithm, the secret key is 256-bit long and the plaintext and cipher-text are both 128-bit long. The unified algorithm is composed of the modules and their improved versions of AES and a sequence-flip module, and has the same encryption and decryption processes. The simulation results show that the unified algorithm has the same processing speed as AES, and its single-thread running speed in Mathematica can reach up to 1.6570Mbps. Meanwhile, the unified algorithm has the same encryption intensity as AES, and its relative errors of system sensitivity index are less than 0.5%. The unified algorithm can be applied to various secure communication occasions to replace the AES algorithm. In addition, due to the encryption and decryption sharing the same module, the unified algorithm can save the hardware resources and simplify the secure communication protocol effectively. [ABSTRACT FROM AUTHOR]

This paper proposes an image encryption scheme based on a discrete-time alternating quantum walk (AQW) and the advanced encryption standard (AES). We use quantum properties to improve the AES algorithm, which uses a keystream generator related to AQW parameters to generate a probability distribution matrix. Some singular values of the matrix are extracted as the key to the AES algorithm. The Rcon of the AES algorithm is replaced with the elements of the probability distribution matrix. Then, the ascending order of the size of the clone probability distribution matrix scrambles the mapping rules of the S-box and ShiftRow transformations in the AES algorithm. The algorithm uses a probability distribution matrix and plaintext XOR operation to complete the preprocessing and uses the modified AES algorithm to complete the encryption process. The technology is based on simulation verification, including pixel correlation, histograms, differential attacks, noise attacks, information entropy, key sensitivity, and space. The results demonstrate a remarkable encryption effect. Compared with other improved AES algorithms, this algorithm has the advantages of the original AES algorithm and improves the ability to resist correlation attacks. [ABSTRACT FROM AUTHOR]

Healthcare big data (HBD) allows medical stakeholders to analyze, access, retrieve personal and electronic health records (EHR) of patients. Mostly, the records are stored on healthcare cloud and application (HCA) servers, and thus, are subjected to end-user latency, extensive computations, single-point failures, and security and privacy risks. A joint solution is required to address the issues of responsive analytics, coupled with high data ingestion in HBD and secure EHR access. Motivated from the research gaps, the paper proposes a scheme, that integrates blockchain (BC)-based confidentiality-privacy (CP) preserving scheme, CP-BDHCA, that operates in two phases. In the first phase, elliptic curve cryptographic (ECC)-based digital signature framework, HCA-ECC is proposed to establish a session key for secure communication among different healthcare entities. Then, in the second phase, a two-step authentication framework is proposed that integrates Rivest-Shamir-Adleman (RSA) and advanced encryption standard (AES), named as HCA-RSAE that safeguards the ecosystem against possible attack vectors. CP-BDAHCA is compared against existing HCA cloud applications in terms of parameters like response time, average delay, transaction and signing costs, signing and verifying of mined blocks, and resistance to DoS and DDoS attacks. We consider 10 BC nodes and create a real-world customized dataset to be used with SEER dataset. The dataset has 30,000 patient profiles, with 1000 clinical accounts. Based on the combined dataset the proposed scheme outperforms traditional schemes like AI4SAFE, TEE, Secret, and IIoTEED, with a lower response time. For example, the scheme has a very less response time of 300 ms in DDoS. The average signing cost of mined BC transactions is 3,34 seconds, and for 205 transactions, has a signing delay of 1405 ms, with improved accuracy of $\approx$ 12% than conventional state-of-the-art approaches. [ABSTRACT FROM AUTHOR]

Face recognition is playing an increasingly important role in present society, and suffers from the privacy leakage in plaintext. Therefore, a recognition system based on homomorphic encryption that supports privacy preservation is designed and implemented in this paper. This system uses the CKKS algorithm in the SEAL library, latest homomorphic encryption achievement, to encrypt the normalized face feature vectors, and uses the FaceNet neural network to learn on the image's ciphertext to achieve face classification. Finally, face recognition in ciphertext is accomplished. After been tested, the whole process of extracting feature vectors and encrypting a face image takes only about 1.712s in the developed system. The average time to compare a group of images in ciphertext is about 2.06s, and a group of images can be effectively recognized within 30 degrees of face bias, with a recognition accuracy of 96.71%. Compared to the face recognition scheme based on the Advanced Encryption Standard encryption algorithm in ciphertext proposed by Wang et al. in 2019, our scheme improves the recognition accuracy by 4.21%. Compared to the image recognition scheme based on the Elliptical encryption algorithm in ciphertext proposed by Kumar S et al. in 2018, the total spent time in our system is decreased by 76.2%. Therefore, our scheme has better operational efficiency and practical value while ensuring the users' personal privacy. Compared to the face recognition systems in plaintext presented in recent years, our scheme has almost the same level on recognition accuracy and time efficiency. [ABSTRACT FROM AUTHOR]

As CMOS(Complementary Metal Oxide Semiconductor) technology reaches its scaling threshold, evolving non-volatile memory approaches are becoming a hopeful substitutes to Dynamic RAM (i.e.) DRAM because of the low leakage power and improved scalability. Nonetheless, a new security flaw concerns the non-volatile central memory system. An intruder can easily access confidential memory records, as the non-volatility cause's knowledge to be stored even after the electricity is off for a long time. While memory encryption in real-time is an efficient way for dealing with this vulnerability in memory accesses along with an exclusive Advanced Encryption Standard (AES) engine, runtime performance and overhead energy are involved. The proposed work is to combine the AES key and the ECC key alternately for encryption and decryption and hence, a quick and efficient application of AES in memory (AESIM) was proposed in the paper to encrypt the either a part of the memory or the entire only if it is needed. Instead of counting additional processing elements to the cost-sensitive memory, the intrinsic logic operating capability of NVM was utilized to employ the proposed AESIM technique. We take advantage of the assistances provided by the in-memory storage design (huge internal bandwidth and dramatic reduction in movement of data) to overcome the complexities of the bandwidth concentrated encryption method. S-box is utilized along with AESIM methodology for performing the encryption process and then the counter action of decryption is performed by the inverse S-box which is employed with the AESIM. By embracing the memory's massive parallelism, AESIM outperforms current methods with higher performance yet lower consumption of energy. The efficiency of the proposed AESIM technique is calculated for both encryption and decryption process by measuring the minimum time used, the minimum time taken for the time before clock delivery, the average time required for operation after clock, the latency and the amount of logic separately for the proposed AESIM encryption and decryption technique. [ABSTRACT FROM AUTHOR]

The Advanced Encryption Standard (AES) is the most widely used symmetric cipher today. AES has an important place in cryptology. Finite field, also known as Galois Fields, are cornerstones for understanding any cryptography. This encryption method on AES is a method that uses polynomials on Galois fields. In this paper, we generalize the AES-like cryptology on 2x2 matrices.We redefine the elements of k-order Fibonacci polynomials sequences using a certain irreducible polynomial in our cryptology algorithm. So, this cryptology algorithm is called AES-like cryptology on the k-order Fibonacci polynomial matrix. [ABSTRACT FROM AUTHOR]

Purpose: The paper aims to develop a systematic approach to design, integrate, and implement a set of crypto cores in a system-on-chip SoC) environment for data security applications. The advanced encryption standard (AES) and PRESENT block ciphers are deployed together, leading to a common crypto chip for performing encryption and decryption operations. Design/methodology/approach: An integrated very large-scale integration (VLSI) architecture and its implementation for the AES and PRESENT ciphers is proposed. As per the choice, the architecture performs encryption or decryption operations for the selected cipher. Experimental results of the field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) implementations and related design analysis are provided. Findings: FPGA implementation of the architecture on Xilinx xc5vfx70t-1-ff1136 device consumes 19% slices, whereas the ASIC design is implemented in 180 nm complementary metal-oxide semiconductor ASIC technology that takes 1.0746 mm2 of standard cell area and consumes 14.26 mW of power at 50 MHz clock frequency. A secure audio application using the designed architecture on an open source SoC environment is also provided. A test methodology for validation of the designed chip using an FPGA-based platform and tools is discussed. Originality/value: The proposed architecture is compared with a set of existing hardware architectures for analyzing various design metrics such as latency, area, maximum operating frequency, power, and throughput. [ABSTRACT FROM AUTHOR]

The Internet of Things (IoT) has brought new ways for humans and machines to communicate with each other over the internet. Though sensor-driven devices have largely eased our everyday lives, most IoT infrastructures have been suffering from security challenges. Since the emergence of IoT, lightweight block ciphers have been a better option for intelligent and sensor-based applications. When public-key infrastructure dominates worldwide, the symmetric key encipherment such as Advanced Encryption Standard (AES) shows immense prospects to sit with the smart home IoT appliances. As investigated, chaos motivated logistic map shows enormous potential to secure IoT aligned real-time data communication. The unpredictability and randomness features of the logistic map in sync with chaos-based scheduling techniques can pave the way to build a particular dynamic key propagation technique for data confidentiality, availability and integrity. After being motivated by the security prospects of AES and chaos cryptography, the paper illustrates a key scheduling technique using a 3-dimensional S-box (substitution-box). The logistic map algorithm has been incorporated to enhance security. The proposed approach has applicability for lightweight IoT devices such as smart home appliances. The work determines how seeming chaos accelerates the desired key-initiation before message transmission. The proposed model is evaluated based on the key generation delay required for the smart-home sensor devices. [ABSTRACT FROM AUTHOR]

Side-channel analysis is a critical threat to cryptosystems on the Internet of Things and in relation to embedded devices, and appropriate side-channel countermeasure must be required for physical security. A combined countermeasure approach employing first-order masking and desynchronization simultaneously is a general and cost-efficient approach to counteracting side-channel analysis. With the development of side-channel countermeasures, there are plenty of advanced attacks introduced to defeat such countermeasures. At CARDIS 2013, Belgarric et al. first proposed time-frequency analysis, a promising attack regarding the complexity of computation and memory compared to other attacks, such as conventional second-order side-channel analysis after synchronization. Nevertheless, their time-frequency analysis seems to have lower performance than expected against some datasets protected by combined countermeasures. It is therefore required to study the factors that affect the performance of time-frequency analysis. In this paper, we investigate Belgarric et al.'s time-frequency analysis and conduct a mathematical analysis in regard to the preprocessing of frequency information for second-order side-channel analysis. Based on this analysis, we claim that zero-mean preprocessing enhances the performance of time-frequency analysis. We verify that our analysis is valid through experimental results from two datasets, which are different types of first-order masked Advanced Encryption Standard (AES) software implementations. The experimental results show that time-frequency analysis with zero-mean preprocessing seems to have an enhanced or complementary performance compared to the analysis without preprocessing. [ABSTRACT FROM AUTHOR]

Privacy-preserving techniques allow private information to be used without compromising privacy. Most encryption algorithms, such as the Advanced Encryption Standard (AES) algorithm, cannot perform computational operations on encrypted data without first applying the decryption process. Homomorphic encryption algorithms provide innovative solutions to support computations on encrypted data while preserving the content of private information. However, these algorithms have some limitations, such as computational cost as well as the need for modifications for each case study. In this paper, we present a comprehensive overview of various homomorphic encryption tools for Big Data analysis and their applications. We also discuss a security framework for Big Data analysis while preserving privacy using homomorphic encryption algorithms. We highlight the fundamental features and tradeoffs that should be considered when choosing the right approach for Big Data applications in practice. We then present a comparison of popular current homomorphic encryption tools with respect to these identified characteristics. We examine the implementation results of various homomorphic encryption toolkits and compare their performances. Finally, we highlight some important issues and research opportunities. We aim to anticipate how homomorphic encryption technology will be useful for secure Big Data processing, especially to improve the utility and performance of privacy-preserving machine learning. [ABSTRACT FROM AUTHOR]

There is a lack of fairness in market competition and disorder of order as a result of the lack of supervision. OCH (online car-hailing) driver accidents are also reported frequently, causing a slew of social and traffic safety issues. In this paper, we reconstruct the logical path of OCH platform data legal supervision in China's big data era. We propose a big data encryption algorithm based on data redundancy technology that combines the characteristics of the ECC (Elliptic Curve Cryptography) and AES (Advanced Encryption Standard) block cipher modes in terms of computing speed, parallelism, and security. The system can process large amounts of network data and detect distributed denial of service (DDOS) attacks in real time. The observed feature change trend charts before and after the attacks show significant differences, demonstrating that the proposed features can better distinguish normal traffic from abnormal traffic. [ABSTRACT FROM AUTHOR]

The Internet of Things (IoT) has changed our lives significantly. Although IoT provides new opportunities, security remains a key concern while providing various services. Existing research methodologies try to solve the security and time-consuming problem also exists. To solve those problems, this paper proposed a Hashed Advanced Encryption Standard (HAES) algorithm based efficient key management system for internet-based lightweight devices in IoT networks. The proposed method is mainly divided into two phases namely Data Owner (DO) and Data User (DU) phase. The DO phase consists of two processes namely authentication and secure data uploading. In authentication, the registration process consists of three phases namely KGC, SCC and DVC. In Key Generation Center (KGC), the device ID is converted into a 128-bit hash key using the Point on Curve based Fowler–Noll–Vo (PoC-FNV) algorithm. In DVC, the Data Access Policy (DAP) is created by using the selected attributes which is in turn selected by using the Chen Chaotic Chimp Optimization Algorithm (CCCOA). Thus, the authentication information is stored in the blockchain. If the person is an authorized, then the data is securely stored and uploaded into the cloud server using HAES. In the DU phase, the DU sends the data access request to the blockchain then the blockchain forwards the request to the DO, if the DO accepts the request then the DU obtains the data by using the DAP. Finally, the performance of the proposed method is compared with the existing methods and attains better result than the existing research methodologies. [ABSTRACT FROM AUTHOR]

In the era of multimedia technologies and rapidly growing multimedia contents, secured information transfer needs to be ensured through robust cryptography techniques. This paper presents a bio-key-generation scheme in the local environment to transfer multimedia content over vulnerable networks. To encrypt the images, one user has to ensure his/her authentication and further needs to provide a secret key for bio-key generation. Secret key aids to fetch biometric features for key formation and key expansion. Thus, the user receives an expanded key from the template database to perform encryption of a plain image. Once the cipher image is delivered to the network, the user has to repeat the same steps for decryption. This paper experiments the proposed bio-key-generation scheme with advanced encryption standard algorithm. This encryption strategy can also be used to encrypt confidential or personal images in various digital systems such as mobile phones, personal digital gadgets and so on. Various analyses ensure the robustness and the performance of the bio-key-based AES encryption scheme. Entropy, correlation coefficient, number of pixel change rate and unified average changing intensity are evaluated to ensure the effectiveness of the proposed method over other key-based encryption techniques. [ABSTRACT FROM AUTHOR]

Non-linear substitution is the essential step in the most popular Advanced Encryption Standard symmetric-key cryptosystem. Designing substitution boxes (S-boxes) with good quality solution and execution time efficiency are the significant challenges for the researchers for eliminating vulnerable attacks due to the static behavior of S-box. The main aim of this paper is to design a dynamic S-box for attaining the properties of high non-linearity and low autocorrelation. In this paper, a dynamic sub-key dependent S-box design is proposed to overcome the drawbacks of static S-box. The dynamic sub-key is generated based on the data block, so the proposed system is mostly depend on the data to provide more secure against the intruder. The proposed system generate a strong S-box with the good quality solutions and high efficiency in the execution time. The mapping of the non-linear initial S-box with the final sub-key generated S-box based on the cat swarm optimization function, so that the final S-box design is obtained as high non-linearity and low autocorrelation. The simulation performance is analyzed in in terms of solution quality and execution time compared with other relevant approaches. [ABSTRACT FROM AUTHOR]

GOST-R 34.11-94 is a Russian standard cryptographic hash function that was introduced in 1994 by the Russian Federal Agency for the purposes of information processing, information security, and digital signature. Mendel et al. (2008) and Courtois and Mourouzis (2011) found attacks on the compression function of the GOST-R structure that were basically weaknesses of the GOST-R block cipher (GOST 28147–89, 1989). Hence in 2012, it was updated to GOST-R 34.11-2012, which replaced the older one for all its applications from January 2013. GOST-R 34.11-2012 is based on a modified Merkle-Damgård construction. Here we present a modified version of GOST-R 34.11-2012 (Modified GOST-R (MGR) hash). The design of the MGR hash is based on wide-pipe construction, which is also a modified Merkle-Damgård construction. MGR is much more secure as well as three times faster than GOST-R 34.11-2012. Advanced Encryption Standard (AES)-like block ciphers have been used in designing the compression function of MGR because AES is one of the most efficient and secure block ciphers and has been evaluated for more than 14 years. A detailed statistical analysis with a few other attacks on MGR is incorporated into this paper. [ABSTRACT FROM AUTHOR]

This paper demonstrates autotuning of the coefficients of the feedback loop of an inductive integrated voltage regulator (IVR) using an on-chip delay sensor. The proposed approach improves the effective performance of the digital core under variations in the on-die/package integrated passives and transistor process. A 130-nm CMOS test-chip is designed containing a multisampled 125-MHz IVR with a wirebond inductor, on-die capacitor, and all-digital proportional-integral-differential (PID) controller powering a parallel Advanced Encryption Standard (AES) engine. The autotuning is performed using a Vernier delay line based on-chip delay sensor and an all-digital tuning engine. The measurement results demonstrate up to 5.2% improvement in the maximum operating frequency of the AES core using performance-based autotuning. [ABSTRACT FROM AUTHOR]

With technology scaling, fault tolerance has become more essential for digital circuits. Some solutions, like all types of redundancies, have been proposed to increase the reliability of the systems. In this paper, we present a cost-aware algorithm to enhance the fault tolerance ability of combinational digital circuits. Proposed algorithm improves the circuit logical masking with minimum area overhead based on an improved version of genetic algorithm (GA). Given a set of potential gates that are more sensitive to fault occurrence, we first extract feasible functional redundant, ffr, between the source nodes and the potential gates' outputs that their improvement on logical masking be more than a pre-defined threshold and hold them in a library, Masking_Lib. Then, we have to find a set of minimum number of potential gates as a target to add appropriate ffr, so that the maximum improvement on logical masking with minimum area overhead is achieved. Since, finding a set of potential gates with their suitable ffrs to meet these objectives is an NP-hard problem, we formulize this, as an optimization problem and solve using GA. We introduce an efficient chromosome representation and an adaptive objective function along with the basic GA operators. Besides, we integrate an assimilation operator with GA in order to enhance its searching ability. Our approach is applied to composite field substitution box implementation (S-box) that forms the core building block of any hardware implementation of the Advanced Encryption Standard algorithm. The simulation and synthesis results have been reported to show the effectiveness of our approach. Through these results, it has been shown that our proposed algorithm provides reliable digital circuits based on different level of logical masking (from 25.58 to 52.15). [ABSTRACT FROM AUTHOR]

Cloud computing allows the users to store their data in its storage and use them whenever they need. While the data of user is traveling outside its physical infrastructure through Internet, it needs to use a very strong encryption to protect them against the hackers who attempt to steal or alter the data. Thus, the data security in transmission is so important. Most of the users send the data to cloud, but all the data do not have a high sensitivity. In this paper, K nearest neighbors algorithm is used to decide whether the data is normal sensitive or high sensitive, and then according to the level of sensitivity we proposed a framework to do data encryption. In order to ensure user authentication, we used one time password to authenticate the user, and for the data which belong to normal sensitivity level we have applied AES (advanced encryption standard)-192 algorithm. Finally, for the data which belong to high sensitivity level, AES-256 algorithm has been applied, and RSA (Rivest-Shamir-Adleman) algorithm is used to encrypt the key of AES 256, then we use hash-based massage authentication code to be attached in the end of message to ensure integrity and authenticity of message. [ABSTRACT FROM AUTHOR]

Protecting the contents of medical records is of paramount importance when it comes to preserving patients’ privacy. Most existing cryptographic-based solutions rely on traditional encryption algorithms having a multi-round structure, which introduces processing latency and requires increased resources. Medical images possess special characteristics compared to other types of images. The main goal of this paper is to leverage these characteristics to design and implement an efficient and secure encryption algorithm for such images. The proposed solution defines three variants of encryption algorithms: (a) full, (b) middle-full, and (c) selective. The full approach encrypts all sub-matrices of an image, while the middle-full variant is a middle solution between the selective and full algorithms and its goal is to just hide the type of the medical image. Selective encryption identifies a set of sub-matrices of an image according to a statistical average test, known as region of interest (ROI). In the three approaches, a high security level is ensured since each image is encrypted independently of the previous and next images. Also, all primitives of the proposed cipher, such as permutation and substitution, depend on a dynamic key. Furthermore, the encryption scheme is efficient since the proposed round function is lightweight and applied for only one round. This reduces the latency and the required resources as compared to traditional cryptographic schemes. The proposed approach is flexible as it can be applied in either selective, middle-full, or full mode. Also, the size of a sub-matrix is variable and can be changed according to the available memory size. Several security and performance tests are conducted to evaluate the effectiveness of the proposed solution. The results validate the robustness of the proposed scheme against almost all considered types of attacks and show an improvement in terms of latency and resources compared to current image-encryption schemes. Also, the results confirm the robustness of the proposed algorithm in protecting the contents of medical images. [ABSTRACT FROM AUTHOR]

Digital Steganography is the art of hiding secret messages behind an innocent looking digital media that do not raise suspicions. In this paper, a new proposed image realization steganography method is introduced which is a mapping-based method that hides in an unrevealed manner and without any change in the image cover file. The image cover is only used for referencing. The proposed method generates the cover-secret mapping that will realize the concealed secret message without embedding the real message. A mapping between the American Standard Code of Information Interchange (ASCII) codes of a secret message and an image is performed and the positions of the secret message in the image is noted in a position array. This reference positions are then sent to the receiver after first being compressed by Huffman algorithm and then encrypted using Advanced Encryption Standard with 128 bits key (AES-128). The position array and the cover image are transferred separately, so that the interception of any one file alone will not conceal any information. In addition, it has unlimited capacity as specific matching positions can be used more than once. Furthermore, the proposed method has a reduced size of position key and mapping table, hence having high-speed searching and matching compared to prevailing methods. Furthermore, several experimental tests have been applied to assess the efficiency and performance of the new proposed method to evaluate it according to the widely used metrics: Mean Squared Error (MSE) and Peak Signal to Noise Ratio (PSNR). From the security point of view, Structural Similarity Index Measure (SSIM) together with Histogram have been performed. Moreover, it is critiqued showing its pros and cons and further compared with existing state-of-the-art research. The experimental results verified the efficacy of the new proposed method. [ABSTRACT FROM AUTHOR]

Data security is an essential aspect of data communication and data storage. To provide high-level security against all kinds of unauthorized accesses, cryptographic algorithms have been applied to various fields such as medical and military applications. Advanced Encryption Standard (AES), a symmetric cryptographic algorithm, is acknowledged as the most secure algorithm for the cryptographic process globally. Several modifications have been made to the original architecture after it was proposed by two Belgian researchers, Joan Daemen and Vincent Rijment, at the third AES candidate Conference in 2000. The existing modifications aim to increase security and speed. This paper proposes an efficient pipelined architecture for the key expansion process, effectively reducing the propagation delay to generate the required subkeys. Along with the pipeline structure, the fork and join architecture is also used in the key expansion part of the AES architecture, and it significantly reduces the time taken to generate the required subkeys. The proposed architecture is simulated and implemented on Xilinx Virtex4 XC4VLX200 FPGA. The result indicates that the proposed architecture achieves an improvement of about 37% in throughput compared with the original architecture. Also, the proposed architecture can convert the given plain text to cipher with a minimal propagation delay. [ABSTRACT FROM AUTHOR]

Real-time multimedia applications are increasingly achieving success in the everyday world. Thereby, multimedia information relies on security to protect private life. The Advanced Encryption Standard (AES) has been designed to secure different applications. Yet, some limitations are given, making it inappropriate for secure video storation and transmission. The limitations are the time complexity, the multiple iterations, and the predefined substitution box. Thus, any user can use it to break the encryption. Moreover, the multiple iterations augment the need for CPU usage, and so the overall run time. Hence, it is necessary to modify the AES algorithm to make it more appropriate for securing video frames transmission over insecure channel. In this paper, an Improved AES (IAES) is put forward, which improves both diffusion and confusion in ciphered video. Our work consists in the following two main points: First, we propose to eliminate both shift-row and sub-byte transformations and replace them with a mix-row operation. This task reduces the run time, which presents a significant factor for real-time video transmission. Equally important, we propose to use the henon chaotic map in the key generation procedure, which provides more randomness. The Hash Algorithm SHA-3 is used to generate the initial conditions of the chaotic attractor. The video encryption procedure is verified with success, and the experimental results confirm that the novel algorithm combining chaos and IAES augments the entropy of the ciphered video by 15% and reduces the complexity time for both encryption and decryption compared to the standard one. Security analysis is successfully performed, and the results prove that our suggested technique provides the basics of cryptography with more correctness. The PRNG is tested by NIST 800–22 test suit, which indicates that it is suitable for secure image encryption. It provides a large key space of 2128 which resists the brute-force attack. All in all, the findings confirm that the novel security approach eliminates the limitation of the existing AES and provides a trade-off between speed and safety levels to secure video transmission. [ABSTRACT FROM AUTHOR]

IPv6 over Low Power Wireless Personal Area Network (6LoWPAN) provides IP connectivity to the highly constrained nodes in the Internet of Things (IoTs). 6LoWPAN allows nodes with limited battery power and storage capacity to carry IPv6 datagrams over the lossy and error-prone radio links offered by the IEEE 802.15.4 standard, thus acting as an adoption layer between the IPv6 protocol and IEEE 802.15.4 network. The data link layer of IEEE 802.15.4 in 6LoWPAN is based on AES (Advanced Encryption Standard), but the 6LoWPAN standard lacks and has omitted the security and privacy requirements at higher layers. The sensor nodes in 6LoWPAN can join the network without requiring the authentication procedure. Therefore, from security perspectives, 6LoWPAN is vulnerable to many attacks such as replay attack, Man-in-the-Middle attack, Impersonation attack, and Modification attack. This paper proposes a secure and efficient cluster-based authentication scheme (CBAS) for highly constrained sensor nodes in 6LoWPAN. In this approach, sensor nodes are organized into a cluster and communicate with the central network through a dedicated sensor node. The main objective of CBAS is to provide efficient and authentic communication among the 6LoWPAN nodes. To ensure the low signaling overhead during the registration, authentication, and handover procedures, we also introduce lightweight and efficient registration, de-registration, initial authentication, and handover procedures, when a sensor node or group of sensor nodes join or leave a cluster. Our security analysis shows that the proposed CBAS approach protects against various security attacks, including Identity Confidentiality attack, Modification attack, Replay attack, Man-in-the-middle attack, and Impersonation attack. Our simulation experiments show that CBAS has reduced the registration delay by 11%, handoff authentication delay by 32%, and signaling cost by 37% compared to the SGMS (Secure Group Mobility Scheme) and LAMS (Light-Wight Authentication & Mobility Scheme). [ABSTRACT FROM AUTHOR]

Smart health surveillance technology has attracted wide attention between patients and professionals or specialists to provide early detection of critical abnormal situations without the need to be in direct contact with the patient. This paper presents a secure smart monitoring portable multivital signal system based on Internet-of-Things (IoT) technology. The implemented system is designed to measure the key health parameters: heart rate (HR), blood oxygen saturation (SpO2), and body temperature, simultaneously. The captured physiological signals are processed and encrypted using the Advanced Encryption Standard (AES) algorithm before sending them to the cloud. An ESP8266 integrated unit is used for processing, encryption, and providing connectivity to the cloud over Wi-Fi. On the other side, trusted medical organization servers receive and decrypt the measurements and display the values on the monitoring dashboard for the authorized specialists. The proposed system measurements are compared with a number of commercial medical devices. Results demonstrate that the measurements of the proposed system are within the 95% confidence interval. Moreover, Root Mean Squared Error (RMSE), Mean Absolute Error (MAE), and Mean Relative Error (MRE) for the proposed system are calculated as 1.44, 1.12, and 0.012, respectively, for HR, 1.13, 0.92, and 0.009, respectively, for SpO2, and 0.13, 0.11, and 0.003, respectively, for body temperature. These results demonstrate the high accuracy and reliability of the proposed system. [ABSTRACT FROM AUTHOR]

This paper deals with the design of a true random number generator (TRNG) using the fingerprint as an entropy source and its implementation in substitution box (S-box) of Advanced Encryption Standard (AES). Considering fingerprint as a unique and random arrangement of minutiae, these minutiae points are used as the source of entropy. The proposed design utilizes fewer resources minimizing hardware redundancy and enhancing the level of randomness. This TRNG has been designed and validated using Artix-7 FPGA. The data rate, speed and latency have been obtained as 40 Mbps, 5 Mbps and 305 ns, respectively. The generated random bit stream had also been sampled and converted to a binary format in MATLAB and tested through the National Institute of Standards and Technology (NIST) 800.22 statistical suite for validation. The proposed TRNG design pass efficiency achieved is more than 95% for a sample size of 10 binary sequences. [ABSTRACT FROM AUTHOR]

In this paper, the authors presented a new symmetric block cipher, BSBC (Bassam Symmetric Block Cipher). BSBC is mostly the combination of the two standard symmetric block ciphers, DES (Data Encryption Standard) and AES (Advanced Encryption Standard), into a more powerful cipher. Indeed, for many years, DES has been the main standard for encryption, it is fast, easy to understand and simple to implement and well suited for hardware implementation. But most importantly, it uses the Feistel structure, which makes it a strong cipher. However, it is vulnerable to attacks like linear cryptanalysis, differential cryptanalysis, linear-differential cryptanalysis and rotational cryptanalysis. On the other hand, AES, which is the latest standard for symmetric block cipher, is robust against all these cryptanalysis attacks. The main drawback of AES is that its time, space and data complexity is quite high, which prohibits its implementation on smaller processors. Thus, the algorithm BSBC aims to include the strengths of both standards, while minimizing their disadvantages. That is, our algorithm is designed so as to withstand known cryptanalysis attacks while flexible enough to be implemented on small processors. In addition, the authors compared and contrasted the algorithm against the two standard for symmetric block encryption DES and AES with respect to Linear cryptanalysis, differential cryptanalysis and linear-differential cryptanalysis. A brief note on rotational cryptanalysis was also be provided. [ABSTRACT FROM AUTHOR]

This paper proposes novel secret key generation techniques using memristor devices. The approach depends on using the initial profile of a memristor as a master key. In addition, session keys are generated using the master key and other specified parameters. In contrast to existing memristor-based security approaches, the proposed development is cost effective and power efficient since the operation can be achieved with a single device rather than a crossbar structure. An algorithm is suggested and demonstrated using physics based Matlab model. It is shown that the generated keys can have dynamic size which provides perfect security. Moreover, the proposed encryption and decryption technique using the memristor based generated keys outperforms Triple Data Encryption Standard (3DES) and Advanced Encryption Standard (AES) in terms of processing time. This paper is enriched by providing characterization results of a fabricated microscale Al/TiO2 Al memristor prototype in order to prove the concept of the proposed approach and study the impacts of process variations. The work proposed in this paper is a milestone towards System On Chip (SOC) memristor based security. [ABSTRACT FROM AUTHOR]

This paper describes the experiments that have been conducted to determine the optimal implementation method for AES (Advanced Encryption Standard) data encryption in a ZigBee network in terms of energy consumption. Four possible scenarios have been considered. The first one is a freely available AES-cryptographic algorithm on the processor which controls the ZigBee nodes. The second also involves the processor but is based on a proprietary, highly optimized algorithm. The other methods are based on hardware implementations. Whereas the third option is based on a cryptographic block, embedded in the ZigBee node controller, the last solution utilizes an AES128-CBC-MAC hardware co-processor embedded on a Spartan 3A FPGA. The ZigBee modules in the network contain an 8-bit microcontroller which takes care of the ZigBee protocol stack--and the encryption calculations in all but the last case. All approaches are examined and compared. We show that the usage of a microcontroller with an on-board AES processor is the optimal design choice for a newhardware platform. An optimized software library gives the best results when extending an existing platform. This paper gives developers an idea of the amount of energy they can gain/lose by choosing one of the four solutions. [ABSTRACT FROM AUTHOR]

Scan chain-based attacks are side-channel attacks focusing on one of the most significant features of hardware test circuitry. A technique called Design for Testability (DfT) involves integrating certain testability components into a hardware design. However, this creates a side channel for cryptanalysis, providing crypto devices vulnerable to scan-based attacks. Advanced Encryption Standard (AES) has been proven as the most powerful and secure symmetric encryption algorithm announced by USA Government and it outperforms all other existing cryptographic algorithms. Furthermore, the on-chip implementation of private key algorithms like AES has faced scan-based side-channel attacks. With the aim of protecting the data for secure communication, a new hybrid pipelined AES algorithm with enhanced security features is implemented. This paper proposes testing an AES core with unpredictable response compaction and bit level-masking throughout the scan chain process. A bit-level scan flipflop focused on masking as a scan protection solution for secure testing. The experimental results show that the best security is provided by the randomized addition of masked scan flipflop through the scan chain and also provides minimal design difficulty and power expansion overhead with some negligible delay measures. Thus, the proposed technique outperforms the state-of-the-art LUT-based S-box and the composite sub-byte transformation model regarding throughput rate 2 times and 15 times respectively. And security measured in the avalanche effect for the sub-pipelined model has been increased up to 95 per cent with reduced computational complexity. Also, the proposed sub-pipelined S-box utilizing a composite field arithmetic scheme achieves 7 per cent area effectiveness and 2.5 times the hardware complexity compared to the LUT-based model. [ABSTRACT FROM AUTHOR]

This paper presents the design of a Built-in-self-Test (BIST) implemented Advanced Encryption Standard (AES) cryptoprocessor Application Specific Integrated Circuit (ASIC). AES has been proved as the strongest symmetric encryption algorithm declared by USA Govt. and it outperforms all other existing cryptographic algorithms. Its hardware implementation offers much higher speed and physical security than that of its software implementation. Due to this reason, a number of AES cryptoprocessor ASIC have been presented in the literature, but the problem of testability in the complex AES chip is not addressed yet. This research introduces a solution to the problem for the AES cryptoprocessor ASIC implementing mixed-mode BIST technique, a hybrid of pseudo-random and deterministic techniques. The BIST implemented ASIC is designed using IEEE industry standard Hardware Description Language(HDL). It has been simulated using Electronic Design Automation (EDA)tools for verification and validation using the input-output data from the National Institute of Standard and Technology (NIST) of the USA Govt. The simulation results show that the design is working as per desired functionalities in different modes of operation of the ASIC. The current research is compared with those of other researchers, and it shows that it is unique in terms of BIST implementation into the ASIC chip. [ABSTRACT FROM AUTHOR]

Cloud computing helps users to store and retrieve their data in the cloud online on an as-per-pay basis anytime, anywhere in the world. As a consequence, the security of data stored in the cloud serves as a key concern for cloud consumers due to ongoing hacking incidents in the cloud. Both cloud service providers (CSPs) and consumers face various attacks that pose a serious threat to both the organization and the user. Therefore, a robust intrusion detection system (IDS) needs to be configured to identify and avoid potential attacks in the cloud at an earlier stage. The state-of-the-art IDS system which used shallow machine learning techniques suffered from poor accuracy with a higher false alarm rate and higher response time. To overcome this problem, a hybrid semantic deep learning (HSDL) architecture is developed in this paper by integrating the long short-term memory (LSTM), convolutional neural network (CNN), and support vector machine (SVM) architectures. The semantic information present in the network traffic is identified using a semantic layer known as the Word2Vec embedding layer. The HSDL model classifies the intrusion present in the text along with its corresponding attack class. The normal text without any trace of intrusion is encrypted using an advanced encryption standard (AES) algorithm to enhance cloud storage security, and the optimal key with the largest key breaking time for the AES algorithm is selected using the crossover-based mine blast optimization algorithm (CMBA). The proposed HSDL scheme is evaluated and tested using two real-time intrusion detection benchmark datasets, namely NSL-KDD and UNSW-NB15. The proposed model achieves an accuracy of 99.98% for the NSL-KDD and 98.47% for the UNSW-NB15 dataset, respectively. The experimental and security analysis conducted proves the efficiency and robustness of the proposed scheme. [ABSTRACT FROM AUTHOR]

Security is a critical issue in cloud computing (CC) because attackers can fabricate data by creating, copying, or deleting data with no user authorization. Most of the existing techniques make use of password-based authentication for encrypting data. Password-based schemes suffer from several issues and can be easily compromised. This paper presents a new concept of hybrid metaheuristic optimization as an identity-based secure and optimal authentication (HMO-ISOA) scheme for CC environments. The HMOISOA technique makes use of iris and fingerprint biometrics. Initially, the HMO-ISOA technique involves a directional local ternary quantized extrema pattern-based feature extraction process to extract features from the iris and fingerprint. Next, the features are fed into the hybrid social spider using the dragon fly algorithm to determine the optimal solution. This optimal solution acts as a key for an advanced encryption standard to encrypt and decrypt the data. A central benefit of determining the optimal value in this way is that the intruder cannot determine this value. The attacker also cannot work out which specific part of the fingerprint and iris feature values are acted upon as a key for the AES technique. Finally, the encrypted data can be saved in the cloud using a cloud simulator. Experimental analysis was performed on five fingerprint and iris images for a man-in-the-middle attack. The simulation outcome validated that the presented HMO-ISOA model achieved better results compared with other existing methods. [ABSTRACT FROM AUTHOR]

In this modern era, communication plays an important role in a human's life. Also information security is a significant aspect of all types of communication. Now a day all the communications are carried out in wireless medium. It is necessary to transmit the confidential data in wireless media in a secure manner. Cryptography is a technique to protect the electronic data in a communication network. Efficient hardware architecture to implement the Advanced Encryption Standard (AES) algorithm for high throughput and less area is presented in this paper. In the proposed architecture the throughput is increased by using the Parallel Sub-Pipeline (PSP) architecture for the AES algorithm, the techniques like composite field arithmetic (CFA), on the fly key expansion and order change are combined in order to reduce the area. Also different combination like PSP plus on the fly, PSP plus CFA and PSP plus order change are explored in this research. Based on synthesis report and the throughput, it is suggested that the proposed PSP plus CFA plus On the fly plus Order change (PSP CO) produces reasonably high throughput and less area compared to other combination. The proposed PSP CO architecture is implemented in field programmable gate array. This implementation achieves a throughput of 52.29 Gbps at a frequency of 450.045 MHz on Xilinx Virtex XC6VLX75T device which is reported to be higher than all the other implementations in the literature survey. [ABSTRACT FROM AUTHOR]

Known plaintext attack is a common attack method in cryptographic attack. For ciphertext, only known part of the plaintext but unknown key, how to restore the rest of the plaintext is an important part of the known plaintext attack. This paper uses backpropagation neural networks to perform cryptanalysis on AES in an attempt to restore plaintext. The results show that the neural network can restore the entire byte with a probability of more than 40%, restoring more than half of the plaintext bytes with a probability of more than 63% and restoring more than half of the bytes above 89%. [ABSTRACT FROM AUTHOR]

Advanced Encryption Standard (AES) is a standard algorithm for block ciphers for providing security services. A number of variations of this algorithm are available in network security domain. In spite of the strong security features, this algorithm has been recently broken down by the cryptanalysis processes. Therefore, it is required to improve the security strength of this algorithm as AES is popular in commercial use. In this paper, we have shown the reasons of the loopholes in AES and also have provided a solution by using our Symmetric Random Function Generator (SRFG). The use of randomness in the key generation process in block cipher is novel in this domain. We have also compared our results with the original AES based upon some parameters such as nonlinearity, resiliency, balancedness, propagation characteristics, and immunity. The results show that our proposed version of AES is better in withstanding attacks. [ABSTRACT FROM AUTHOR]

Laser fault injection (LFI) attack on cryptographic processors is a serious threat to information security. This paper proposes a sense-and-react countermeasure against LFI. A distributed bulk-current sensor monitors the abnormal current conduction caused by laser irradiation to a silicon substrate. The single sensor occupies only 286 F2/Cell and it is distributed across the entire cryptographic core for 100% attack detection coverage. Upon detection of LFI attack, a flush code eraser prevents a leakage of faulty ciphertext by immediately shunting the core supply path within nano-second order. In addition, the core supply during the shunting is electrically isolated from the global supply line to prevent side-channel information leakage of intermediate faulty codes. A test chip was designed and fabricated in 0.18- $\mu \text{m}$ standard CMOS, integrating a 128-bit Advanced Encryption Standard (AES) cryptographic processor with the proposed countermeasures. A protected AES processor can disable LFI attack with only +28% layout area penalty compared to an unprotected core. [ABSTRACT FROM AUTHOR]

In this paper, we propose an energy-efficient reconfigurable platform for in-memory processing based on novel four-terminal spin Hall effect-driven domain wall motion devices that could be employed as both nonvolatile memory cell and in-memory logic unit. The proposed designs lead to unity of memory and logic. The device to system level simulation results show that, with 28% area increase in memory structure, the proposed in-memory processing platform achieves a write energy ~15.6 fJ/bit with 79% reduction compared to that of SOT-MRAM counterpart while keeping the identical 1 ns writing speed. In addition, the proposed in-memory logic scheme improves the operating energy by 61.3%, as compared with the recent nonvolatile in-memory logic designs. An extensive reliability analysis is also performed over the proposed circuits. We employ advanced encryption standard (AES) algorithm as a case study to elucidate the efficiency of the proposed platform at application level. Simulation results exhibit that the proposed platform can show up to 75.7% and 30.4% lower energy consumption compared to CMOS-ASIC and recent pipelined domain wall (DW) AES implementations, respectively. In addition, the AES energy-delay product can show 15.1% and 6.1% improvements compared to the DW-AES and CMOS-ASIC implementations, respectively. [ABSTRACT FROM AUTHOR]

Power analysis attacks (PAAs), a class of side-channel attacks based on power consumption measurements, are a major concern in the protection of secret data stored in cryptographic devices. In this paper, we introduce the secure double rate registers (SDRRs) as a register-transfer level (RTL) countermeasure to increase the security of cryptographic devices against PAAs. We exploit the SDRR in a conventional advanced encryption standard (AES)-128 architecture, improving the immunity of the cryptographic hardware to the state-of-the-art PAAs. In the AES-128 exploiting SDRR, the combinational path evaluates random data throughout the entire clock cycle, and the interleaved processing of random and real data ensures the protection of both combinational and sequential logics. Our technique does not require the duplication of the combinational path to process the random data, thus limiting area overhead, unlike previous RTL countermeasures. The proposed approach is validated by means of PAAs based on real measurements on a field-programmable gate array implementation and on a 65-nm CMOS prototype chip. The protected implementation shows a strongly reduced correlation coefficient for the correct key, and more than three orders of magnitude increase in the measurements to disclosure with respect to the unprotected AES-128. [ABSTRACT FROM AUTHOR]

Cloud computing has been developed to deliver IT services and so its security is important as well. This paper mainly focusses on two algorithms AES(Advanced Encryption Algorithm) and Blowfish algorithms. The main goal behind the design of the encryption algorithm is to provide security against the unauthorized data access. The main purpose of this paper is to provide idea of the combination of these two algorithms to provide double security to the data stored inside the cloud. Performance and cost of implementation are also major concerns. This paper is only the initial work on the proposal without any technical details and data analysis. [ABSTRACT FROM AUTHOR]

Summary: In this paper, a lightweight 8‐bit S‐box and combined S‐box/S‐box−1 with a security level equal to the AES S‐box is presented. From the viewpoint of hardware implementation, the S‐box has better hardware and timing complexities. The structure is based on an efficient field inversion and a low‐cost affine transformation. The field multiplications over 픽24 in the inversion circuit are implemented by resource sharing to reduces logic gates. The original equations of the inversion over 픽24 are optimally rewritten. In addition, a part of the S‐box called Part1 is optimized for reducing area and delay. This part consists of two addition operations, one multiplication, field squaring, and multiplication by constant λ, which all operations are over 픽24. The subblocks of Part1 are combined to generate a unified structure. Security analysis of the proposed S‐box showed that the structure has a security level equal to the Advanced Encryption Standard (AES) S‐box. The implementation results in 180‐ and 65‐nm Complementary metal oxide semiconductor (CMOS) technologies show the proposed S‐box and combined S‐box/S‐box−1 are comparable in terms of area, delay, and area × delay than most of the famous S‐boxes. The proposed S‐box is a high‐secure and area‐efficient S‐box as a good candidate for block ciphers. [ABSTRACT FROM AUTHOR]

Software defined network suggests centralizing network knowledge in one network portion by separating the routing (control plane) mechanism from the transmission network packet operation (data plane). The control plane is composed of one, two or more controllers which are considered as softwaredefined networking (SDN) network brain where the real intelligence is incorporated. The process of separating the control unit from the data unit led to a problem related to poor security of data sent in the network, so solutions to these problems had to be found. In this paper, address this problem by implementing robust algorithms to encrypt information, based on advanced encryption standard (AES), Rivest-Shamir-Adleman (RSA), and hybrid encryption algorithms to guarantee data protection and authenticity. The results showed that the hybrid coding method is better in terms of security and improved time (faster than RSA alone) by applying several scenarios in the SDN network to a set of encrypted files. [ABSTRACT FROM AUTHOR]

Authentication of encrypted speeches is a technique that can judge the integrity of encrypted speech in cloud computing, even the encrypted speeches have been subjected to common signal processing operations. In this paper, a novel and effective authentication scheme for encrypted speech is proposed. At first, the host speech signal is first scrambled and encrypted by Advanced Encryption Standard (AES). Then, Integer Wavelet Transform (IWT) is performed to obtain the approximation coefficients and the detail coefficients. At last, Non-negative Matrix Factorization (NMF) is employed to generate perceptual hashing, which is embedded into the encrypted speech by differential expansion. In authentication section, the tampered region of encrypted speech is located by comparing the reconstructed perceptual hashing with the extracted perceptual hashing version. Extensive experiments are carried out, which demonstrate that the proposed scheme is not only sensitive to malicious tampering of encrypted speech files, but also robust to tolerate common signal processing operations. The comparison shows that our algorithm performs better than the existing methods on Bit Error Rate (BER) values. [ABSTRACT FROM AUTHOR]

Unmanned Aerial Vehicle (UAV) or drone, is an evolving technology in today's market with an enormous number of applications. Mini UAVs are developed in order to compensate the performance constraints imposed by larger UAVs during emergency situations. Multiple mini autonomous UAVs require communication and coordination for ubiquitous coverage and relaying during deployment. Multi-UAV coordination or swarm optimization is required for reliable connectivity among UAVs, due to its high mobility and dynamic topology. In this paper, a Secured UAV (S-UAV) model is proposed which takes the location of the UAVs as inputs to form a Wireless Mesh Network (WMN) among multiple drones with the help of a centralized controller. After WMN formation, efficient communication takes place using A* search, an intelligent algorithm that finds the shortest communication path among UAVs. Further, the S-UAV model utilizes cryptographic techniques such as Advanced Encryption Standard (AES) and Blowfish to overcome the security attacks efficiently. Simulation results show that the S-UAV model offers higher throughput, reduced power consumption and guaranteed message transmission with reduced encryption and decryption time. [ABSTRACT FROM AUTHOR]