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Transformer model architectures have recently received great interest in natural language, machine translation, and computer vision, where attention mechanisms are their building blocks. However, the attention mechanism is expensive because of its intensive matrix computations and complicated data flow. The existing hardware architecture has some disadvantages for the computing structure of attention, such as in- flexibility and low efficiency. Most of the existing papers accelerate attention by reducing the amount of computation through various pruning algorithms, which will affect the results to a certain extent with different sparsity. This paper proposes the hardware accelerator for the multi-head attention (MHA) on field-programmable gate arrays (FPGAs) with reconfigurable architecture, efficient systolic array, and hardware-friendly radix-2 softmax. We propose a novel method called Four inputs Processing Element (FPE) to double the computation rate of the data-aware systolic array (SA) and make it efficient and load balance. Especially, the computation framework is well designed to ensure the utilization of SA efficiently. Our design is evaluated on a Xilinx Alveo U250 card, and the proposed architecture achieves 51.3x, 17.3x improvement in latency, and 54.4x, 17.9x energy savings compared to CPU and GPU. [ABSTRACT FROM AUTHOR]

Both kraft lignin phenol-formaldehyde (KLPF) and phenol-formaldehyde (PF) resins were synthesized and the curing kinetics of the resins was determined using thermal analysis data. The kinetic parameters were predicted using two popular model-free kinetic (MFK) methods: the advanced form of the Vyazovkin method and the Kissinger–Akahira–Sunose method. From the experimental and predicted values, the rate of kraft lignin phenol-formaldehyde curing was less compared to the phenol-formaldehyde resin. To increase the cure rate different cure additives were tried. Among these, only potassium carbonate (KC) showed a positive effect: An increase in additive concentration to 4% reduced the curing time to almost 50% as compared to pure KLPF resin at 160°C. Comparison of the predicted values from MFK calculations with isothermal experimental data showed that both MFK approaches were suitable to predict the curing characteristics. [ABSTRACT FROM AUTHOR]

With the recent advancements in high-performance computing, convolutional neural networks (CNNs) have achieved remarkable success in various vision tasks. However, along with improvements in model accuracy, the size and computational complexity of the models have significantly increased with the increasing number of parameters. Although graphics processing unit (GPU) platforms equipped with high-performance memory and specialized in parallel processing are commonly used for CNN processing, the significant power consumption presents challenges in their utilization on edge devices. To address these issues, research is underway to design CNN models using field-programmable gate arrays (FPGAs) as accelerators. FPGAs provide a high level of flexibility, allowing efficient optimization of convolution operations, which account for a significant portion of the CNN computations. Additionally, FPGAs are known for their low power consumption compared to GPUs, making them a promising energy-efficient platform. In this paper, we review and summarize various approaches and techniques related to the design of FPGA-based CNN accelerators. Specifically, to comprehensively study CNN accelerators, we investigate the advantages and disadvantages of various methods for optimizing CNN accelerators and previously designed efficient accelerator architectures. We expect this paper to serve as an important guideline for future hardware research in artificial intelligence. [ABSTRACT FROM AUTHOR]

Bit-serial neural network accelerators address the growing need for compact and energy-efficient deep learning tools. Traditional neural network accelerators, while effective, often grapple with issues of size, power consumption, and versatility in handling a variety of computational tasks. To counter these challenges, this paper introduces an approach that hinges on the integration of bit-serial processing with advanced dataflow techniques and architectural optimizations. Central to this approach is a column-buffering (CB) dataflow, which significantly reduces access and movement requirements for the input feature map (IFM), thereby enhancing efficiency. Moreover, a simplified quantization process effectively eliminates biases, streamlining the overall computation process. Furthermore, this paper presents a meticulously designed LeNet-5 accelerator leveraging a convolutional layer processing element array (CL PEA) architecture incorporating an improved bit-serial multiply–accumulate unit (MAC). Empirically, our work demonstrates superior performance in terms of frequency, chip area, and power consumption compared to current state-of-the-art ASIC designs. Specifically, our design utilizes fewer hardware resources to implement a complete accelerator, achieving a high performance of 7.87 GOPS on a Xilinx Kintex-7 FPGA with a brief processing time of 284.13 μs. The results affirm that our design is exceptionally suited for applications requiring compact, low-power, and real-time solutions. [ABSTRACT FROM AUTHOR]

With the continuous development of deep learning, Deep Convolutional Neural Network (DCNN) has attracted wide attention in the industry due to its high accuracy in image classification. Compared with other DCNN hardware deployment platforms, Field Programmable Gate Array (FPGA) has the advantages of being programmable, low power consumption, parallelism, and low cost. However, the enormous amount of calculation of DCNN and the limited logic capacity of FPGA restrict the energy efficiency of theDCNNaccelerator. The traditional sequential sliding window method can improve the throughput of the DCNN accelerator by data multiplexing, but this method’s datamultiplexing rate is low because it repeatedly reads the data between rows. This paper proposes a fast data readout strategy via the circular sliding window data reading method, it can improve the multiplexing rate of data between rows by optimizing the memory access order of input data. In addition, themultiplication bit width of the DCNN accelerator ismuch smaller than that of the Digital Signal Processing (DSP) on the FPGA, whichmeans that there will be a waste of resources if amultiplication uses a single DSP. Amultiplier sharing strategy is proposed, the multiplier of the accelerator is customized so that a singleDSP block can complete multiple groups of 4, 6, and 8-bit signed multiplication in parallel. Finally, based on two strategies of appeal, an FPGA optimized accelerator is proposed.The accelerator is customized byVerilog language and deployed onXilinxVCU118.When the accelerator recognizes the CIRFAR-10 dataset, its energy efficiency is 39.98 GOPS/W, which provides 1.73 × speedup energy efficiency over previous DCNN FPGA accelerators. When the accelerator recognizes the IMAGENET dataset, its energy efficiency is 41.12 GOPS/W, which shows 1.28×−3.14 × energy efficiency compared with others. [ABSTRACT FROM AUTHOR]

Deep learning has brought great development to radar emitter identification technology. In addition, specific emitter identification (SEI), as a branch of radar emitter identification, has also benefited from it. However, the complexity of most deep learning algorithms makes it difficult to adapt to the requirements of the low power consumption and high-performance processing of SEI on embedded devices, so this article proposes solutions from the aspects of software and hardware. From the software side, we design a Transformer variant network, lightweight convolutional Transformer (LW-CT) that supports parameter sharing. Then, we cascade convolutional neural networks (CNNs) and the LW-CT to construct a one-dimensional-CNN-Transformer(1D-CNN-Transformer) lightweight neural network model that can capture the long-range dependencies of radar emitter signals and extract signal spatial domain features meanwhile. In terms of hardware, we design a low-power neural network accelerator based on an FPGA to complete the real-time recognition of radar emitter signals. The accelerator not only designs high-efficiency computing engines for the network, but also devises a reconfigurable buffer called "Ping-pong CBUF" and two-level pipeline architecture for the convolution layer for alleviating the bottleneck caused by the off-chip storage access bandwidth. Experimental results show that the algorithm can achieve a high recognition performance of SEI with a low calculation overhead. In addition, the hardware acceleration platform not only perfectly meets the requirements of the radar emitter recognition system for low power consumption and high-performance processing, but also outperforms the accelerators in other papers in terms of the energy efficiency ratio of Transformer layer processing. [ABSTRACT FROM AUTHOR]

Graph convolution networks (GCN) have demonstrated success in learning graph structures; however, they are limited in inductive tasks. Graph attention networks (GAT) were proposed to address the limitations of GCN and have shown high performance in graph-based tasks. Despite this success, GAT faces challenges in hardware acceleration, including: 1) The GAT algorithm has difficulty adapting to hardware; 2) challenges in efficiently implementing Sparse matrix multiplication (SPMM); and 3) complex addressing and pipeline stall issues due to irregular memory accesses. To this end, this paper proposed SH-GAT, an FPGA-based GAT accelerator that achieves more efficient GAT inference. The proposed approach employed several optimizations to enhance GAT performance. First, this work optimized the GAT algorithm using split weights and softmax approximation to make it more hardware-friendly. Second, a load-balanced SPMM kernel was designed to fully leverage potential parallelism and improve data throughput. Lastly, data preprocessing was performed by pre-fetching the source node and its neighbor nodes, effectively addressing pipeline stall and complexly addressing issues arising from irregular memory access. SH-GAT was evaluated on the Xilinx FPGA Alveo U280 accelerator card with three popular datasets. Compared to existing CPU, GPU, and state-of-the-art (SOTA) FPGA-based accelerators, SH-GAT can achieve speedup by up to 3283 × , 13 × , and 2.3 ×. [ABSTRACT FROM AUTHOR]

Recently, the neural networks with convolution computation is widely used for image classification and recognition. For real-time implementation, the video buffer is required to store the image temperately. However, traditional buffers like CLSB (content line shift buffer) may experience delays during the read process, particularly when encountering line breaks or image changes. As for N × N convolution, the delay time is N−1 clocks for every row changing. As the image width is W, the delay time is 2W + N clocks for every frame changing. These delays can impact the efficiency and performance of the neural network. To overcome this challenge, this paper presented novel buffer design to avoid the delay at the line ends and frame change. By proactively fetching data ahead of time, the buffer can dynamically schedule the read operation and ensure that the subsequent data are correctly placed for efficient processing. This improvement in read latency contributes to enhanced performance and better utilization of computational resources within the hardware system. Then the full convolutional network accelerator is implemented with the fast buffer design and common computational kernel to save the hardware cost based on LeNet model. The results show that the accuracy can achieve 99.1% with MNIST dataset verification. By eliminating the waiting time, the modified buffer allows for more efficient processing in the image, and the fame rate for a computer vision can achieve 46 per second, to meet the real-time requirement. [ABSTRACT FROM AUTHOR]

Specific workloads are increasingly offloaded to accelerators such as a graphic processing unit (GPU) and field-programmable gate array (FPGA) for real-time processing and computing efficiency. Because accelerators are expensive and consume much power, it is desirable to increase the efficiency of accelerator utilization by sharing accelerators among multiple servers over a network. However, task offloading over a network has the problem of latency due to network processing overhead in remote offloading. This paper proposes a low-latency system for accelerator offloading over a network. To reduce the overhead of remote offloading, we propose a system composed of (1) fast recombination processing of chunked data with a simple protocol to reduce the number of memory copies, (2) polling-based packet receiving check to reduce overhead due to interrupts in interaction with a network interface card, and (3) a run-to-completion model in network processing and accelerator offloading to reduce overhead with context switching. We show that the system can improve performance by 66.40% compared with a simple implementation using kernel protocol stack and confirmed the performance improvement with a virtual radio access network use case as a low-latency application. Furthermore, we show that this performance can also be achieved in practical usage in data center networks. [ABSTRACT FROM AUTHOR]

In this paper, we presented a PYNQ framework Based object recognition implementation using Convolution Neural Network (CNN) in Xilinx FPGA. A hardware-software codesign framework is used to implement the CNN for object recognition. Training CNN model on PC, and implementation object recognition under embedded system on PYNQZ1 FPGA. Compare to a single ARM processor core on FPGA, we achieve 43.2 times speedup ratio for object recognition implementation. The performance demonstrates that this model can be highly improved by exploring the hardware resources of the FPGA. [ABSTRACT FROM AUTHOR]

This paper presents the architecture of a Convolution Neural Network (CNN) accelerator based on a new processing element (PE) array called a diagonal cyclic array (DCA). As demonstrated, it can significantly reduce the burden of repeated memory accesses for feature data and weight parameters of the CNN models, which maximizes the data reuse rate and improve the computation speed. Furthermore, an integrated computation architecture has been implemented for the activation function, max-pooling, and activation function after convolution calculation, reducing the hardware resource. To evaluate the effectiveness of the proposed architecture, a CNN accelerator has been implemented for You Only Look Once version 2 (YOLOv2)-Tiny consisting of 9 layers. Furthermore, the methodology to optimize the local buffer size with little sacrifice of inference speed is presented in this work. We implemented the proposed CNN accelerator using a Xilinx Zynq ZCU102 Ultrascale+ Field Programmable Gate Array (FPGA) and ISE Design Suite. The FPGA implementation uses 34,336 Look Up Tables (LUTs), 576 Digital Signal Processing (DSP) blocks, and an on-chip memory of only 58 KB, and it could achieve accuracies of 57.92% and 56.42% mean Average Precession @0.5 thresholds for intersection over union (mAP@0.5) using quantized 16- bit and 8-bit full integer data manipulation with only 0.68% as a loss for 8- bit version and computation time of 137.9 and 69 ms for each input image respectively using a clock speed of 200 MHz. These speeds are expected to be doubled five times using a clock speed of 1 GHz if implemented in a silicon System on Chip (SoC) using a sub-micron process. [ABSTRACT FROM AUTHOR]

This paper describes experiments with the main parameters of the RF accelerating systems of the Booster and the Nuclotron of the Nuclotron based Ion Collider fAcility (NICA) complex, which affect the capture and acceleration, as well as the additional hardware solutions used in this case. The operating modes of accelerating stations of the Booster and the Nuclotron are considered. In particular, the paper describes the principle of formation of the law of the change in the amplitude of the accelerating voltage during the adiabatic capture of particles both in the Booster and in the Nuclotron, as well as the features of setting the sequence of synchronization pulses. [ABSTRACT FROM AUTHOR]

This paper conducts a comprehensive study on intermittent computing within IoT environments, emphasizing the interplay between different dataflows—row, weight, and output—and a variety of non-volatile memory technologies. We then delve into the architectural optimization of these systems using a spatial architecture, namely IDEA, with their processing elements efficiently arranged in a rhythmic pattern, providing enhanced performance in the presence of power failures. This exploration aims to highlight the diverse advantages and potential applications of each combination, offering a comparative perspective. In our findings, using IDEA for the row stationary dataflow with AlexNet on the CIFAR10 dataset, we observe a power efficiency gain of 2.7% and an average reduction of 21% in the required cycles. This study elucidates the potential of different architectural choices in enhancing energy efficiency and performance in IoT systems. [ABSTRACT FROM AUTHOR]

This paper presents a review of scientific and technical literature on the main production methods, various fields of application, and use of unsymmetrical ureas as an accelerator for the curing processes of epoxy compositions. Mechanisms of reactions between ureas and the widely used latent hardener dicyandiamide are presented, and the characteristics of resulting epoxy resins, as well as prepregs based on them, are considered. The possibility of using substituted ureas as an independent cross-linking agent for epoxy resins is mentioned. [ABSTRACT FROM AUTHOR]

The national institute of standards and technology (NIST) has presented its draft of the module-lattice-based key-encapsulation mechanism standard (MLBKEMS), choosing cryptographic suite for algebraic lattices (CRYSTALS)- Kyber as the base encryption. Existing hardware implementations of modern cryptography will need to process the new standard efficiently. The primary process in CRYSTALS-Kyber key-encapsulation mechanism (KEM) is the number theoretic transform (NTT), which requires heavy computing power. This paper contributes an efficient hardware accelerator for NTT and inverse NTT (INTT) by CRYSTAL-Kyber parameters. The proposed design utilizes the K-RED algorithm for reducing polynomial multiplication. It also incorporates the Brent-Kung method for efficient modular addition and subtraction operation with an address generator to control the sequences of computation. On the Xilinx Artix 7 field programmable gate array (FPGA), our design achieves 262 MHz clock speed, utilizing only 1405 LUTs. [ABSTRACT FROM AUTHOR]

The paper describes the design of a prototype magnetic field compensator intended to eliminate the influence of the edge magnetic field of the S-25P Pakhra accelerator magnet, Lebedev Physical Institute, on the electron beam during its output. The results of the study showed that this design could reduce an external magnetic field of B0 ~ 0.1 T to zero values inside the prototype. [ABSTRACT FROM AUTHOR]

As one of the fields of Artificial Intelligence (AI), Optical Character Recognition (OCR) systems have wide application in both industrial production and daily life. Conventional OCR systems are commonly designed and implement data computation on the basis of microprocessors; the performance of the processor relates to the effect of the computation. However, due to the "Memory-wall" problem and Von Neumann bottlenecks, the drawbacks of traditional processor-based computing for OCR systems are gradually becoming apparent. In this paper, an approach based on the Memory-Centric Computing and "Memory-Tree" algorithm has been proposed to perform hardware optimization of traditional OCR systems. The proposed algorithm was first designed in software implementation using C/C++ and OpenCV to verify the feasibility of the idea and then the RTL conversion of the algorithm was done using the Xilinx Vitis High Level Synthesis (HLS) tool to implement the hardware. This work chose Xilinx Alveo U50 FPGA Accelerator to complete the hardware design, which can be connected to the x86 CPU in the PC by PCIe to form heterogeneous computing. The results of the hardware implementation show that the system this work designed can recognize characters of English capital letters and numbers within 34.24 us. The power of FPGA is 18.59 W, which saves 77.87% of energy consumption compared to the 84 W of the processor in PC. [ABSTRACT FROM AUTHOR]

In this paper, a new match circuit of the capacitive divider is studied. Using the proposed match circuit, the signal measured by the capacitive divider will not be secondarily attenuated near the accelerator, and the secondary attenuation is done at the terminal end of the cable which is located in a shielding room with a good electromagnetic environment. So, the proposed circuit has a better anti-interference capability than the traditional terminal-end match circuit. The result of the theoretic analysis shows that the proposed match circuit is equivalent with the traditional terminal-end match circuit when the parameters of the circuit are well chosen. Rectangular pulse response of the proposed match circuit is tested based on an equivalent circuit. It shows that the proposed match circuit has a good pulse response characteristic for rectangular pulse with a rise time of 5 ns, and the output waveform of the match circuit has a flattop jitter less than 1%. The match circuit proposed in this paper is utilized to measure the diode voltage of the accelerator in our laboratory. It is found that the high-frequency interference on the output waveform measured by the new match circuit is much smaller than that measured by the traditional terminal-end match circuit, which proves that the match circuit proposed in this paper is an effective method for increasing the signal-to-noise ratio of capacitive divider for measurement of nanosecond-range HV pulse. [ABSTRACT FROM AUTHOR]

This paper conducts an extensive comparative study of state-of-the-art solutions for implementing the SHA-3 hash function. SHA-3, a pivotal component in modern cryptography, has spawned numerous implementations across diverse platforms and technologies. This research aims to provide valuable insights into selecting and optimizing Keccak SHA-3 implementations. Our study encompasses an in-depth analysis of hardware, software, and software–hardware (hybrid) solutions. We assess the strengths, weaknesses, and performance metrics of each approach. Critical factors, including computational efficiency, scalability, and flexibility, are evaluated across different use cases. We investigate how each implementation performs in terms of speed and resource utilization. This research aims to improve the knowledge of cryptographic systems, aiding in the informed design and deployment of efficient cryptographic solutions. By providing a comprehensive overview of SHA-3 implementations, this study offers a clear understanding of the available options and equips professionals and researchers with the necessary insights to make informed decisions in their cryptographic endeavors. [ABSTRACT FROM AUTHOR]

In this paper, phosphogypsum-based polymer foam lightweight soil was prepared by taking phosphogypsum as fine aggregate and adding coagulant and prefabricated foam. The changes in the properties of the material were studied deeply in terms of flow rate, setting time, mechanical properties, water absorption and softening coefficient, combined with XRD and SEM for microscopic testing. The results show that mortar test blocks with excellent performance can be prepared under the conditions of sand-to-ash ratio 0.6, water-to-material ratio 0.5 and quicklime 4%. The initial and final setting times are 210 and 260 minutes, the compressive strength of the specimen can reach 2.8 MPa after 3 days, and 11.9 MPa after 28 days. Foam lightweight soil with different wet density can be prepared by adjusting the amount of prefabricated foam, providing a new way for phosphogypsum resource application. [ABSTRACT FROM AUTHOR]

In recent decades, convolutional neural network (CNN) has become essential in many real-time applications due to its massive computational ability. But its use in portable devices is limited due to its high computation requirements. This paper proposes a novel One-Pass Processing Element (OPPE) to mitigate this limitation. The proposed OPPE removes redundant computations by eliminating those with zeros that leads to low area as well as low power consumption. The proposed OPPE model is evaluated with the help of VGG-16-based CNN accelerator. The proposed OPPE design reduces the number of four-input LUTs by 5.19%, 15.91%, 10.06% and 4.93% and the power consumption by 4.26%, 7.36%, 5.81% and 1.55% when compared with the conventional processing element (PE), activation gating PE, weight gating PE and zero gating PE, respectively. The proposed CNN accelerator design using OPPE achieves high throughput with less resource utilization. [ABSTRACT FROM AUTHOR]