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Paper chip is an efficient and inexpensive device for pesticide residues detection. However, the reasons of detection error are not clear, which is the main problem to hinder the development of pesticide residues detection. This paper focuses on error analysis for pesticide detection performed on paper-based microfluidic chip devices, which test every possible factor to build the mathematical models for detection error. In the result, double-channel structure is selected as the optimal chip structure to reduce detection error effectively. The wavelength of 599.753 nm is chosen since it is the most sensitive detection wavelength to the variation of pesticide concentration. At last, the mathematical models of detection error for detection temperature and prepared time are concluded. This research lays a theory foundation on accurate pesticide residues detection based on paper-based microfluidic chip devices. [ABSTRACT FROM AUTHOR]

In the process of complex product design, modeling in different fields and different disciplines is often involved. Designers often face many different development kits, platforms, and theories, among which significant differences exist. Especially in the process of algorithm-hardware implementation, it is necessary to have mastery of the knowledge including algorithm, hardware, circuit, and system engineering. In this paper, a modeling method of algorithm-hardware based on SysML is proposed to reduce the difficulty of algorithm-hardware modeling. By using the method, the designers who do not know the knowledge of hardware can also easily build the algorithm-hardware model. In this method, a method of graphical system modeling based on SysML is used, where the elements of the algorithm-hardware model are described by SysML graphical models. Then, the SysML graphical models are converted to Very-High-Speed Integrated Circuit Hardware Description Language. At last, a detecting algorithm of random number is complemented by the modeling method in this paper and the simulation results are presented at the conclusion. [ABSTRACT FROM AUTHOR]

First-order allpass filters are analog filters with a unit magnitude response, but they change the phase shift between input and output signals at various frequencies. This paper presents the transadmittance-mode first-order allpass filters based on the modified current-controlled current differencing transconductance amplifier (M-CCCDTA). The proposed filters utilize a single M-CCCDTA and a grounded capacitor with no external resistors, making them well suited for implementation in an integrated circuit. The gain and phase response of the proposed filters can be adjusted electronically and separately. Also, the high output impedance of the proposed filters at both the input voltage node and the output current node makes cascading easy without the need for buffer devices. A quadrature sinusoidal oscillator based on the proposed first-order allpass filter has been designed as an example of an application. The PSpice simulation and actual experiments are utilized to validate the functionality of the proposed filters. The simulation and experimental results are consistent with the idea of anticipation. [ABSTRACT FROM AUTHOR]

A simple circuit based on modified extra-X second-generation current conveyor (MEXCCII), which is capable of realizing the following grounded immittance functions: a lossless capacitor, a lossy capacitor, a lossy inductor and a lossy frequency-dependent negative conductance, is introduced in this paper. The circuit employs one MEXCCII and three passive components. The use of single active block makes the circuit structure simpler. No component's matching constraint is needed in the proposed circuit. The nonideal study of the proposed grounded immittance circuit is also included. The circuit's performance is examined using 0.18- μ m technology-based PSPICE simulations. Experimental results which are performed using off-the-shelf integrated circuits (ICs) and bread board are also included. The proposed circuit is negligibly affected by the temperature variation and process variation. A single pole high-pass filter as an application of the realized lossy capacitor and a band-pass filter as an application of the realized lossy inductor are also presented in this paper. The realized filters offer the feature of ease of cascadability. [ABSTRACT FROM AUTHOR]

This paper presents the structure and operational principles of high-frequency electronically controllable sinusoidal oscillators employing current-feedback operational amplifiers (CFOAs) with externally accessible compensation node z as active components. The resonant circuits in the oscillators are connected to the terminal z , and for them in the selective network varactor diodes or varicaps as the variable capacitances are utilized, which are controlled by external DC voltage. Based on an analysis of the proposed circuit configurations, analytical expressions for the characteristic equation in a steady-state mode of operation and formulas for the basic electrical parameters have been obtained. In order to verify the functionality of the proposed electronic circuits and the effectiveness of the derived analytical expressions, an experimental and simulation study of sample electronic circuits with commercially available integrated circuit CFOAs AD844 in the frequency range up to about 10 MHz is performed. The obtained results for the studied electronic circuits confirm the theoretical studies and hypotheses, and the comparative analysis shows that the maximum value for the relative error does not exceed 10%, which is acceptable considering the tolerances of the technological parameters of the used passive and active elements. [ABSTRACT FROM AUTHOR]

As the only nonlinear operation, masked S-box is the core to resist differential power attack (DPA) for advanced encryption standard (AES) cipher chips. In order to suit for the resource-constrained applications, a compact masked S-box based on composite field is proposed in this paper. Firstly, the architecture of masked S-box is designed with composite field masking method. Secondly, four masked S-boxes based on GF ((24)2), which are based on four basis methods with the optimal coefficient and the corresponding optimal root, are implemented and optimized by the delay-aware common subexpression elimination (DACSE) algorithm. Finally, experimental results show that, while maintaining the DPA-resistance performance, our best masked S-box achieves better area performance with the fastest speed compared with the existing works. Therefore, our masked S-box is suitable for resource-constrained applications with fast speed requirements. [ABSTRACT FROM AUTHOR]

Currently, static circuit power is becoming a major concern, dominating the total power consumption due to the scaling down of CMOS technology. The smaller sizes drastically affect the leakage current, which integrated circuit designers attempt to overcome this issue. Hence, several methods and technologies have been proposed to prevail this phenomenon. One of these methods is using memory structures in logic designs. A Hybrid MTJ/CMOS circuit is one of these promising techniques to design low-power nonvolatile circuits with power gating ability and low overhead for reconfigurable possibilities. In this paper, we have proposed a fully nonvolatile, low-power Full-Adder based on MTJs that uses the spin transfer torque method assisted by the spin hall effect. Simulation results of these designs by HSPICE show that they can work fast with low-power consumption compared to other state-of-the-art nonvolatile full-adders. [ABSTRACT FROM AUTHOR]

This paper suggests a new operational transconductance amplifier (OTA) based electronically tunable transimpedance-mode first-order universal filter (FOUF). The suggested FOUF produces all-pass (AP), high-pass (HP) and low-pass (LP) filter responses simultaneously. It employs three OTAs, two grounded resistors and only one grounded capacitor. Owing to use of grounded passive elements, the suggested FOUF is suitable for integrated circuit implementation. It operates at low power supply voltages. Additionally, the resonance frequency of the suggested AP filter can be adjusted in a wide frequency range. However, the suggested FOUF consists of only one matching condition. Moreover, a sinusoidal quadrature oscillator (QO) application that is derived from the suggested FOUF topology is given. The suggested FOUF and its QO application are simulated by using 0.18- μ m TSMC technology parameters in the SPICE program to validate the presented theory. Finally, an experimental test is performed to demonstrate workability of the suggested AP filter. [ABSTRACT FROM AUTHOR]

The design complexity and outsourcing trend of modern integrated circuits (ICs) have increased the chance for adversaries to implant hardware Trojans (HTs) in the development process. To effectively defend against this hardware-based security threat, many solutions have been reported in the literature, including dynamic and static techniques. However, there is still a lack of methods that can simultaneously detect and diagnose HT circuits with high accuracy and low time complexity. Therefore, to overcome these limitations, this paper presents an HT detection and diagnosis method for gate-level netlists (GLNs) based on different machine learning (ML) algorithms. Given a GLN, the proposed method first partitions it into several circuit cones and extracts seven HT-related features from each cone. Then, we repeat this process for the sample GLN to construct a dataset for the next step. After that, we use K-Nearest Neighbor (KNN), Decision Tree (DT) and Naive Bayes (NB) to classify all circuit cones of the target GLN. Finally, we determine whether each circuit cone is HT-implanted through the label, completing the HT detection and diagnosis for target GLN. We have applied our method to 11 GLNs from ISCAS'85 and ISCAS'89 benchmark suites. As shown in experimental results of the three ML algorithms used in our method: (1) NB costs shortest time and achieves the highest average true positive rate (ATPR) of 100%; (2) DT costs longest time but achieve the highest average true negative rate (ATNR) of 98.61%; (3) Compared to NB and DT, KNN costs a slightly longer time than NB but the ATPR and ATNR values are approximately close to DT. Moreover, it can also report the possible implantation location of a Trojan instance according to the detecting results. [ABSTRACT FROM AUTHOR]

With the development of system engineering and related technology, modeling and simulation of complex systems need to include many disciplines, modeling languages, simulation environments, etc. By using unified modeling language to build models, barriers among different fields can be broken; the efficiency of model integration can be improved. Generally, a complex system contains some integrated circuit modules, which can be used for control or calculation of the system. Compared with system model, integrated circuit model is more fine-grained and lower-level and contains logic for control and algorithms. Thus, a method that modeling integrated circuit by unified modeling language is necessary. In this paper, a unified modeling language is introduced, called X language, and a modeling method of algorithm-hardware based on the X language is proposed. First of all, the hardware characteristics of the Kalman filter algorithm are extracted by analyzing the algorithm. Second, X language models are built to describe the algorithm-hardware. Then, the X language models are converted to Very-High-Speed Integrated Circuit Hardware Description Language (VHDL). Finally, the algorithm-hardware models are simulated and verified. The results show that the algorithm-hardware modeling method based on X language is feasible. [ABSTRACT FROM AUTHOR]

Electrical engineering models often rely on complex circuit configurations that facilitate the dynamic flow of electrically charged particles within a closed conductive network. These circuits serve as essential tools for simulating and analyzing diverse electrical systems and components. This paper introduces a study on nonlinear fractional circuits modeling through the development of a stochastic neuro-computational artificial intelligent-based solver to address mathematical models governing the Fractional order Caputo–Fabrizio stiff electric circuit model (FO-CFSECM) by manipulating the knacks of layered recurrent neural networks (LRNNs) trained with Gradient-based local search algorithm (GLA). In fractional calculus, the Caputo–Fabrizio (CF) fractional order derivative (FOD) emerges as a powerful instrument, binding its capabilities to deliver remarkably accurate solutions for fractional stiff systems. The objective of this work is to exploit the numerical treatment comprehensively for the dynamics of fractal Resistor–Capacitor (RC) and fractal Resistor–Inductor (RL) circuit models by introducing the CF fractional operator. Through the application of artificial intelligence-based soft computing and advanced back-propagative deep neural networks, a deeper understanding of the behavior and distinctive characteristics inherent in these models is sought. The Levenberg–Marquardt optimizer serves as an efficient training GLA tool for learning of LRNNs weights of fractal RL/RC circuit models. The comparative studies on variants of FO-CFSECM demonstrate that LRNNs achieve an impressive mean square error (MSE) ranging from 10−9 to 10−19 and absolute error (AE) within 10−6 to 10−8. The accuracy, reliability, and efficiency of LRNNs for solving the FO-CFSECM were further validated through MSE, AE, controlling parameters of state transitions, error histograms, and correlation measures. [ABSTRACT FROM AUTHOR]

Full adders are a core component and play an essential role in the design of contemporary very-large-scale integration (VLSI) integrated circuits. Low-power, high-speed adder design has been the subject of numerous different sorts of research. The never-ending process is still in progress. The saturation point for MOS-based VLSI circuit design has been reached. As a consequence, many additional issues arise when MOS devices are scaled down to the nanoscale range, including an increase in leakage power and a vulnerability to PVT variation. Hence, MOSFET alternatives have been looked after by VLSI industries. Future nanoscale VLSI circuits would benefit greatly from the use of FINFETs in place of MOS transistors. In this paper, two diode-connected transistors-based low power, high speed, and low-power–delay product (PDP) adiabatic logic full adders are proposed using 7 nm technology. DCT TSAA-I, DCT TSAA-II, DCT TCAA-I, and DCT TCAA-II are the names of the proposed structures. Power, speed, and power–delay product (PDP) performance of the proposed adders are compared with those of traditional full adders. According to the simulation outcomes, the proposed adder architectures offer the least PDP in comparison to the adders taken into consideration. On power and delay, the impact of changing variables like temperature, supply voltage, load capacitance, and frequency is seen. A 7 nm FINFET model has been used in the simulations, which were conducted using the Hspice simulation tool. [ABSTRACT FROM AUTHOR]

Tunability of correlated color temperature (CCT) and dimmability are the two major sought after features of functional solid-state lighting. This paper presents a low-cost, efficient, single-inductor-dual-output buck driver that facilitates CCT-control and dimming of a light emitting diode (LED) module composed of cool-white and warm-white chips. The proposed driver is designed based on two familiar integrated circuits (ICs), namely LM2596 and NE556. LM2596 serves as the main switching regulator and amplitude modulation (AM) controller whereas NE556 serves as the constant-frequency, dual-output pulse-width-modulation (PWM) controller. The exponential model of LED is exploited for improved estimation of the design parameters of the LED module and the driver circuit. The developed driver prototype is tested for its electrical, photometric, and colorimetric performances. The driver offers a full-load efficiency of about 90% for a 12-W test LED module. Under different operating modes, the LED system can produce warm, cool, or neutral white light and at the same time, the produced illuminance can be varied over a wide range. Moreover, the light flicker is imperceptible since the PWM frequency is set according to IEEE-1789 guideline. [ABSTRACT FROM AUTHOR]

The term "self-organized criticality" in the scientific literature is shown to have spread in a fractal, tree-like process. The probability that one of the original papers will be cited in a subsequent paper is related to the random network growth of the entire field, much like the growth of the World Wide Web. This is in opposition to recent publications that argue for a multiplicative process in scientific publishing where publishing success is based on attributes directly inherent to the author. [ABSTRACT FROM AUTHOR]

Side-channel attacks (SCAs) are powerful noninvasive attacks that can be used for leaking the secret key of integrated circuits (ICs). Numerous countermeasures were proposed to elevate the security level of ICs against SCAs. Unfortunately, it is quite inconvenient to predict the security levels of these countermeasures since no solid mathematical model exists in the literature. In this paper, neural network (NN)-based entropy is proposed to model the resilience of a system against SCAs. The NN-based entropy model well links the side-channel leakages and probabilities with the neurons and weights of NNs, respectively. In such a circumstance, the NN-based entropy can be used for modeling the robustness of countermeasures since a one-to-one relationship is established between the NN-based entropy and the measurement-to-disclose (MTD) enhancement ratio related with the countermeasures. As demonstrated in the result, the proposed NN-based entropy metric shows 100% consistency with the MTD enhancement ratio if multiple SCA countermeasures are employed into a system. [ABSTRACT FROM AUTHOR]

Compared with the traditional copper material, carbon nanotube (CNT) has been identified as one of the most potential materials for interconnects in nanometer regime due to higher performance. However, for CNT interconnects, most of the researches focus on voltage-mode signaling (VMS) scheme, whereas current-mode signaling scheme (CMS) is meagerly investigated. The paper proposes an equivalent circuit model of two-line coupled single-walled CNT bundle interconnects, which is applicable to both CMS and VMS schemes. In addition, the model takes capacitive and inductive crosstalk into consideration. In CMS and VMS interconnects, the performance of victim line in the time domain is studied according to decoupling technique and ABCD parameter matrix approach at local, intermediate and global levels, respectively. The influence of aggressor line on victim line is discussed because of dynamic crosstalk and functional crosstalk. Furthermore, the paper comparatively analyzes the performance advantage between CMS interconnects and VMS interconnects. The results show that CMS interconnects have lower output voltage swing and propagation delay than VMS interconnects in the same condition. In terms of noise, CMS scheme has higher advantage for lesser noise peak, noise width and noise area. Moreover, it is found that the results obtained by ABCD parameter matrix approach have great consistency with Advanced Design System simulation results. [ABSTRACT FROM AUTHOR]

Improved speed, reduced delay, reduced size and reduced power are the most important requirements of integrated circuits. The carry select adder (CSA) is one of the most important adders in most data processors for performing arithmetic operations. The speed of parallel adders can be enhanced CSA, which widens the area to speed and eliminates propagation delays. The major problem faced in CSA is inefficient area due to the usage of multiple pairs of Ripple carry adders (RCAs) for generating the sums and carry. This research paper proposes the modified 32-bit square root carry select adder (MSCSLA) to improve the direct digital synthesizer's performance (DDS). DDS plays an effective role in the digital system due to its ability of broad frequency generation. Phase accumulator is the main component in the DDS synthesizer, where the speed of the adder is enhanced through MSCSLA. The general square root CSA still consumes more power due to the assembly of more RCAs. Hence, in the proposed approach, certain sets of RCAs are replaced with BEC1 (Binary to excess 1 convertor) to improve the speed and reduce the delay of the adder. Finally, the continuous sinusoidal waveform is attained by attenuating the high-frequency components by adopting a low pass filter. The entire structure of DDS is designed using Xilinx Verilog coding. The Simulation result shows better outcomes in terms of area, delay, power, and high performance in the DDS synthesizer compared to the existing CSAs. When compared to the existing adders, the area occupied by the proposed MSCSLA model is attained to be 636 μ m2, the power is achieved as 50.125 μ W and delay is attained to be 1.280 ns, which are comparatively less. When comparing delay and maximum frequency with the existing techniques, the proposed model obtained minimum delay and maximum frequency. The overall power consumption by the proposed model is also attained to be lower than the existing techniques. [ABSTRACT FROM AUTHOR]

This paper deals with the experimental realization of square/triangular wave generator using commercially available ICs. A prototype of extra-X second generation current conveyor and five passive components are used in the experimental setup. The proposed generator provides both square and triangular waveforms simultaneously in voltage-mode. The circuit enjoys the feature of independent controllability of oscillation frequency via grounded resistor/grounded capacitor. A range of oscillation frequency from 3 Hz to 250 Hz is easily achieved via variation in one of the grounded resistors for a fixed value of capacitor. Moreover, a range of oscillation frequency from 19.8 Hz to 19.2 kHz can be achieved through the variation in grounded capacitor. The experimental results show that the performance of the proposed generator is good at operating frequency as low as at 19.8 Hz and as high as 19.2 kHz. Therefore, the proposed circuit can operate well from extra-low-frequency range to very-low-frequency range. Furthermore, the maximum nonlinearity of oscillation frequency is found to be 4% only. [ABSTRACT FROM AUTHOR]

This paper presents a low-power low-noise instrumentation amplifier (IA) for bio-potential recording. The proposed IA is based on a novel Gm-RSC structure, whose gain is determined by the transconductance (Gm) and the equivalent resistance (R) of the switched-capacitor (SC) load. The transconductance amplifier stage is based on the current-reuse telescope topology to achieve low noise at low-power dissipation. A resistor-controlled oscillator is designed to generate desirable operational frequency for SC load and to continuously tune the mid-band gain of the IA for different biomedical applications. Measurement results show that the input referred noise of the proposed IA is about 1.27μVRMS (BW=150Hz) and the noise efficiency factor is 3.3. The range of tunable gain is from 28 to 40dB. The common mode rejection ratio and power supply rejection ratio at 50Hz are 72 and 78dB, respectively. The IA consumes only 660nA current at 1.2V supply and the active area of the IA is only 0.035mm2. [ABSTRACT FROM AUTHOR]

Integrated circuit (IC) industry network has been built in Yangtze River Delta with the constant expansion of IC industry. The IC industry network grows exponentially with the establishment of new companies and the establishment of contacts with old firms. Based on preferential attachment and exponential growth, the paper presents the analytical results in which the vertices degree of scale-free network follows power-law distribution p(k)∼k−γ (γ=2β+1) and parameter β satisfies 0.5≤β≤1. At the same time, we find that the preferential attachment takes place in a dynamic local world and the size of the dynamic local world is in direct proportion to the size of whole networks. The paper also gives the analytical results of no-preferential attachment and exponential growth on random networks. The computer simulated results of the model illustrate these analytical results. Through some investigations on the enterprises, this paper at first presents the distribution of IC industry, composition of industrial chain and service chain firstly. Then, the correlative network and its analysis of industrial chain and service chain are presented. The correlative analysis of the whole IC industry is also presented at the same time. Based on the theory of complex network, the analysis and comparison of industrial chain network and service chain network in Yangtze River Delta are provided in the paper. [ABSTRACT FROM AUTHOR]

This paper deals with the realization of current-mode first-order universal filter based on multiple output second generation current conveyor (MO-CCII). Two MO-CCIIs, one resistor and one capacitor are used in the circuit realization. The proposed work includes additional features such as ease of cascadability, easily implementable in modern integrated circuit technology and no requirement of passive components matching condition. The additional beauty of the proposed filter structure is that all three responses can also be realized by interchanging the positions of passive components as well. Moreover, a possible transformation of the proposed current-mode type universal filter into a voltage-mode type universal filter using network transpose method is also explored. The possibility of mode transformation further expands the scope of proposed idea. The theoretical aspects are verified using cadence VIRTUOSO simulation results. [ABSTRACT FROM AUTHOR]

The complexity of any integrated circuit pushes the researchers to optimize the various parameters in the design process. Usually, the Nondeterministic Polynomial problems in the design process of Very Large Scale Integration (VLSI) are considered as a Single Objective Optimization Problem (SOOP). However, due to the increasing demand for the multi-criterion optimization, researchers delve up on Multi-Objective Optimization methodologies to solve a problem with multiple objectives. Moreover, it is evident from the literature that biologically inspired algorithm works very well in optimizing a Multi-Objective Optimization Problem (MOOP). This paper proposes a new Lion's pride inspired algorithm to solve any MOOP. The methodologies mimic the traits of a Lion which always strives to become the Pride Lion. The Algorithm was tested with VLSI floorplanning problem wherein the area and dead space are the objectives. The algorithm was also tested with several standard test problems. The tabulated results justify the ruggedness of the proposed algorithm in solving any MOOP. [ABSTRACT FROM AUTHOR]

The ancient Vedic mathematics is well known for quicker handy multiplications but its recognition as an integrated circuit core against existing hardware multipliers is not established. As optimized hardware implementation of binary multiplier is one of the prominent unsolved problems in computer architecture, this paper proposes efficient Urdhava Tiryakbhyam Vedic multiplier architecture and compares it with the set of hierarchical multiplication algorithms which generate multiplication result in a single clock cycle. Two innovative algorithms are proposed here, one with a compact structure and another for faster execution. Also, its optimized transistor level layout is designed and implemented. To maintain homogeneity for comparison, all the algorithms are programmed on a common HDL language platform and analyzed with the same tool and technology. Final results indicate that the proposed architecture delivers 15.5% less power delay product (PDP) compared to closest competitor algorithm. [ABSTRACT FROM AUTHOR]

In the analog and mixed-signal integrated circuits, voltage references that are independent of various factors such as temperature drift, noise, supply voltage, etc., and efficient in terms of power as well as area, are highly in demand to improve the efficiency of the overall circuits. Voltage references are one of those circuits that have applications in both high-power systems and low-power system-on-chip (SoC) designs for wireless connectivity like the internet of the things (IoT) or the internet of the medical things (IoMT). They are responsible for providing a stable bias or reference voltage. Thus, voltage reference influences directly or indirectly the performance of these systems. A comparative study between the techniques used in bandgap voltage references and CMOS voltage references, in terms of performance parameters such as line sensitivity, output noise, PSRR, temperature coefficient, etc., is presented in this paper so that we can choose the voltage references as per the applications and environment. [ABSTRACT FROM AUTHOR]

In this paper, Pseudo-Boolean Satisfiability (PB-SAT)-based congestion reduction and overflow minimization techniques are introduced for constructing congestion-aware rectilinear Steiner trees for global routing in IC design. Since congestion in different routing channels is a big issue in routing nets, various congestion minimization approaches have been proposed by many researchers. However, the increasing complexity of integrated circuits and the reduction of their size make the congestion problem more complicated. The proposed method can produce a congestion-free routing solution by generating a suitable rectilinear Steiner tree for circuit nets. To reduce the complexity of the problem, the nets are solved individually using a Minimum Bounding Box (MBB)-based heuristic technique. The algorithm is validated by utilizing the well-known ISPD 98 global routing benchmarks. Experimental results prove that the methodology is capable of routing most of the nets within the given routing capacity satisfying all the routing parameters. The results also show that the algorithm can produce congestion-aware Steiner trees efficiently within a nominal time-bound. [ABSTRACT FROM AUTHOR]

This paper presents a scalable Fully-digital differential analog voltage comparator designed in Semi-Conductor Laboratory (SCL) 180 nm complementary metal-oxide semiconductor technology. The proposed design is based on a digital design approach and is easily configurable to lower technology nodes. This design methodology makes the circuit less sensitive to process variations and takes fewer design efforts suitable for Systems-on-a-Chips (SOCs) application. The proposed circuit is designed and simulated in Cadence Virtuoso Analog Design Environment at the supply voltage ranging from 1 V to 1.8 V. The fully-digital analog voltage comparator has been synthesized using Synopsys Design Vision and auto-placed & auto-routed using Synopsys IC Compiler. This proposed comparator has a resolution of up to 7-bit at a supply voltage of 1.8 V and a worst-case operating frequency of about 750 MHz at the TT corner. The obtained value of the offset voltage and delay is 0.55 mV and 0.72 ns, respectively. The simulated results have shown that the power dissipation of the proposed scalable analog voltage comparator is 1 5 0 μ W @ 1 V and 3 1 2 μ W @ 1. 8 V supply voltage, respectively. Also, the RC extracted post-layout simulations have been implemented to verify the performance, which does not affect the results much. [ABSTRACT FROM AUTHOR]

In this research paper, a simple design of an ultra-wideband (UWB) multi-input multi-output (MIMO) antenna with low envelope correlation coefficient (ECC), high isolation, enhanced gain, radiation efficiency and reconfigurable band notching functionality is proposed. Two symmetrical slots are carefully integrated into the partial ground plane of the conventional monopole to provide a notched band at 5.8 GHz for the WLAN system. This notching method is simple and does not endure negative effect performance or any design complexity. The notched band is then controlled using PIN diodes. A complete biasing circuit is integrated on the same partial ground plane to bias the PIN diodes in forward and reverse directions. To reduce the complexity of the design that may be increased due to the reconfiguration circuit, isolation enhancement is accomplished by orthogonal placement of the elements rather than using any additional decoupling structures. A prototype of the MIMO UWB structure is fabricated and its performance parameters are experimentally tested. The captivating agreement between simulation and measurement demonstrates that the proposed antenna system is a good candidate for UWB applications with an operating band extending from 3 to 11 GHz, notch-band reconfiguration freedom, and isolation of more than 20 dB. [ABSTRACT FROM AUTHOR]

This paper introduces the experimental results obtained after processing an electrocardiographic signal by a full-custom, low-complexity, Sigma-Delta Modulator integrated circuit, designed and fabricated using the C5N CMOS technology available through MOSIS. By exploiting a large oversampling ratio, it was possible to obtain an effective number of bits equal to 11 at the proposed single-bit modulator's output. The resulting bitstream was captured with a logic-state analyzer and processed offline. After decimation and digital filtering, the electrocardiographic signal was reconstructed and plotted in the time domain. Commonly referred quality metrics over the retrieved signal were calculated. A total signal-to-noise and distortion ratio, superior to 66 dB, was achieved by analyzing the entire system. The proposed approach shows the feasibility of processing electrocardiographic signals using low-cost and straightforward CMOS technology circuits. Since the proposed converter uses a single voltage supply of 1.5 V, exhibits a power consumption of 38 μ W, and uses a silicon area of 0.052 mm2, it is suitable for single battery-operated systems on a chip. [ABSTRACT FROM AUTHOR]

Simulation of inductors has been a very popular area of analog circuit research and the alternative choice for realizing inductor-based circuits in integrated circuits. In this paper, lossless, grounded and floating inductor topologies using current-controlled-current-feedback amplifier (CC-CFA) with single grounded capacitor are presented. The proposed topologies can be tuned electronically by changing the biasing current of the CC-CFA. Two topologies for grounded inductor simulator employ two CC-CFA and one grounded capacitor. One topology for floating inductor simulator employs three CC-CFA and one grounded capacitor. The performance of the grounded and floating inductor simulators are demonstrated on resonant circuits. The theoretical analysis is verified by PSPICE simulation results. [ABSTRACT FROM AUTHOR]

This paper presents a new electronically tunable voltage-mode universal filter with four-input one-output employing six simple operational transconductance amplifiers (OTAs), two grounded capacitors and two MOS resistors. The use of grounded passive components is beneficial for integrated circuit implementation. The proposed filter can realize low-pass, band-pass, high-pass, band-stop and all-pass filtering functions without active and passive component-matching conditions and inverting-type input signals requirements. The natural frequency and quality factor can be tuned independently and electronically by adjusting the bias currents. The voltage-mode filter offers the features of high-input impedance and low active and passive sensitivities. The characteristics of the proposed universal filter are verified using PSPICE simulators through 0.35 μ m CMOS process. Experimental results are used to confirm the workability of proposed circuit through LM13600 commercially available OTAs. Also a digitally programmable filter is shown to confirm the advantage of multiple-input universal filter. [ABSTRACT FROM AUTHOR]

In this paper, a half-elliptical disc ultra-wideband (UWB) monopole antenna integrated with a reconfigurable rectangular slot antenna is presented. It consists of a half-elliptical disc radiator to operate in the UWB mode whereas the etched rectangular slot on the half-elliptical patch is designed to operate as a reconfigurable narrowband slot antenna which is fed through a microstrip line from the back side of the patch. Both the antennas are placed in such a way that they are isolated to each other. Frequency reconfigurability has been achieved by inserting three lumped elements (two PIN diodes and a varactor diode) in the slot. An approximate transmission line model of the proposed slot antenna is derived to calculate the proper positioning of the diodes, and the design has been verified through numerical simulations. The simple compact proposed antenna covers a wide frequency range from 0.75 to 12 GHz. Additionally, a wide tuning range from 0.8 to 2.9 GHz (with the frequency ratio of 3.625:1) has been achieved. This compact integrated antenna is a good choice to be implemented in Cognitive Radio (CR) devices. [ABSTRACT FROM AUTHOR]

This paper presents an ultra-low-power current-mode ECG instrumentation amplifier, which is designed based on the current balancing technique and fabricated in TSMC 0.35 μm CMOS process. The instrumentation amplifier, which is presented here has three features. First, the instrumentation amplifier is a full-CMOS implementation of current-balancing technique applied for ECG signal conditioning. Second, the instrumentation amplifier is of ultra-low-power due to a power-oriented design methodology, which makes its power consumption very low compared to the earlier reported works for ECG recording applications. Third, integrated programmable bandpass filtering is implemented in the amplifier itself, which provides a compact solution for analog ECG signal conditioning. Measurement results show that the amplifier only draws 9 μA current from a 3.3 V lithium-ion battery, while CMRR of 100 dB and input voltage dynamic range of ± 6 mV are achieved. By considering trade-offs between input noise voltage and power, noise performance was compromised with power and area for ultra-low-power ECG signal conditioning applications. Measurement results show $0.3\, \mu {\rm V}/\sqrt{{\rm Hz}}$ input referred noise voltage with a flicker noise corner frequency of 15 Hz at 9 μA dc current and small area, which is appropriate for the desired application. Measurement results meet the recommended specifications for signal conditioning of portable ECG monitoring devices. Design methodology, fabrication considerations, measurement setup, and experimental results are also explained in this paper. [ABSTRACT FROM AUTHOR]

The proliferation of integrated circuits (ICs) in the present technological era has brought forth revolutionary digital modernization that has ultimately transformed the history and lifestyle of humankind. ICs have become the heart of practically all state-of-the-art electronic devices such as computers, cell phones, video game consoles, and cameras. This ever-flourishing IC design industry is knowledge-intensive, which in turn translates into a huge appetite for technically precocious talents. Hence, in an effort to fuel and further foster the industry with more highly skilled manpower and at the same time to vie for a share of the burgeoning industry, higher educational institutions and universities from all around the globe are placing greater than ever emphasis on IC design research. Most importantly, strenuous efforts in a holistic manner are being made by each university in order to elicit outstanding and top-notch research in IC design. The authors have conducted a detailed and extensive survey to rank the various universities of the world in the field of IC design based on their research performance. In fact, assessments in the form of ranking have gained prominence over the recent years captivating the attention of a large number of students and universities. It helps the students in knowing how each university is progressing in a particular field and in turn helps the universities in analyzing their positions globally to remain competitive. Three ranking indicators, namely the Number of Publications, Citation Counts, and Cites per Paper have been chosen. The methodology used in ranking is also reported. The universities occupying the top echelons in IC design research are identified and a proven three-pronged approach for eliciting outstanding research performance is discussed. [ABSTRACT FROM AUTHOR]

This paper proposes designing a precision rectification circuit by using a single operational transresistance amplifier (OTRA). The proposed circuit is a switch-controllable OTRA-based full-phase operation precision half-wave rectifier, which can rectify an input signal to yield four-phase half-wave rectified output signals. Compared with existing designs, the advantage of the proposed circuit is that all of the possible rectified outputs of a half-wave rectifier can be obtained in one configuration. This paper first reviews previously reported half-wave precision rectifiers consisting of various active devices and the proposed OTRA-based precision half-wave rectifier; subsequently, an analysis of non-ideal effects and design considerations are presented. Computer simulations of the proposed circuit were conducted for verifying the feasibility of the circuit by using the Taiwan Semiconductor Manufacturing Company (TSMC) 0.35-m CMOS process technology. For practical circuit measurements, a prototype circuit was implemented, and commercially integrated circuits (AD844ANs) and discrete passive components were used to conduct experimental tests. The simulation and experimental results exhibited satisfactory agreement with those of theoretical analyses. [ABSTRACT FROM AUTHOR]

Dynamic frequency scaling (DFS) is a feature commonly found in modern processors. It lowers the clock frequency of a core according to the load level and reduces the power consumption. In this paper, we present a case study of tuning DFS parameters on a platform with an AMD Phenom II X6 using the SPECjEnterprise2010 (jEnt10) and SPECjbb2005 (jbb05) as the workload. In jEnt10, a longer sampling period of core utilization (up to 1.5s) reduced the power by 6Watt at 25% load level. At 50% load level, combining it with an increased threshold level (98%) to switch the clock frequency further reduced the power consumption by up to 10Watt. In jbb05, stretching the sampling period was only effective up to 0.5s. The maximum reduction was observed at around 60% load level. Raising the threshold level was not effective for jbb05. [ABSTRACT FROM AUTHOR]

Instead of boost/buck conversion processor, power supplies single-phase SEPIC conversion processor becomes widely used in computer motherboards and other integrated circuits as well as in photovoltaic solar cell systems. However, multiplier and multiphase interleaved conversion processors become preferred due to their identical advantages over traditional single-phase SEPIC from the possibility of current stress or ripple reduction in active or passive elements perspectives. This paper presents a new class of a double-phase SEPIC conversion processor that has a modified structure in order to maximize the dynamic performance of the previously mentioned topologies of SEPIC. An analytical comparative study was conducted for the multiplier and modified double-phase interleaved SEPIC processor with magnetically uncoupled inductive reactors to show the benefits of this new class of the double-phase connection of SEPIC when compared with the traditional and the multiplier connection. The proposed topologies of multiplier and modified SEPIC are simulated using the Simulink MATLAB, Excel and Simplorer 7. The experimental results and analysis have shown the improved characteristics of the proposed new class of the double-phase SEPIC, low harmonic distortion, sacredness to component tolerance, relief in overall current fluctuation reduction complexity, high power efficiency and a very high voltage gain. [ABSTRACT FROM AUTHOR]

This paper presents a multi-output on-chip switched-capacitor (SC) DC-DC converter simultaneously providing two output voltages (2VDD/3 and VDD/3, in addition to the available full VDD) that enables the use of three different power modes for optimizing system power/performance trade-offs: super-threshold (full VDD), near-threshold (2VDD/3) and sub-threshold (VDD/3). Unlike some previously proposed multi-output SC converters, the multiple conversion ratios of the proposed converter are achieved without changing the topology of the circuit, thus fewer components being needed to support multiple voltages. The paper also presents an optimization method by using unequal flying capacitors for different regions of the circuit by taking advantage of the different levels of expected power consumption in the various power modes. Above 84% and 70% efficiencies are obtained in simulation over a range of load currents from 0.4 to 5 mA, and from 0.4 to 1 mA, with conversion ratios of 2/3 and 1/3, respectively. The target application for the proposed converter is for circuits with discrete power modes and for systems that use dithering to emulate a continuous range of voltages such as the panoptic dynamic voltage scaling (PDVS). [ABSTRACT FROM AUTHOR]

Hardware Trojan Horses (HTHs) are malicious modifications inserted in Integrated Circuit during fabrication steps. The HTHs are very small and can cause damages in circuit function. They cannot be detected by conventional testing methods. Due to dangerous effects of them, Hardware Trojan Detection has become a major concern in hardware security. In this paper, a new HTH detection method is presented based on side-channel analysis that uses path delay measurement. In this method, we find and observe the paths that Trojans have most effect on them. Most of the previous works add some structures to the circuit and need a large overhead cost. But, in our method, there is no modification in the circuit and we can use it for testing the circuits received after fabrication. The proposed method is evaluated with Xilinx FPGA over a number of test circuits. The results show that measuring the delays on 20 paths with an accuracy of 0.01ns can detect more than 80% of Trojans. [ABSTRACT FROM AUTHOR]

As the performing ability of a silicon chip relies on the power supply voltage, it must be configured using genuine power and ground bond pads for mitigating power and ground noise (PGN), which is directly boosted by the increasing peaks of instantaneous current and current ramp . To address the same, a novel and compact clock gating (CG) scheme is unveiled in this paper to effectively control the peak of and , thereby subduing PGN. The new CG arrangement is simulated for 90nm Predictive Technology Model (PTM90), where it is observed that the scheme reduces 88.80% of and 84.19% of average in comparison to its no gating counterpart along with a reduction of 80.14% in average power dissipation. These results are found to be more prominent when the proposed circuit configuration is tested in 90nm Generic Process Design Kit (GPDK90), proclaiming 88.75% and 84.34% reduction in average and average power, respectively, to illustrate its capability of truncating PGN in silicon chips. [ABSTRACT FROM AUTHOR]

Low-power consumption in three-dimensional integrated circuits (3D IC) design is becoming an important concern that cannot be neglected. The multiple layers/dies are stacked in 3D IC and communicate with each other through-silicon-vias (TSVs) to work as a single device in order to achieve high performance with minimum power dissipation. This paper demonstrates high-level power modeling approach for the power estimation of homogenous integration of Network-on-Chip (NoC)-based mesh architecture in 3D IC design. The preliminary experimental work of power model is divided into two major parts of the design. The first part estimates the power of NoC architecture on each stack separately and the second estimates the power dissipation of the uniformly distributed TSVs and input/output (I/O) pads. The model uses a linear function to estimate the average power dissipation. For an entire IC design, the average power is extracted by simple addition of all power estimation results of the model. The design is operated with multiple frequencies to find the most appropriate frequency to minimize power dissipation. In experiments, the average maximum error is estimated 18.03%. [ABSTRACT FROM AUTHOR]

A simple analog multiplier circuit employing one current-mode active building block (ABB) and two n-channel metal-oxide semiconductor (NMOS) transistors is presented in this paper. The used ABB is extra-X second generation current conveyor. The used NMOS transistors are operated in triode region. The circuit has appropriate impedance level at the input and output terminals. Some other key features of the proposed circuit are as follows: suitable to integrated circuit fabrication, good dynamic range and low operating power supplies. The nonideal effects of extra-X second generation current conveyor on the proposed circuit are studied. Additionally, the layout of the proposed circuit is developed using Cadence VIRTUOSO Analog Design Environment with gpdk 0.18 µm technology and post layout simulation results are given to verify the theoretical aspects. [ABSTRACT FROM AUTHOR]

This paper details an application-specific integrated circuit (ASIC) with an array of switched-resistor-based memristors (resistor with memory) and integrate & fire (I & F) neuron circuits for the development of memristor-based pattern recognition. Since real memristors are not commercially available, a compact memristor emulator is needed for device study. The designed ASIC has five memristor emulators with one having a conductance range from 4.88ns to 4.99s (200k to 204.8M) and other four having conductance ranging from 195ns to 190s (5.2k to 5.12M). Signal processing has been planned to be off-chip to get the freedom of programmability of a wide range of memristive behavior. This paper introduces the memristor emulator and the realization of synapse functionalities used in neuromorphic circuits such as long term potentiation (LTP), Long Term depression (LTD) and synaptic plasticity. The ASIC has two I & F neuron circuits which are intended to be used in conjunction with memristors in a multiple chip network for pattern recognition. This paper explains the memristor emulator, I & F neuron circuit and a respective neuromorphic system for pattern recognition simulated in LTspice. The ASIC has been fabricated in AMS 350nm process. [ABSTRACT FROM AUTHOR]

This paper presents a formal and model driven design approach for a high speed data transmission channel. The formal process algebra communicating sequential processes (CSP) was used to specify the system functionality. Automated model checking established, beyond reasonable doubt, important system properties, such as freedom from deadlock and livelock. Once these properties were established, the functionality was translated into an implementation which realizes high speed data transmission between two independent IC chips. Normal and failure case testing ensured that the implementation complies with the specification. This work shows how formal and model driven design methodologies speed up the process of turning ideas into physical problem solutions. More specifically, formal modeling gave us firm understanding and deep insight of the system functionality which enabled us to implement and to select correct system components. [ABSTRACT FROM AUTHOR]

A readout integrated circuit (ROIC) of infrared focal plane array (IRFPA) with low power and low noise is presented in this paper. It consists of a 384 x 288 pixel array and column-level A/D conversion circuits. The proposed system has high resolution because of the odd-even Analog to Digital Conversion (ADC) structure, containing correlated switches design, multi- Vth amplifier design and high speed high resolution comparator design including latch-stage. Designed and simulated in 0.35-7#976;m CMOS process, this high performance ROIC achieves 81.24 dB SNR at 8.64 KS/s consuming 98 mW under 5 V voltage supply, resulting in an ENOB of 13.2-bit. [ABSTRACT FROM AUTHOR]

A novel electronically adjustable square/triangular waveform generator has been introduced in this paper. The proposed circuit employs one active element, the multi-output current-controlled current conveyor transconductance amplifier, and one passive component grounded capacitor only. The resistorless realization of the presented generator provides a good advantage in terms of integrated circuit fabrication. In the offered circuit, the frequency and amplitude of the output square wave are electronically tunable by means of relevant bias currents. Additionally, the upper and lower threshold levels are electronically controllable by the respective bias current. On the contrary, electronically adjusting of the duty cycle of output waveform is possible via the external DC current. The generator circuit is simulated with TSMC 0.18 μ m technology parameters and SPICE. Moreover, the introduced circuit is implemented by using commercially available active devices and thus it is also verified experimentally. [ABSTRACT FROM AUTHOR]

This paper presents a state-of-the-art application of fractional hopfield neural networks (FHNNs) to defend against chip cloning attacks, and provides insight into the reason that the proposed method is superior to physically unclonable functions (PUFs). In the past decade, PUFs have been evolving as one of the best types of hardware security. However, the development of the PUFs has been somewhat limited by its implementation cost, its temperature variation effect, its electromagnetic interference effect, the amount of entropy in it, etc. Therefore, it is imperative to discover, through promising mathematical methods and physical modules, some novel mechanisms to overcome the aforementioned weaknesses of the PUFs. Motivated by this need, in this paper, we propose applying the FHNNs to defend against chip cloning attacks. At first, we implement the arbitrary-order fractor of a FHNN. Secondly, we describe the implementation cost of the FHNNs. Thirdly, we propose the achievement of the constant-order performance of a FHNN when ambient temperature varies. Fourthly, we analyze the electrical performance stability of the FHNNs under electromagnetic disturbance conditions. Fifthly, we study the amount of entropy of the FHNNs. Lastly, we perform experiments to analyze the pass-band width of the fractor of an arbitrary-order FHNN and the defense against chip cloning attacks capability of the FHNNs. In particular, the capabilities of defense against chip cloning attacks, anti-electromagnetic interference, and anti-temperature variation of a FHNN are illustrated experimentally in detail. Some significant advantages of the FHNNs are that their implementation cost is considerably lower than that of the PUFs, their electrical performance is much more stable than that of the PUFs under different temperature conditions, their electrical performance stability of the FHNNs under electromagnetic disturbance conditions is much more robust than that of the PUFs, and their amount of entropy is significantly higher than that of the PUFs with the same rank circuit scale. [ABSTRACT FROM AUTHOR]