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As the amount of data is increasing rapidly, its storage and security issues also increase. Hadoop is currently a popular framework for big data storage and processing. Since, security is not a primary consideration in Hadoop when it was initially developed makes the data stored in Hadoop distributed file system (HDFS) vulnerable to attacks. For protecting these data, numerous encryption techniques has been developed. This paper analyses and presents a comparison on advanced encryption standard (AES), a symmetric cipher and Rivest-Shamir-Adleman (RSA), an asymmetric cipher cryptographic algorithms. Finally, this paper proposes a hybrid method that combines both RSA and AES technique to improve the performance of encryption-decryption on HDFS files and thereby increases the security of big data in Hadoop framework. The proposed technique is found to be feasible and is able to enhance the confidentiality of HDFS files stored in Hadoop framework and is also able to overcome the limitations when using the AES encryption technique alone.

Encryption is a major requirement in today’s world as it boosts the security of the data that everyone shares all over the Internet. Videos are the means of communication in several industries and can be private. Encrypting a video file to a text file using the AES encryption algorithm increases the security provided while sharing such content over the Internet. Currently, apps to encrypt text files and images exist for the Android OS, and this paper proposes the next step in that direction - an Android app for video encryption and decryption. The results obtained via the method proposed in this paper are nearly 10 times better than the existing results.

With the rapid development of the Internet technology, data security is becoming more and more important. Data encryption is an important means to protect data security. AES is an important algorithm for encrypting data. However, when the amount of data needed to be encrypted is large, the traditional AES algorithm runs very slowly. This paper presents a parallel AES encryption algorithm based on MapReduce architecture, which can be applied in large-scale cluster environment. It can improve the efficiency of massive data encryption and decryption by parallelization. And the paper designs a parallel cipher block chaining mode to apply AES algorithm. Experiments show that the proposed algorithm has good scalability and efficient performance, and can be applied to the security of massive data in cloud computing environment.

This paper proposes an efficient closely-coupled method for integrating the widely used Advanced Encryption Standard (AES) hardware as a coprocessor IP core in the LEON3 processor-based System-on-Chip (SoC) design. As AES is increasingly being used in Internet of Things (IoT) and Edge computing devices to secure transmission of sensitive data, this method can be used to reduce the energy consumption in embedded applications. The closely-coupled method presented in this paper combines the benefits of both the traditional tightly-coupled and the industry prevalent bus-coupled approaches. The proposed method provides higher performance along with portability, to address the demand of higher processing power and reduced time-to-market. A maximum of 10% reduction in number of clock cycles was achieved in our experiments which translates to significant energy saving compared to industry prevalent bus-coupled hardware coupling method.

This paper proposes a High Level Synthesis (HLS) design methodology that translates complex algorithms modeled in high level language to hardware description. The existing HLS strategies fails to provide adequate abstraction to the underlying hardware details and thus limits software programmers from designing complex and advanced cipher algorithms. In this paper the method of generating synthesizable Register Transfer Level (RTL) design from algorithm is accomplished through an open framework called AHIR, an acronym for a hardware intermediate representation. The integrated design flow intends to generate layout from algorithm with minimal human intervention and thus offers software programmers with ample opportunities to design application specific digital hardware. The paper discusses several highlights of the design flow including savings in verification, rapid prototyping and shorter time to market together with various performance overheads. The cipher algorithms implemented in this paper includes the widely accepted Advanced Encryption Standard (AES) along with other established lightweight algorithms namely PRESENT, Light Encryption Device (LED) which are effective for resource constrained applications. A comparative performance analysis was carried out between the high level design approach and the traditional RTL style based on their FPGA and ASIC implementation.

Substitution-Box (S-BOX) is the most critical block in the Advanced Encryption Standard (AES) algorithm, consumes 75% of total power during encryption. The primary idea to implement S-BOX is to have a unique byte substitution. In this paper 4 different architecture of SBOX discussed; (a) look-up table or ROM based S-BOX contains a pre-computed value stored at defined address (b) modified look-up table based approach which uses decoders and multiplexer makes overall substitution faster (c) computational method has composite field architecture to compute the substitution byte (d) blend of computational method and look up table method where pre-computed multiplicative inverse values are stored in lookup table to reduce power consumption. Look up table based method requires a fetching circuit from a certain location, suffers from area overhead; to overcome that to be substituted values are divided into groups and using decoders and multiplexer that values will be fetched. The computational method requires complex computation result in high power consumption. To overcome that one particular module is pre-computed and stored in a look-up table in the last method. The overall objective of this paper is to implement S-box using different methods and to come up with method which is optimum as far as the area, power, delay parameters are concerned and security wise robust. In this work a comparative study of all these methods has been explored with CMOS 180 nm, 90 nm, and 45 nm technology node.

Rijndael was the finalist of Advanced Encryption Standard (AES) competition and Rijndael-128 with the 128-bit block size was selected as the standard. In this paper, we concentrate on the security of large-block Rijndael under impossible differential attack. First, the differential properties of S-box and MixColumn in Rijndael were analyzed to construct a 6-round impossible differential distinguisher of Rijndael-192. Based on the new distinguisher, the first impossible differential attack on 9-round Rijndael-192 was proposed. Then the flaws in the impossible differential attack on 10-round Rijndael-224 introduced by Minier in 2016 were presented. And a new impossible differential attack on 10-round Rijndael-224 was introduced in this paper. Finally, the optimal techniques such as: early abort technique, quick sort algorithm and time-memory tradeoff strategy could be used to improve the security of Rijndael-160 and Rijndael-256 under the impossible differential attack.

Encryption plays an important role in data security against third-party attacks and it is significant to safeguard sensitive data and personal information for the community. Within this era of technology, privacy and confidentiality are the essential considerations to be addressed as a result of the exponential development of the Internet. One of the main concerns involving software implementation of encryption algorithm is the possibility of slower processing when transmitting and receiving data which consequently will encounter low security level during process of encryption for real-time application. The focus of this paper is to match with the existing cryptography algorithm, 128-bit Advanced Encryption Algorithm and improving the processing speed for the design with hardware implementation. Real-time application is essential for today’s modern world and Field Programmable Gate Array approach is applied for this purpose. The optimization approaches include loop release, pipeline architecture and Look-Up-Table (LUT) which allow for exact synchronization in order to meet applications’ requirements in real time. The design is coded using the Verilog HDL and the hardware design is analyzed and tested with Altera Cyclone II-V in Quartus II and ModelSim. Through comparative analysis with previous implementation, the maximum throughput for this design is 31.37 Gbit/s for the encryption process can operate at 244.89 MHz. The complete 128-bit AES encryption cycle requires only 41 clock cycles to get the encrypted data.

Encryption algorithms such as Advanced Encryption Standard (AES) are known as symmetric encryption algorithms which use the same key for both encryption and decryption. These algorithms have a huge variety of applications such as for securing data and transferring files. They also have a key expansion algorithm which is used for expanding the given key. In AES the key expansion algorithm expands the given 128 bit key into 176 bytes which will then be used in the encryption process which spans for 10 rounds. This paper aims at making this process even more secure. This is implemented by including different steps to increase security in this key expansion process so that it becomes computationally infeasible to get the original key even if the adversary gets a hold of the different parts of the key. Current works suggest that there is a need for increased security in the key scheduling algorithm of the AES. It has also been tested to have inferior strict avalanche criteria in comparison with other contenders of the AES such as Serpent and Twofish. Usage of the concept of affine recurrence ensures this in the proposed model. In affine recurrence, no two outputs of the operation will have a relation between them. Another concept used is the AES Substitution Box (S-box), and this is done to ensure higher levels of confusion in the key scheduling process.

Information security has always been an important aspect of consideration in daily life communication and with the advent of COVID-19 and communication, including sensitive data like corporate files, personal data, etc., increasingly moving online, it has become more important than ever to provide secure communication methods. One such method is using encryption and steganography. Encryption is the process of converting ordinary plaintext data into an alternative form that is unreadable by perpetrators without authorization. Furthermore, steganography is the practice of hiding a file, message, video, or image within another such file. In this paper, we introduce a web application that will enable the user to encrypt the data in a file of his choice and then hide it within a picture or GIF. This will provide the layman an application that is easy to use to communicate securely, even without extensive technical knowledge. The encryption algorithm used will be the AES-256 algorithm and the steganographic algorithm will be Syndrome-Trellis Codes (STCs) for their high embedding efficiency. The results display that the system designed offers a significant security level.

AES is the most widely accepted standard in cryptography as it is considered to be the most secure and safest cryptographic algorithm. But in today’s world even AES is susceptible to some form of malicious attacks like the Trojan horse injection. This paper proposes denial-of-service (DoS) Trojan horse injection attacks in AES-128 decryption algorithm and also discusses the effect of these DoS Trojans on the side-channel parameters, power consumption, and time delay. The proposed DoS Trojan horse injection attacks have minimal impact on the power consumed (in μW) and time delay (in ms) thus the chances of detecting these Trojans by side-channel analysis are very less.

There has been a significant rise in internet and wireless device users, raising the need for security to protect consumer data shared over open networks. Field Programmable Gate Arrays (FPGAs) are particularly desirable alternative for hardware implementation of cryptographic algorithm. This paper discusses hardware implementation of AES algorithm on a Field Programmable Gate Array (FPGA) platform with focus on high throughput and low area constraint. In the proposed design, an efficient pipelined architecture for AES encryption/decryption is realized using unrolled and external pipelining techniques. The proposed design is implemented on different families Virtex-5 and Spartan-6 of FPGA platform. This design obtained maximum throughput of 37.57 Gbps and 32.44 Gbps on Virtex-5 and Spartan-6, respectively. Along with throughput, it also got maximum frequency and high throughput per slice with significant number of slices.

In a communication channel, message transfer happens through a noisy medium which can introduce errors in the transmitted message. It is required to maintain an acceptable bit error rate for a reliable transmission. This can be handled by an efficient error control coding scheme. This paper discusses the hardware design of an error control decoder, namely turbo product code decoder. The iterative Chase-Pyndiah decoding algorithm has been used in the turbo decoder design. The decoder has been designed using both MATLAB and Verilog, and its performance has been analysed. To study the robustness of the decoder in dealing with different data types, performance analysis is done with both the received data and the encrypted version of the same. Advanced Encryption Standard (AES) has been used for the encryption process, and it is shown that there is only a negligible difference in the performance for both the data sets.

Internet of Things (IoT) devices are easily exposed to physical attacks; therefore, their design must consider authentication and encryption. Many authentication and encryption methods use algorithms such as advanced encryption standard (AES) and secure hash algorithm (SHA). A pseudo-random number generator (PRNG) can also be used for authentication and encryption, and linear feedback shift register (LFSR) provides an easy way to generate PRNGs. LFSR allows the mathematical generation of unique values ​​proportional to a given length. However, as LFSR is mathematically predictable, it is not used alone for this purpose. PingPong256 uses a variable clock for LFSR that can generate very long periods. However, LFSRs are still potentially at risk of being attacked by correlation analysis attacks. There are several methods to account these security issues, including chaos maps (such as logistic maps), SHA, and AES. This paper proposes a method of using logistic maps corresponding to PingPong256 and chaos maps. For this purpose, various PingPong256 configurations are proposed and compared to verify the effectiveness of the proposed method. The method was tested using NIST SP800-22.

Cryptography is becoming slowly but surely a more important feature of computer security. In every field of technology, there are major issues of security but these issues overcome by using cryptographic algorithms. Biometric images are used as input and then the features like shape, size, edge, and texture are extracted. This is done by applying feature extraction algorithms and advanced encryption standard algorithm on Fingerprints, Iris, faces, and palm print simultaneously. In this paper, we have explained the information about multimodal biometrics, limitations of the DES algorithm on the encryption process of multimodal biometric images, Solution to these problems, and the role of AES in multimodal. We have discussed the implementation of the AES algorithm by using MATLAB on parameters of captured images according to age and gender. Parameters such as key size, input size, time taken, simulation, memory requirement, CPU usage. Major issues in multimodal biometrics such as matching algorithm, time delay, FAR are also discussed.

For long, software-defined network (SDN) has been the new trend in the field of networking. Despite being way better than the traditional networking approach, security issues related to SDN are a major concern for technologists all over the globe. It has drawn great attention and is still a highly interesting field of study for network administrators. Among the various means suggested to overcome these security issues, working with securing Border Gateway Protocol (BGP) seems to be a feasible solution to securing SDN. BGP deals with transferring data between two autonomous systems by exchanging routing information between the systems. In this paper, we propose an efficient way to secure data transfer, through BGP, between two autonomous systems in SDN. This is achieved by encrypting data using Advanced Encryption Standard (AES) Encryption Algorithm. In order to prove its feasibility, AES data encryption algorithm is implemented on two hosts in SDN and data transfer is traced on Wireshark. Furthermore, we extend our study to conclude that SDN can be secured by encrypting data over BGP and then transferring it safely to the destination.

This paper presents results on modelling of AES encryption algorithm in terms of CPU execution time, considering different modelling techniques such as linear, quadratic, cubic and exponential mathematical models, each with the application of piecewise approximations. C#.net framework is used to implement this study. This study recommends quadratic piecewise approximation modelling as the most optimized model for modelling the CPU execution time of AES towards encryption of data files. The model proposed in this study can be extended to other encryption algorithms, besides taking them over a mobile cloud environment also.

Digital image transfer security is presently vital in image communications, as pictures are more and more utilized in industrial processes. It’s necessary to safeguard confidential image information from unauthorized access. Image security has become a vital downside, and privacy challenges are steadily increasing. Many strategies of knowledge protection and privacy were mentioned and developed. Coding is maybe the foremost obvious. Several methods of data protection and privacy were discussed and developed. Encryption is probably the most obvious. To protect valuable information from unwanted drives, image encryption is necessary. In this paper, we introduce information masking and digital image encryption that enhance the security of confidential data and digital images using LSB technology and the Advanced Encryption Standard (AES) algorithm. To hide data in the image, we use LSB technology, and to encrypt the embedded image, we use the AES algorithm.

Data deduplication method allows the cloud users to manipulate their cloud storage efficiently by avoiding the storage of certain repeated data having the same bandwidth. To ensure that the data is secure and confidential, and the data is stored by encrypting it. We can use various encryption types like the RSA, DES, and AES. Convergent encryption algorithm is commonly used to retrieve storage capacity and lower data upload throughput and yet poses two challenges. The first problem is that they might be unsafe for statistical attack. The other thing is that they have convergent key management problems. The current paper assists in the usage of key-sharing approach which is verified by the proof of ownership to rectify these problems. As in only the initial data uploader, the holder encrypts the data with a randomly selected convergent key and then disperses the key in the cloud, and the key can only be accessed by users who have the reported data. In the existing framework, we found out that in the convergent encryption, the key of any given data can be generated by anyone in a deterministic way. An attacker can generate a key from plaintext encrypt the plain text and check if the resulting cipher text is already existing or not. Thus to overcome the issues, we propose the much more secure Advanced Encryption Standard (AES) without the third-party administrator (TPA) and to reduce the burden of computational overhead on the admin. We have used the Zeus algorithm to stop the duplicate data string in the database. Zeus algorithm offers better deduplication process and work to reduce the computational overhead of the admin. Analysis shows that this design is more effective, and the proposed security model remains stable.

With the wide application of smart card, people’s demand for the security of smart card is increasing. The Advanced Encryption Standard (AES) algorithm in smart card itself is safe enough, but the encryption algorithm is still threatened by side-channel attacks due to time, power consumption, electromagnetic radiation, and other information leakage during operation. Aiming at the shortcomings of existing mask schemes in security, a smart card AES encryption NARMS mask against side-channel attack is proposed. This scheme calculates the random mask according to the random hamming weight value and random integer, selects three rounds of random selection and NARMS random mask strategy for protection in the first, second, and ninth rounds of AES algorithm, optimizes and improves the design of the random mask and the overall process of mask protection. The mask scheme designed in this paper is comprehensively compared with ordinary AES algorithm, fixed value mask scheme and rotating S-box masking scheme (RSM). Experiments show that this scheme can effectively resist the first- and second-order correlation power analysis (CPA) attacks and has high efficiency, thus ensuring the key security of AES algorithm and privacy security of smart card application.

Cryptography is the study of technique related to the aspect of data security. In this paper, we have proposed high-speed AES hardware architecture by using parallelism in the process. In addition, all 10 stages of the process are divided into pipeline stages. The generic AES has serial processing with pipelining, it runs the key module first to generate round key and save it in RAM, afterward it processes encryption or decryption block. In the modified method, we run key expansion and encryption or decryption block parallel in synchronization with clock. The module uses a register to store the current key and the register modify by process in each round. The overall module consists of key expansion, encryption, decryption and comparator blocks. This architecture has a clock generating circuit to provide a limited number of clock cycles to generic architecture to improve latching problems and provide synchronization. In this module, encryption output is given to decryption input and the decrypted output is compared with plain text (encryption input) to verify the overall process. NIST (National Institute of Standards and Technology) cases are predefined inside the module will be selected by test case bits, according to test case bit selection, the key and input will be selected and module generates corresponding output. A 128 bit AES algorithm synthesized using VHDL code and targeted into FPGA. Xilinx-ISE Design Suite version 14.7 is used for Synthesis and Simulation of the code. The design has been successfully tested on VIRTEX-6 and ARTIX-7 FPGA.

Cloud-based solutions allow companies to add tools to almost any existing or future infrastructure and for client data to be stored in one place. In this way, clients can generally get to the most recent and right form of information, be that as it may, checking the respectability of the information may prompt extreme overheads, which makes re-appropriating of the honesty check to outsiders an alluring alternative. This paper proposes an AES encryption method to protect the privacy of the user data and avoid data leakage during the third party handlings. We have also shown that the proposed solution does not increase the upload time and is in fact beneficial to the system’s performance

Due to widespread use of cloud computing, there is more and more data is being stored over cloud by the users every day in such case finding a solution for easy, secure and safe way to handle the data is necessary. So I have given the solution for such problem using some algorithms like AES encryption and similarity calculating algorithms. So, instead of searching directly using keyword here in this paper the approach is different. Here, I am using searching over the encrypted data which is much secure than the normal searching. In this project, I will be using AES encryption algorithm for encryption and Jaccard coefficient to find the similarity between the keywords. So after giving keyword, the encrypted keywords can be searched and user will be able to find the file over cloud. In this project, I have implemented and tested the solution to the problem of secure cloud computing. By using the fuzzy keyword searching over encrypted cloud computing and taking care of safety and secrecy of data files. This fuzzy keyword searching significantly increases the efficiency and safety over cloud. This is user friendly and easy to manage and require less resource. And the results are accurate enough to get exact files searched by the user. The efficiency is increased by approximated computing and it works great. In this solution, Jaccard coefficient is being used to calcite similarity and used two advanced techniques to make fuzzy keyword set, which achieves the great results. Where n-gram algorithm is used to generate the set of different length n-grams of any keyword which is going to be encrypted and is being stored over cloud. I have done security analysis and found out that this system is secure and reliable for modern cloud computing operations and file storage. This system achieves its proposed goal efficiently and results are shown for same.

In this paper, a noble biometric encryption technique is proposed for national security without the electronic chip by applying encrypted biometric data embedded in the Quick Response code (QR code) to secure the biometric data and personal information. The proposed biometric encryption method is achieved by applying the Advanced Encryption Standard (AES) algorithm and SHA-256 algorithm embedded into the QR code. This technique will enhance the safety and security for a biometric passport from unauthorized access without knowing the passport holder. The proposed method will provide more security for the border crossing and illegal immigrants.

The integration of wireless sensor nodes (WSNs) in the Internet of things (IoT) may generate new security challenges for establishing secure channels between low-power sensor nodes and Internet hosts. It includes a bunch of challenges right from redefining the existing ones from scratch of legacy codes to the current trend of proposing and designing new key establishment and authentication protocols. This paper is the successful attempt in resource constraint environment like wireless sensor network (WSN) to integrate cipher authentication and lightweight key management solutions in one bundle so that it can be deployed in IoT domains WSN is also a part of IoT. The cipher should be authenticated, lightweight, and should be flexible to use in the cryptanalysis. The cipher gives the better authentication techniques and performance but limited to the flexibility. Lightweight block cipher (LBC) uses less computation and secures the data with low computational cost and it is used for many purposes like radio-frequency identification (RFID) tags and sensor network nodes. Advanced Encryption Standard is applied in many devices for the encryption, but it cannot be applied to the smaller embedded devices like wearable devices, etc. LBC works for the many devices with low resources, and research on the LBC has been increased. In this research, Data Encryption Standard (DES) and analyzed algorithm are used to increase the efficiency in terms of solving time and Improved Fault Analysis (IAFA) is used to increases the security of the LBC in wireless sensor node for IoT.

In the present-day scenario, huge amount of data is available on Web due to which the current-day major challenge in the cloud computing is converting the data to knowledge which can be used in the industry for different reasons and on the other hand to attain the confidence of consumers by imposing privacy and security for generating constructive suggestions by agents in a multi-agent architecture using OLAP for eliminating regulatory constraints over sensitive data. In this paper, we are proposing a novel algorithm that uses basic AES while performing communication between distinct agents in a cloud computing environment.

This paper unfolds the development of an HDL model on the ASIC platform for the quicker and safer transmission of image data. Secure image encoding was facilitated by the DWT through image compression and AES through encryption. The DWT computation based on lifting scheme algorithm was developed and implemented on ASIC platform. An algorithm that can compute multi-level sub bands using 2D-DWT was developed. Based on compression ratio and data recovery, appropriate sub bands were chosen to reduce the computation time of the AES encryption. The DWT architecture was developed to facilitate high throughput and latency. The HDL model of the DWT architecture and the AES algorithm were developed and validated on the ASIC platform to identify the area, timing and power performance. The ASIC implementation was carried out using 56nm CMOS technology.

In today’s environment security becomes an important issue for both storage and transmission of multimedia data. Hence there is a need to secure the data from unauthorized access and to thwart the attack by the intruder in between transmission. Images play a great role for multimedia data. It depicts more information by visualization as compared to text data. The application of images in military communication, medical sciences, etc., requires high protection of image data only between the end users. Encryption is the process by which image is unreadable or in determined easily. AES (Advanced Encryption Standard) is an algorithm which is used to encrypt any multimedia data and is used vastly because of its high security. This paper proposes to use simple and simplified steps of the AES algorithm for image encryption. The proposed algorithm provides high randomness in image data for providing high security in minimum number of operations. Java has been used for the implementation.

The most convenient way of data acquisition in recent times is undoubtedly through remote sensing. Remote sensing data has shown substantial growth in terms of pliability, reliability, cost-effectiveness, speed and efficiency. However, the growth is prone to data breaches and attacks. The commonly employed method for data security is encryption and decryption. This paper proposes the secure transmission of remote sensed data by using AES (Rijndael) algorithm with 256-bit key as the underlying encryption algorithm.

The security of data transmitted has paramount significance in the exchange and storage of information. Cryptography provides a solution to a lot of real-world data security problems over digital communication channels. While cryptographic algorithms are not the only requirement for providing security, but these are the first step toward providing the required security over data transmission and communication. Cryptography is the science of keeping messages secure from unauthorized recipients. In this paper, we present a new cryptographic algorithm which is an amalgamated version of Pig Latin, a popular argot or jargon and RSA, one of the most popular asymmetric key cryptosystems. The modified Pig Latin involves a layer of encryption using the cryptographic algorithm RSA to provide better security than RSA alone, thereby increasing the security. The practical performance of the algorithm is analyzed in terms of its empirical computational complexity. There are several cryptographic algorithms which are used to secure information in the form of encryption and decryption. The running time of the proposed algorithm is compared with a present cryptographic algorithm AES-128. Because of the simplicity of the algorithm, it can be implemented for messaging applications used in mobile phones and to secure data stored on other small storage devices.

Reliability comes with security and security comes with latest technology and any technology is best suited for any application area until it possess a high security features. Security is considered to be one of the prominent feature which makes it more acceptable and deployable to diversified and multidisciplinary applications. The paper try to put forth an in depth review on various security aspects confining more on the security details related to cloud robotics. Cloud robotics is a term involved and emerged with the fusion of two dipole concepts namely cloud computing and robotics. Security flaws in these two technologies are the major concerns and can affect the cloud robotics. Cloud computing suffers from various type of vulnerabilities like Network based attacks, Data storage based attacks, Virtualization based attacks is also prone to operating system level attacks. The same way robotics also suffers from attacks namely denial of service attack, and dictionary attack etc. Thus it can be termed as that cloud robotics need to be safeguard from all such threats mentioned above. The draft in particular thus throws light on the different cryptographic algorithms: RSA (Rivest Shamir Andelmen), AES (Advanced Encryption Standard), ECC (Elliptic Curve Cryptography). Exclusive to the algorithms cited above, the article discusses few more methods and techniques concerning to security which can be aptly applied to cloud robotics to make it more safe and secure.

Vehicular Ad hoc Network (VANET) is a developing technology that provides traffic safety management and makes travelling convenient. The basic goal is to broadcast traffic-related information from one vehicle to other vehicle or from vehicle to Road Side Units (RSU) for offering safety in driving and prevent from road accidents. Security and privacy are required for transmitting the data. These data have to be prevented from various attacks on privacy and misuse of private data. In this paper, the proper mechanism for validating the data and eliminating the illegitimate user from the network is done using a symmetric cryptographic algorithm. The proposed method is an efficient privacy-preserving encryption scheme using Reduced Advanced Encryption Standard (R-AES). It reduces the time taken for encryption, computational complexity, energy consumption and memory requirement for storing keys. It is suitable for hardware implementation and secured against a brute force attack. Thus, the method attains data confidentiality, data privacy, authentication and data integrity. It is effective in terms of meting out time and attains maximum throughput. Finally, it is compared with an existing cryptographic algorithm.

Internet of Things (IoT) is now becoming a part of our life. Many devices are already connected, and more are expected to be deployed in the next coming years. The main concern for IoT is to provide a practical solution for security, privacy, and trust. The science of cryptography plays an important role for providing security in IoTs. AES algorithm is a well known symmetric key, block cipher that is highly secure. In this paper, we present an ultra-low power architecture for the AES cipher that is need for most IoT applications. The proposed architecture has been implemented on SCL 180 nm technology. We have used 4-bit serializer and deserializer (SerDes) to send and receive 128-bit data. The proposed AES architecture uses 32-bit data path in SubByte transformation, and it requires 44 clock cycles for encryption of 128-bit plaintext with a 128-bit cipher key. To deserialize 128-bit plaintext and cipher key, the architecture requires 32 clock cycles. Similarly, to serialize 128-bit ciphertext, 32 clock cycles are overlapped by 44 clock cycles required by AES module. By this, once, after the first 32 clock cycles, the use of SerDes does not affect on the throughput of the system. At 10 MHz the ASIC implementation of the proposed architecture on SCL 180 nm PDK consumes 52.2 \(\upmu \)W and 194.7 \(\upmu \)W power at 1 V and 1.8 V respectively and provides a throughput of 28 Mbps.

The vogue of globally manufacturing ICs is increasing rapidly due to which the systems are vulnerable to pernicious Trojan. A promising technique is needed to prevent systems from Trojan. The paper proposes a technique to protect system, in which unused spaces are filled with some dummy logic i.e., (any logic that does not interrupt the functioning of main circuitry). The rival could substitute the dummy logic with malicious Trojan. In order to thwart such situation AES encryption of 128 bit length of modified design is done. The proposed technique is implemented on Xilinx 10.1_ISE in family Automatic Sparton3 and device XA3S50 and comparison with other families of Xilinx is done. The modified design provides 100% protection from HT but not at the cost of performance and power penalties. The proposed technique requires same memory as needed by original circuit.

Communication channels, especially the ones in wireless environments need to be secured. But the use of cipher mechanisms in software is limited and cannot be carried out in hardware and mobile devices due to their resource constraints. This paper focuses on the implementation of Elliptic Curve Integrated Encryption Scheme (ECIES) cryptosystem over an elliptic curve of 163-bit key length with an AES cipher block based on the Diffie-Hellman (ECDH) key exchange protocol.