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The paper proposes a solution to the problem of choosing the size of a cluster in an ultralow latency network. This work is aimed at designing a method for choosing the size of the digital cluster in an ultralow latency network taking into account the lengths of connecting lines. If the linear dimension calculation is based only on the latency requirements without specifics of building the communication line, it negatively affects timing characteristics. This paper shows the method taking into account the communication line features and basing on the fractal dimension estimation of the road network. The proposed method could be used in planning and designing networks with ultralow latencies. Finally, a numerical experiment was carried out, based on the data of electronic maps, which showed that the assessment of the fractal dimension of roads in the network’s service area makes it possible to increase the accuracy of the size of the formed cluster. Moreover, the proposed method can allow you to reduce the error in estimating the length of connecting lines, which without using it can be on average about 30%.

Embedded software is increasingly being used with high reliability. However, the fault localization of embedded software is still largely dependent on the experience of engineers. Besides, faults in embedded software programs are not independent individuals; they are related to each other and affect each other, which may lead to more complex interaction behavior. These uncertainties render the traditional methods for single-fault localization with limited practical value. This paper has proposed a multiple-fault localization method to be applied to the embedded software, with emphasis on the cache-based program spectra-acquiring method and the hybrid clustering-based fault partition method. Through case studies on 108 groups of the subject program, it has been proved that the hybrid clustering-based fault partition method has significantly improved the effectiveness of multiple-fault localization in comparison with the traditional fault localization methods. Experiments on three embedded software programs in engineering have revealed that the cache-based program spectra-acquiring method saves nearly half of the running-time cost compared with the traditional spectrum-acquiring method based on real-time transmission. Therefore, the multiple-fault localization method proposed in this paper can be applied in embedded software debugging and testing in engineering.

Wireless sensor networks (WSN) have gradually integrated into the concept of the Internet of Things (IoT) and become one of the key technologies. This paper studies the optimization algorithm in the field of artificial intelligence (AI) and effectively solves the problem of node location in WSN. Specifically, we propose a hybrid algorithm WOA-QT based on the whale optimization (WOA) and the quasi-affine transformation evolutionary (QUATRE) algorithm. It skillfully combines the strengths of the two algorithms, not only retaining the WOA’s distinctive framework advantages but also having QUATRE’s excellent coevolution ability. In order to further save optimization time, an auxiliary strategy for dynamically shrinking the search space (DSS) is introduced in the algorithm. To ensure the fairness of the evaluation, this paper selects 30 different types of benchmark functions and conducts experiments from multiple angles. The experiment results demonstrate that the optimization quality and efficiency of WOA-QT are very prominent. We use the proposed algorithm to optimize the weighted centroid location (WCL) algorithm based on received signal strength indication (RSSI) and obtain satisfactory positioning accuracy. This reflects the high value of the algorithm in practical applications.

It has great advantages in data processing. Embedded microsystems are widely used in IoT devices because of their specific functions and hard decoding technology. This article adds a literary vocabulary semantic analysis model to the embedded microsystem to reduce power consumption and improve the accuracy and speed of the system. The main purpose of this paper is to improve the accuracy and speed of semantic analysis of literary vocabulary based on the embedded microsystem, combined with the design idea of Robot Process Automation (RPA) and adding CNN logic algorithm. In this paper, RPA Adam model is proposed. The RPA Adam model indicates that the vector in the vector contains not only the characteristics of its own node but also the characteristics of neighboring nodes. It is applied to graph convolution network of isomorphic network analysis and analyzes the types of devices that can be carried by embedded chips, and displays them with graphics. Through the results, we find that the error rate of the RPA Adam model is the same at different compression rates. Due to the different correlations between knowledge entities in different data sets, specifically, high frequency can maintain a low bit error rate of 10.79% when the compression rate is 4.85%, but when the compression rate of high frequency is only 60.32%, the error rate is as high as 11.26%, while the compression rate of low frequency is 23.51% when the error rate is 9.65%.

The existing programs inside the voice assistant machine prompt human-machine interaction in response to a request from a user. However, the crucial problem is that the machine often may not give a proper answer to the user or cannot work out the existing program execution efficiently. Therefore, this study proposes a novel transform method to replace the existing programs (called sample programs in this paper) inside the machine with newly generated programs through code transform model GPT-2 that can reasonably solve the problem mentioned above. In essence, this paper introduces a theoretical estimation in statistics to infer at least a number of generated programs as required so as to guarantee that the best one can be found within them. In addition, the proposed approach not only imitates a voice assistant system with filtering redundant keywords or adding new keywords to complete keyword retrieval in semantic database but also checks code similarity and verifies the conformity of the executive outputs between sample programs and newly generated programs. According to code checking and program output verification, the processes can expedite transform operations efficiently by removing the redundant generated programs and finding the best-performing generated program. As a result, the newly generated programs outperform the sample programs because the proposed approach reduces the number of code lines by 32.71% and lowers the program execution time by 24.34%, which is of great significance.

This paper presents an optimized geometric greedy router (GGR) based on quantum dot cellular automata (QCA) technology. The proposed structure of GGR is based on a spanning tree of the network. This type of communication does not require an IP address. It uses only local information and can be used in many communication devices. In this paper, we first describe the principal components of the router and then we present their QCA architecture. The QCA technology is the most likely alternative to replace conventional circuits (CMOS) due to their very low power consumption and high processing speed. To consider integration with other complex circuit, we have utilized QCA clock-phase-based technique for the proposed design architecture. The results obtained using the QCA designer tool exhibit the superiority of the presented architecture over the existing designs. The proposed structure shows a reduction of 30% reduction in occupied space. The power dissipation rate of the proposed design is analyzed by QCAPro tool to approve its reliability.

With the development of artificial intelligence technology, deep learning has been applied to automatic modulation classification (AMC) and achieved very good results. In this paper, we introduced an improved deep neural architecture for implementing radio signal identification tasks, which is an important facet of constructing the spectrum-sensing capability required by software-defined radio. The architecture of the proposed network is based on the Inception-ResNet network by changing the several kernel sizes and the repeated times of modules to adapt to modulation classification. The modules in the proposed architecture are repeated more times to increase the depth of neural network and the model’s ability to learn features. The modules in the proposed network combine the advantages of Inception network and ResNet, which have faster convergence rate and larger receptive field. The proposed network is proved to have excellent performance for modulation classification through the experiment in this paper. The experiment shows that the classification accuracy of the proposed method is highest with the varying SNR among the six methods and it peaks at 93.76% when the SNR is 14 dB, which is 6 percent higher than that of LSTM and 13 percent higher than that of MentorNet, Inception, and ResNet purely. Besides, the average accuracy from 0 to 18 dB of the proposed method is 3 percent higher than that of GAN network. It will provide a new idea for modulation classification aiming at distraction time signal.

Due to demand of information transfer through higher speed wireless communication network, it is time to think about security of important information to be transferred. Further, as these communication networks are part of open channel, to preserve the security of any Critical Information (CI) is really a challenging task in any real-time application. Data hiding techniques give more security and robustness of important CI against encryption or cryptographic software solutions. However, hardwired approach exhibits better solution not only in terms of reduction of complexity but also in terms of adaptive real-time output. This paper demonstrates frequency, Discrete Cosine Transform (DCT) domain Steganographic data hiding hardware solution for secret communication called Crypto-Stego-Real-Time (CSRT) System. The challenge is to design a secure algorithm keeping reliability of minimum distortion of original cover signal while embedding considerable amount of CI. Field Programmable Gate Array (FPGA) implementation shown in this paper is more secure, robust, and fast. Pipelining process while embedding enhances the speed of embedding, optimizes the memory utilization, and gives better Peak Signal to Noise Ratio (PSNR) and high robustness. Practically implemented hardware Steganographic solutions shown in this paper also give better performance than that of the current state-of-the-art hardware implementations.

User authentication is a process in which a user of a system proves his/her identity to acquire access permission. An effective user authentication method should be both secure and usable. In an attempt to achieve these two objectives, Bianchi et al. recently proposed novel unimodal PIN-entry methods that use either audio or vibration cues. This paper analyzes the security of their method, in particular, the vibration version of one of their proposals, Timelock. A probabilistic analysis and real attack experiment reveal that the security level guaranteed by Timelock is lower than that claimed in Bianchi et al.’s paper. As countermeasures to this problem, three PIN-entry methods are proposed and a usability study is performed. According to the result of this study, a simple modification may improve the security significantly while retaining the design philosophy of unimodal systems. In addition, the proposed methods address the PIN compatibility issue of Timelock and they can be used to enter a legacy numerical PIN without any change in the PIN.

Being easy to understand and simple to implement, substitution technique of performing steganography has gain wide popularity among users as well as attackers. Steganography is categorized into different types based on the carrier file being used for embedding data. The audio file is focused on hiding data in this paper. Human has associated an acute degree of sensitivity to additive random noise. An individual is able to detect noise in an audio file as low as one part in 10 million. Given this limitation, it seems that concealing information within audio files would be a pointless exercise. Human auditory system (HAS) experiences an interesting behavior known as masking effect, which says that the threshold of hearing of one type of sound is affected by the presence of another type of sound. Because of this property, it is possible to hide some data inside an audio file without being noticed. In this paper, the research problem for optimizing the audio steganography technique is laid down. In the end, a methodology is proposed that effectively resolves the stated research problem and finally the implementation results are analyzed to ensure the effectiveness of the given solution.

In order to achieve energy saving and reduce the total cost of ownership, green storage has become the first priority for data center. Detecting and deleting the redundant data are the key factors to the reduction of the energy consumption of CPU, while high performance stable chunking strategy provides the groundwork for detecting redundant data. The existing chunking algorithm greatly reduces the system performance when confronted with big data and it wastes a lot of energy. Factors affecting the chunking performance are analyzed and discussed in the paper and a new fingerprint signature calculation is implemented. Furthermore, a Bit String Content Aware Chunking Strategy (BCCS) is put forward. This strategy reduces the cost of signature computation in chunking process to improve the system performance and cuts down the energy consumption of the cloud storage data center. On the basis of relevant test scenarios and test data of this paper, the advantages of the chunking strategy are verified.

Spectral efficient transmission techniques are necessary and promising for future broadband wireless communications, where the quality of service (QoS) and/or max-min fair (MMF) of intended users are often considered simultaneously. In this paper, both the QoS problem and the MMF problem are investigated together for transmit beamforming in broadband multigroup multicast channels with frequency-selective fading characters. We first present a basic algorithm by directly using the results in frequency-flat multigroup multicast systems (Karipidis et al., 2008), namely, the approximation algorithms in this paper, for both problems, respectively. Due to high computational consumption nature of the approximation algorithms, two reduced-complexity algorithms for each of the two problems are proposed separately by introducing the time-frequency correlations. In addition, parameters in the new time-frequency formulations, such as the number of optimization matrix variables and the taps of the beamformer with finite impulse response (FIR) structure, can be used to make a reasonable tradeoff between computational burden and system performance. Insights into the relationship between the two problems and some analytical results of the computational complexity of the proposed algorithms are also studied carefully. Numerical simulations indicate the efficiency of the proposed algorithms.

The performance of opportunistic beamforming might be degraded if the number of users is small. This paper proposes an adaptive opportunistic beamforming technique for orthogonal frequency division multiple access systems, which can produce good results even with a small number of users. This paper also proposes a modified proportional fairness scheduling algorithm, which can further improve the performance of the proposed opportunistic beamforming technique.

Downlink transmission techniques for multiuser (MU) multiple-input multiple-output (MIMO) systems have been comprehensively studied during the last two decades. The well-known low complexity linear precoding schemes are currently deployed in long-term evolution (LTE) networks. However, these schemes exhibit serious shortcomings in scenarios when users’ channels are strongly correlated. The nonlinear precoding schemes show better performance, but their complexity is prohibitively high for a real-time implementation. Two-stage precoding schemes, proposed in the standardization process for 5G new radio (5G NR), combine these two approaches and present a reasonable trade-off between computational complexity and performance degradation. Before applying the precoding procedure, users should be properly allocated into beamforming subgroups. Yet, the optimal solution for user selection problem requires an exhaustive search which is infeasible in practical scenarios. Suboptimal user grouping approaches have been mostly focused on capacity maximization through greedy user selection. Recently, overlapping user grouping concept was introduced. It ensures that each user is scheduled in at least one beamforming subgroup. To the best of our knowledge, the existing two-stage precoding schemes proposed in literature have not considered overlapping user grouping strategy that solves user selection, ordering, and coverage problem simultaneously. In this paper, we present a two-stage precoding technique for MU-MIMO based on the overlapping user grouping approach and assess its computational complexity and performance in IoT-oriented 5G environment. The proposed solution deploys two-stage precoding in which linear zero forcing (ZF) precoding suppresses interference between the beamforming subgroups and nonlinear Tomlinson-Harashima precoding (THP) mitigates interuser interference within subgroups. The overlapping user grouping approach enables additional capacity improvement, while ZF-THP precoding attains balance between the capacity gains and suffered computational complexity. The proposed algorithm achieves up to 45% higher MU-MIMO system capacity with lower complexity order in comparison with two-stage precoding schemes based on legacy user grouping strategies.

Neural networks employ massive interconnection of simple computing units called neurons to compute the problems that are highly nonlinear and could not be hard coded into a program. These neural networks are computation-intensive, and training them requires a lot of training data. Each training example requires heavy computations. We look at different ways in which we can reduce the heavy computation requirement and possibly make them work on mobile devices. In this paper, we survey various techniques that can be matched and combined in order to improve the training time of neural networks. Additionally, we also review some extra recommendations to make the process work for mobile devices as well. We finally survey deep compression technique that tries to solve the problem by network pruning, quantization, and encoding the network weights. Deep compression reduces the time required for training the network by first pruning the irrelevant connections, i.e., the pruning stage, which is then followed by quantizing the network weights via choosing centroids for each layer. Finally, at the third stage, it employs Huffman encoding algorithm to deal with the storage issue of the remaining weights. Qatar University [IRCC-2020-009].

Traditionally, the High-Level Synthesis (HLS) for Field Programmable Gate Array (FPGA) devices is a methodology that transforms a behavioral description, as the timing-independent specification, to an abstraction level that is synthesizable, like the Register Transfer Level. This process can be performed under a framework that is known as Design Space Exploration (DSE), which helps to determine the best design by addressing scheduling, allocation, and binding problems, all three of which are NP-hard problems. In this manner, and due to the increased complexity of modern digital circuit designs and concerns regarding the capacity of the FPGAs, designers are proposing novel HLS techniques capable of performing automatic optimization. HLS has several conflicting metrics or objective functions, such as delay, area, power, wire length, digital noise, reliability, and security. For this reason, it is suitable to apply Multiobjective Optimization Algorithms (MOAs), which can handle the different trade-offs among the objective functions. During the last two decades, several MOAs have been applied to solve this problem. This paper introduces a comprehensive analysis of different MOAs that are suitable to perform HLS for FPGA devices. We highlight significant aspects of MOAs, namely, optimization methods, intermediate structures where the optimizations are performed, HLS techniques that are addressed, and benchmarks and performance assessments employed for experimentation. In addition, we show the analysis of how multiple objectives are optimized currently in the algorithms and which are the objective functions that are optimized. Finally, we provide insights and suggestions to contribute to the solution of major research challenges in this area.

Timing analysis and optimization is one of the key areas in modern VLSI design and has become bottleneck in designing multi-million gate systems. Consequently, computer-aided design research in this area has shown in a new renaissance after the advent of deep sub-micron IC technology and the accompanying restrictive performance constraints. Effects related to interconnect dominance has resulted in technical problems in areas such as floorplanning, placement, routing and performance prediction, and therefore has made accurate and effective timing analysis and optimization more challenging. The current special issue of VLSI DESIGN Journal is devoted to papers that provide high-quality ideas and results in critical areas related to the timing analysis and optimization for deep sub-micron IC. The first paper called, “Timing Challenges for Very Deep Sub-Micron (VDSM) IC” is by Lin et al. The paper presents current and future timing challenges for VDSM IC. It presents why traditional design flow failed in timing sign-off and how silicon-accurate timing tools are necessary to overcome timing challenges and limitations that cause timing convergence and capacity problems in VDSM IC technology. The second paper is by Dhaou et al. Its title is “Energy Efficient Signaling in DSM Technology.” The key idea is to combat crosstalk noise and to reduce the power consumption while driving the global wire at an optimal delay by reducing voltage swing with buffer insertion and resizing. In 0.25mm CMOS, over 60% of energy-saving can be achieved if supply voltage is reduced from 2.5 down to 1.5 V. The third paper is written by Chen et al., entitled “Simultaneous Buffer-Sizing and Wire-Sizing for Clock Tress Based on Lagrangian Relaxation.” In this paper, a Lagrangian relaxation algorithm for simultaneously optimizing delay, power, skew, area, and sensitivity in clock tree is presented. The effectiveness and accuracy of algorithm is demonstrated. The fourth paper is by Hu et al. Its title is “Performance Driven Global Routing Through Gradual Refinement.” The authors present a heuristic for interconnect global routing that can optimize routing congestion, delay and the number of bends that are oftenly competing objectives. In addition to exploiting timing constrained routing flexibility, a gradual refinement method is applied for simultaneous optimization on congestion, timing and the number of bends. Experiments on benchmarks confirm the effectiveness of this method. The fifth paper is written by Arunachalam et al and is entitled “Accurate Coupling-Centric Timing Analysis Incorporating Temporal and Functional Isolation.” This paper presents a timing analysis methodology TACO that can accurately bind the arrival times in the presence of coupling. The timing windows at the aggressor can be used to determine whether the aggressor can switch in conjunction with the victim. Results of industrial examples show that the proposed method actually helps in reducing pessimism in the timing analysis. The sixth paper is authored by Lee et al. and is entitled “CMOS Delay and Power Model Equations for Simultaneous Transistor and Interconnect Wire Analysis and Optimization.” Generalized delay and power equations are proposed in this paper for CMOS circuit optimization achieved by transistor and interconnect minimization. The equations help analyze the entire power-delay trade-off with less complexity and fast computation time. The seventh paper is written by Huang and is entitled “Improving the Timing of Extended Finite State Machines via Catalyst.” In this paper, a timing optimization technique for a complex finite state machine that consists of random logic and data operator is presented. The proposed technique based on the concept of catalyst adds a functionally redundant block to the original circuit so the timing critical paths are divided for speed improvement. The eighth paper is by Huang et al. Its title is “TimingDriven-Testable Convergent Tree Adders.” The tree structure of adders is normally unbalanced and therefore generates high fanout in timing critical paths that may cause racing and increase the delay. A timing optimization

Unmanned aerial vehicle (UAV) enabled mobile-edge computing (MEC) has been recognized as a promising approach for providing enhanced coverage and computation capability to Internet of Things (IoT), especially in the scenario with limited or without infrastructure. In this paper, we consider the UAV assisted partial computation offloading mode MEC system, where ground sensor users are served by a moving UAV equipped with computing server. Computation bits (CB) and computation efficiency (CE) are two vital metrics describe the computation performance of system. To reveal the CB-CE tradeoff, an optimization problem is formulated to maximize the weighted sum of the above two metrics, by optimizing the UAV trajectory jointly with communication resource, as well as the computation resource. As the formulated problem is non-convex, it is difficult to be optimally solved in general. To tackle this issue, we decouple it into two sub-problems: UAV trajectory optimization and resource allocation optimization. We propose an iterative algorithm to solve the two sub-problems by Dinkelbach’s method, Lagrange duality and successive convex approximation technique. Extensive simulation results demonstrate that our proposed resource allocation optimization scheme can achieve better computational performance than the other schemes. Moreover, the proposed alternative algorithm can converge with a few iterations.

With the evolution of smart cities, images are used in a wide range of services such as smart healthcare and surveillance. How to ensure that images are transmitted and shared securely is of paramount importance for smart cities. To this end, a secure and efficient scheme for image transmission is proposed in this paper, which uses sparse signal transformation (SST) and parallel compressive sensing (CS). The primary employed techniques are sparse signal transformation (SST), parallel CS, and diffusion-permutation operation. The compression performance is achieved by parallel CS, whereas the encryption performance is derived from SST, parallel CS, and diffusion-permutation procedure. SST is exploited to change energy information before CS sampling and incorporated into diffusion-permutation framework, which not only balances the security and the efficiency of the algorithm, but also improves the transmission efficiency of the cipher image. We introduce chaotic system to generate the measurement matrix, SST matrix, and diffusion matrix to improve security. Furthermore, numerical simulation results and theoretical analyses confirm the security performances and effectiveness of the proposed scheme.

The recent decade has witnessed an exponential surge of digital content, especially multimedia and its applications. The security requirements of these innovative platforms necessitate the significance of enhancing advanced encryption schemes. In this paper, a novel encryption scheme is presented for real-time audio applications. The framework of the proposed scheme is grounded on the principles of confusion and diffusion. The confusion incorporates nonlinearity by the application of Mordell elliptic curves (MEC) and a symmetric group of permutations S8. The endurance of the proposed scheme is further enriched through the application of chaotic maps. The proposed scheme is intended to cater requirements of real-time voice communications in defense applications particularly warzones. The adoption of a modular design and fusion of chaotic maps makes the algorithm viable for numerous real-time audio applications. The security can further be enriched by incorporating additional rounds and number of S-boxes in the algorithm. The security and resistance of the algorithm against various attacks are gaged through performance evaluation and security measurements. The audio encryption scheme has the ability to tolerate noise triggered by a channel or induced by an invader. The decryption was successful and the resultant output was audible for noisy data. The overall results depict that the proposed audio encryption scheme contains an excellent cryptographic forte with the minimum computational load. These characteristics allow the algorithm to be a hotspot for modern robust applications.

Heterogeneous systems have gained popularity due to the rapid growth in data and the need for processing this big data to extract useful information. In recent years, many healthcare applications have been developed which use machine learning algorithms to perform tasks such as image classification, object detection, image segmentation, and instance segmentation. The increasing amount of big visual data requires images to be processed efficiently. It is common that we use heterogeneous systems for such type of applications, as processing a huge number of images on a single PC may take months of computation. In heterogeneous systems, data are distributed on different nodes in the system. However, heterogeneous systems do not distribute images based on the computing capabilities of different types of processors in the node; therefore, a slow processor may take much longer to process an image compared to a faster processor. This imbalanced workload distribution observed in heterogeneous systems for image processing applications is the main cause of inefficient execution. In this paper, an efficient workload distribution mechanism for image processing applications is introduced. The proposed approach consists of two phases. In the first phase, image data are divided into an ideal split size and distributed amongst nodes, and in the second phase, image data are further distributed between CPU and GPU according to their computation speeds. Java bindings for OpenCL are used to configure both the CPU and GPU to execute the program. The results have demonstrated that the proposed workload distribution policy efficiently distributes the images in a heterogeneous system for image processing applications and achieves 50% improvements compared to the current state-of-the-art programming frameworks.

Digital image watermarking is an attractive research area since it protects the multimedia data from unauthorized access. For designing an efficient and robust digital image watermarking system, the trade-off among imperceptibility, robustness, capacity, and security must be maintained. Various studies regarding this concern have been performed to ensure these requirements by hybridizing different domains, such as spatial and transform domains. In this paper, we have presented an analytical study of the existing hybrid digital image watermarking methods. At first, we have given a standard framework for designing a hybrid method that ensures the basic design requirements of watermarking for various applications. After a brief literature review, we compared and analyzed the complexity of several existing hybrid methods in a tabular form. The limitations and applications of these methods are also highlighted. Finally, we summarized the challenges of the existing methods and concluded the study by giving future research directions.

In this paper, we propose an efficient cryptosystem for digital image encryption and authentication. The cryptosystem is a hybrid scheme that uses symmetric and asymmetric approaches. The first one is used to encrypt the host image by utilizing a chaos-based key generator. The second one is used to encrypt the initial secret key and the owner’s signature that permit authentication. The algorithm is evaluated and validated by its application on several types of standard images and tools such as the statistical analysis, the key, and the performance analysis. The results indicate that the proposed cryptosystem provides high performance and enhanced security. The NIST 800-22 is used for testing the pseudorandom numbers generation (PRNG). The obtained simulation results are better than those cited in the recent works in terms of execution time and security level and low computational complexity.

Blockchain is a new technology for processing complex and disordered information with respect to business and other industrial applications. This work is aimed at studying the consensus algorithm of blockchain to improve the performance of blockchain. Despite their advantages, the proof of stake (POS) algorithm and the practical Byzantine fault tolerance (PBFT) algorithm have high latency, low throughput, and poor scalability. In this paper, a blockchain hybrid consensus algorithm which combines advantages of the POS and PBFT algorithms is proposed, and the algorithm is divided into two stages: sortition and witness. The proposed algorithm reduces the number of consensus nodes to a constant value by verifiable pseudorandom sortition and performs transaction witness between nodes. The algorithm is improved and optimized from three dimensions: throughput, latency, and scalability. The experimental results show that the improved hybrid consensus algorithm is significantly superior to the previous single algorithms for its excellent scalability, high throughput, and low latency.

Developing the formal model based on the Event-B design pattern is an excellent method to improve the development efficiency of the embedded control system and improve the reusability of the formal model. However, the instantiation of the Event-B design pattern requires the manual writing of a large number of model codes, which brings a great deal of learning cost and coding burden to the engineering staff. In this paper, we propose a modelling approach for formal development of control systems based on the application of iUML-B state machine patterns to model the four synchronization patterns of the typical control system. Then, we use the instantiation of iUML-B pattern state machine to establish a typical multilevel control system's Event-B model. The simulation results show that the event trace of the model obtained using our method is the same as that of the corresponding model obtained using the traditional Event-B design pattern. Compared with the traditional Event-B design pattern method, our method can greatly reduce the manual coding burden in the modelling process. The system model expressed using the iUML-B pattern state machine can be easily mapped to the labelled transition system so as to verify the behavioural properties of the model.

Intensive studies have been done to get robust encryption algorithms. Due to the importance of image information, optical encryption has played a vital role in information security. Many optical encryption schemes have been proposed but most of them suffer from poor robustness. In this paper six proposed algorithms will be presented for optical encryption to be robust to severe attacks: composite attack. Three of these approaches are based on one level Discrete Wavelet Transform (DWT) and the others are based on Wavelet Packet (WP). Not only will new techniques be presented but also a new proposed chaotic map has been developed as random keys for all algorithms. After extensive comparative study with some traditional techniques, it has been found that the novel algorithms have achieved better performance versus conventional ones. Also it has been found that WP based algorithms have achieved better performance than DWT based ones against severe composite attacks.

The field of nanosatellites is constantly evolving and growing at a very fast speed. This creates a growing demand for more advanced and reliable EDAC systems that are capable of protecting all memory aspects of satellites. The Hamming code was identified as a suitable EDAC scheme for the prevention of single event effects on-board a nanosatellite in LEO. In this paper, three variations of Hamming codes are tested both in Matlab and VHDL. The most effective version was Hamming [16, 11, 4]2. This code guarantees single-error correction and double-error detection. All developed Hamming codes are suited for FPGA implementation, for which they are tested thoroughly using simulation software and optimized.

DOI: 10.1155/2016/1370259 Texture analysis methods are widely used to characterize breast masses in mammograms. Texture gives information about the spatial arrangement of the intensities in the region of interest. This information has been used in mammogram analysis applications such as mass detection, mass classification, and breast density estimation. In this paper, we study the effect of factors such as pixel resolution, integration scale, preprocessing, and feature normalization on the performance of those texture methods for mass classification. The classification performance was assessed considering linear and nonlinear support vector machine classifiers. To find the best combination among the studied factors, we used three approaches: greedy, sequential forward selection (SFS), and exhaustive search. On the basis of our study, we conclude that the factors studied affect the performance of texture methods, so the best combination of these factors should be determined to achieve the best performance with each texture method. SFS can be an appropriate way to approach the factor combination problem because it is less computationally intensive than the other methods.