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With the recent advancements in high-performance computing, convolutional neural networks (CNNs) have achieved remarkable success in various vision tasks. However, along with improvements in model accuracy, the size and computational complexity of the models have significantly increased with the increasing number of parameters. Although graphics processing unit (GPU) platforms equipped with high-performance memory and specialized in parallel processing are commonly used for CNN processing, the significant power consumption presents challenges in their utilization on edge devices. To address these issues, research is underway to design CNN models using field-programmable gate arrays (FPGAs) as accelerators. FPGAs provide a high level of flexibility, allowing efficient optimization of convolution operations, which account for a significant portion of the CNN computations. Additionally, FPGAs are known for their low power consumption compared to GPUs, making them a promising energy-efficient platform. In this paper, we review and summarize various approaches and techniques related to the design of FPGA-based CNN accelerators. Specifically, to comprehensively study CNN accelerators, we investigate the advantages and disadvantages of various methods for optimizing CNN accelerators and previously designed efficient accelerator architectures. We expect this paper to serve as an important guideline for future hardware research in artificial intelligence. [ABSTRACT FROM AUTHOR]

Bit-serial neural network accelerators address the growing need for compact and energy-efficient deep learning tools. Traditional neural network accelerators, while effective, often grapple with issues of size, power consumption, and versatility in handling a variety of computational tasks. To counter these challenges, this paper introduces an approach that hinges on the integration of bit-serial processing with advanced dataflow techniques and architectural optimizations. Central to this approach is a column-buffering (CB) dataflow, which significantly reduces access and movement requirements for the input feature map (IFM), thereby enhancing efficiency. Moreover, a simplified quantization process effectively eliminates biases, streamlining the overall computation process. Furthermore, this paper presents a meticulously designed LeNet-5 accelerator leveraging a convolutional layer processing element array (CL PEA) architecture incorporating an improved bit-serial multiply–accumulate unit (MAC). Empirically, our work demonstrates superior performance in terms of frequency, chip area, and power consumption compared to current state-of-the-art ASIC designs. Specifically, our design utilizes fewer hardware resources to implement a complete accelerator, achieving a high performance of 7.87 GOPS on a Xilinx Kintex-7 FPGA with a brief processing time of 284.13 μs. The results affirm that our design is exceptionally suited for applications requiring compact, low-power, and real-time solutions. [ABSTRACT FROM AUTHOR]

Copyright of Acta Scientiarum Naturalium Universitatis Pekinensis is the property of Editorial Office of Acta Scientiarum Naturalium Universitatis Pekinensis and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Deep learning has brought great development to radar emitter identification technology. In addition, specific emitter identification (SEI), as a branch of radar emitter identification, has also benefited from it. However, the complexity of most deep learning algorithms makes it difficult to adapt to the requirements of the low power consumption and high-performance processing of SEI on embedded devices, so this article proposes solutions from the aspects of software and hardware. From the software side, we design a Transformer variant network, lightweight convolutional Transformer (LW-CT) that supports parameter sharing. Then, we cascade convolutional neural networks (CNNs) and the LW-CT to construct a one-dimensional-CNN-Transformer(1D-CNN-Transformer) lightweight neural network model that can capture the long-range dependencies of radar emitter signals and extract signal spatial domain features meanwhile. In terms of hardware, we design a low-power neural network accelerator based on an FPGA to complete the real-time recognition of radar emitter signals. The accelerator not only designs high-efficiency computing engines for the network, but also devises a reconfigurable buffer called "Ping-pong CBUF" and two-level pipeline architecture for the convolution layer for alleviating the bottleneck caused by the off-chip storage access bandwidth. Experimental results show that the algorithm can achieve a high recognition performance of SEI with a low calculation overhead. In addition, the hardware acceleration platform not only perfectly meets the requirements of the radar emitter recognition system for low power consumption and high-performance processing, but also outperforms the accelerators in other papers in terms of the energy efficiency ratio of Transformer layer processing. [ABSTRACT FROM AUTHOR]

Graph convolution networks (GCN) have demonstrated success in learning graph structures; however, they are limited in inductive tasks. Graph attention networks (GAT) were proposed to address the limitations of GCN and have shown high performance in graph-based tasks. Despite this success, GAT faces challenges in hardware acceleration, including: 1) The GAT algorithm has difficulty adapting to hardware; 2) challenges in efficiently implementing Sparse matrix multiplication (SPMM); and 3) complex addressing and pipeline stall issues due to irregular memory accesses. To this end, this paper proposed SH-GAT, an FPGA-based GAT accelerator that achieves more efficient GAT inference. The proposed approach employed several optimizations to enhance GAT performance. First, this work optimized the GAT algorithm using split weights and softmax approximation to make it more hardware-friendly. Second, a load-balanced SPMM kernel was designed to fully leverage potential parallelism and improve data throughput. Lastly, data preprocessing was performed by pre-fetching the source node and its neighbor nodes, effectively addressing pipeline stall and complexly addressing issues arising from irregular memory access. SH-GAT was evaluated on the Xilinx FPGA Alveo U280 accelerator card with three popular datasets. Compared to existing CPU, GPU, and state-of-the-art (SOTA) FPGA-based accelerators, SH-GAT can achieve speedup by up to 3283 × , 13 × , and 2.3 ×. [ABSTRACT FROM AUTHOR]

Specific workloads are increasingly offloaded to accelerators such as a graphic processing unit (GPU) and field-programmable gate array (FPGA) for real-time processing and computing efficiency. Because accelerators are expensive and consume much power, it is desirable to increase the efficiency of accelerator utilization by sharing accelerators among multiple servers over a network. However, task offloading over a network has the problem of latency due to network processing overhead in remote offloading. This paper proposes a low-latency system for accelerator offloading over a network. To reduce the overhead of remote offloading, we propose a system composed of (1) fast recombination processing of chunked data with a simple protocol to reduce the number of memory copies, (2) polling-based packet receiving check to reduce overhead due to interrupts in interaction with a network interface card, and (3) a run-to-completion model in network processing and accelerator offloading to reduce overhead with context switching. We show that the system can improve performance by 66.40% compared with a simple implementation using kernel protocol stack and confirmed the performance improvement with a virtual radio access network use case as a low-latency application. Furthermore, we show that this performance can also be achieved in practical usage in data center networks. [ABSTRACT FROM AUTHOR]

Recently, the neural networks with convolution computation is widely used for image classification and recognition. For real-time implementation, the video buffer is required to store the image temperately. However, traditional buffers like CLSB (content line shift buffer) may experience delays during the read process, particularly when encountering line breaks or image changes. As for N × N convolution, the delay time is N−1 clocks for every row changing. As the image width is W, the delay time is 2W + N clocks for every frame changing. These delays can impact the efficiency and performance of the neural network. To overcome this challenge, this paper presented novel buffer design to avoid the delay at the line ends and frame change. By proactively fetching data ahead of time, the buffer can dynamically schedule the read operation and ensure that the subsequent data are correctly placed for efficient processing. This improvement in read latency contributes to enhanced performance and better utilization of computational resources within the hardware system. Then the full convolutional network accelerator is implemented with the fast buffer design and common computational kernel to save the hardware cost based on LeNet model. The results show that the accuracy can achieve 99.1% with MNIST dataset verification. By eliminating the waiting time, the modified buffer allows for more efficient processing in the image, and the fame rate for a computer vision can achieve 46 per second, to meet the real-time requirement. [ABSTRACT FROM AUTHOR]

This paper conducts a comprehensive study on intermittent computing within IoT environments, emphasizing the interplay between different dataflows—row, weight, and output—and a variety of non-volatile memory technologies. We then delve into the architectural optimization of these systems using a spatial architecture, namely IDEA, with their processing elements efficiently arranged in a rhythmic pattern, providing enhanced performance in the presence of power failures. This exploration aims to highlight the diverse advantages and potential applications of each combination, offering a comparative perspective. In our findings, using IDEA for the row stationary dataflow with AlexNet on the CIFAR10 dataset, we observe a power efficiency gain of 2.7% and an average reduction of 21% in the required cycles. This study elucidates the potential of different architectural choices in enhancing energy efficiency and performance in IoT systems. [ABSTRACT FROM AUTHOR]

This paper presents a review of scientific and technical literature on the main production methods, various fields of application, and use of unsymmetrical ureas as an accelerator for the curing processes of epoxy compositions. Mechanisms of reactions between ureas and the widely used latent hardener dicyandiamide are presented, and the characteristics of resulting epoxy resins, as well as prepregs based on them, are considered. The possibility of using substituted ureas as an independent cross-linking agent for epoxy resins is mentioned. [ABSTRACT FROM AUTHOR]

The national institute of standards and technology (NIST) has presented its draft of the module-lattice-based key-encapsulation mechanism standard (MLBKEMS), choosing cryptographic suite for algebraic lattices (CRYSTALS)- Kyber as the base encryption. Existing hardware implementations of modern cryptography will need to process the new standard efficiently. The primary process in CRYSTALS-Kyber key-encapsulation mechanism (KEM) is the number theoretic transform (NTT), which requires heavy computing power. This paper contributes an efficient hardware accelerator for NTT and inverse NTT (INTT) by CRYSTAL-Kyber parameters. The proposed design utilizes the K-RED algorithm for reducing polynomial multiplication. It also incorporates the Brent-Kung method for efficient modular addition and subtraction operation with an address generator to control the sequences of computation. On the Xilinx Artix 7 field programmable gate array (FPGA), our design achieves 262 MHz clock speed, utilizing only 1405 LUTs. [ABSTRACT FROM AUTHOR]

The paper describes the design of a prototype magnetic field compensator intended to eliminate the influence of the edge magnetic field of the S-25P Pakhra accelerator magnet, Lebedev Physical Institute, on the electron beam during its output. The results of the study showed that this design could reduce an external magnetic field of B0 ~ 0.1 T to zero values inside the prototype. [ABSTRACT FROM AUTHOR]

High-performance sparse matrix multipliers are essential for deep learning applications, and as big data analytics continues to evolve, specialized accelerators are also needed to efficiently handle sparse matrix operations. This paper proposes a modified, configurable, outer product based architecture for sparse matrix multiplication, and explores design space of the proposed architecture. The performance of various architecture configurations has been examined for input samples with similar characteristics. The proposed architecture has been implemented on Xilinx Kintex-7 FPGA using 32-bit single precision floating-point arithmetic and also in 8-bit, 16-bit and 32-bit fixed-point arithmetic formats. The effect of quantization in the proposed architecture has been analyzed extensively and the results have been reported. The performance of the proposed architecture has been compared with state-of-the-art implementations, and an improvement of 9.21% has been observed in the performance. [ABSTRACT FROM AUTHOR]

Copyright of Journal Of Sichuan University (Natural Sciences Division) / Sichuan Daxue Xuebao-Ziran Kexueban is the property of Editorial Department of Journal of Sichuan University Natural Science Edition and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

FPGAs facilitate prototyping and debug, and recently accelerate full-stack simulations due to their rapid turnaround time (TAT). However, this TAT is restrictive in exhaustive design space explorations of parameterized RTL generators, especially DNN accelerators that unleash an explosive full-stack search space. This paper presents Quickloop, an efficient and scalable framework to enable FPGA-accelerated exploration. Quickloop first abstracts away the cumbersome flow of RTL generation, software stack, FPGA toolflow, workload execution and metrics extraction by wrapping these stages into isolated Quicksteps, featuring cascadability, scalability, and replay. Then, we analytically minimize the FPGA toolflow TAT via a novel, data-driven strategy that intelligently utilizes build fragments from previous iterations, enhancing the loop efficiency and simultaneously lowering the toolflow's compute utilization. Quickloop is built around the OpenAI Gym environment framework and thus supports drop-in regression and reinforcement learning explorations. With a Quickloop around a reference Berkeley's Gemmini DNN accelerator, we exhaustively explore its parameter space and discover complex performance patterns, based on full-stack simulation of Imagenet benchmarks as a workload. Compared to conventional FPGA toolflow, we further show that Quickloop effectively reduces episodal time by above 30%, as the episode approaches realistic lengths. • Machine Learning. • Accelerators. • Systolic Array. • Design Space Exploration. [ABSTRACT FROM AUTHOR]

Linear optics parameters are often estimated using turn-by-turn (TbT) data. In-plane beta functions, which are the most common measurement objectives, can be estimated from the amplitudes or phases of TbT data, providing an overall characterization of the linear lattice. In addition to estimating uncoupled Twiss parameters, TbT data can also be utilized for characterizing coupled linear motion. We investigate several methods for constructing a full normalization matrix at each beam position monitor (BPM). BPMs provide information on beam centroid transverse coordinates, but direct observation of transverse momenta is not available. To estimate momenta, one can use a pair of BPMs or fit data obtained from several BPMs. By using both coordinates and momenta, it is possible to fit the one-turn matrix (or its power) at each BPM, allowing for the computation of coupled Twiss parameters. Another approach involves the minimization of side peak amplitudes in the spectrum of normalized complex coordinates. Similarly, the normalization matrix can be estimated by fitting linear coupled invariants. In this study, we derive and utilize a special form of the normalization matrix, which remains non-singular in the zero coupling limit. Coupled Twiss parameters can be obtained from the normalization matrix. The paper presents the results of applying and comparing these methods to both modeled and measured VEPP-4M TbT data, demonstrating effective estimation of coupled Twiss parameters. [ABSTRACT FROM AUTHOR]

Two water-soluble block copolymers composed of acrylic acid (AA), 2-acrylamido-2-methylpropane sulfonic acid (AMPS), and optionally maleic anhydride (MAH) were synthesized through ammonium persulfate-catalyzed free radical polymerization in water. The introduction of aluminum sulfate (AS) into the resulting mixtures significantly reduced the setting times of the paste and enhanced the mechanical strength of the mortar compared to both the additive-free control and experiments facilitated solely by pure AS. This improvement was primarily attributed to the inhibition of rapid Al3+ hydrolysis, which was achieved through coordination of the synthesized block copolymers, along with the formation of newly identified hydrolytic intermediates. Notably, the ternary copolymer (AA–AMPS–MAH) exhibited superior performance compared to that of the binary copolymer (AA–AMPS). In the early stages of cement setting, clusters of ettringite (AFt) were found to be immobilized over newly detected linkage phases, including unusual calcium silicate hydrate and epistilbite. In contrast to the well-documented role of polymers in retarding cement hydration, this study presents a novel approach by providing both accelerating and hardening agents for cement setting, which has significant implications for the future design of cement additives. [ABSTRACT FROM AUTHOR]

The shielded pair resonator method is a useful tool in the measurement of accelerator components, such as the beam screens used in the Large Hadron Collider (LHC), the High-Luminosity (HL) LHC, or future accelerators. It can measure the resistive losses at several frequency points by separating the resistive losses on the sample from other sources of losses. We built a new resonator to be inserted into a superconducting dipole magnet (peak magnetic field of 9.5 T) and to measure the surface resistance of beam screens, such as LHC beam screens coated with amorphous carbon (a-C). The device can measure surface resistance at any temperature between 4.2 K and 300 K, in the frequency range of 400 MHz to 1600 MHz. We conducted the first surface resistance measurements of two a-C coated beam screens at 4.2 K and showed that the 200 nm to 400 nm titanium underlayer plus 50 nm a-C only has a limited effect on the surface resistance. This first result supports the choice of this coating as baseline for the HL-LHC triplets magnets upgrade. The resonator will have an important role in the characterization of next-generation beam screens, such as a beam screen with laser-engineered surface structure (LESS). Further measurements of the LHC beam screen in the presence of magnetic fields up to 9.5 T and throughout the full temperature range are going to be reported separately. [ABSTRACT FROM AUTHOR]

High-Efficiency Video Coding (HEVC) is a video compression standard designed to improve video compression efficiency compared to its predecessor, Advanced Video Coding (AVC). HEVC provides approximately twice the compression efficiency compared to the AVC. In the HEVC system, the most computational complexity module is the Motion Estimation (ME). ME module helps reduce redundancy by compensating for motion during video compression. However, the computational complexity makes it a bottleneck in the design of high-resolution video encoders. This paper proposes an efficient architecture for the Integer ME (IME) module of the HEVC encoder. The proposed architecture introduces an efficient memory usage scheme to support the Full Search motion search algorithm. The full pipeline architecture includes 4096 Processing Elements (PE) and an adder tree to compute the Sum of Absolute Difference (SAD) for every Prediction Unit (PU) partition. The proposed architecture was designed and implemented on Xilinx Virtex-7 XC7VX550T FPGA. Our design achieved up to 275 FPS and approximately 10 FPS at 4 K video for the Search Regions of [Formula: see text] and [Formula: see text] pixels, respectively.

Graph convolution networks (GCN) have demonstrated success in learning graph structures; however, they are limited in inductive tasks. Graph attention networks (GAT) were proposed to address the limitations of GCN and have shown high performance in graph-based tasks. Despite this success, GAT faces challenges in hardware acceleration, including: 1) The GAT algorithm has difficulty adapting to hardware; 2) challenges in efficiently implementing Sparse matrix multiplication (SPMM); and 3) complex addressing and pipeline stall issues due to irregular memory accesses. To this end, this paper proposed SH-GAT, an FPGA-based GAT accelerator that achieves more efficient GAT inference. The proposed approach employed several optimizations to enhance GAT performance. First, this work optimized the GAT algorithm using split weights and softmax approximation to make it more hardware-friendly. Second, a load-balanced SPMM kernel was designed to fully leverage potential parallelism and improve data throughput. Lastly, data preprocessing was performed by pre-fetching the source node and its neighbor nodes, effectively addressing pipeline stall and complexly addressing issues arising from irregular memory access. SH-GAT was evaluated on the Xilinx FPGA Alveo U280 accelerator card with three popular datasets. Compared to existing CPU, GPU, and state-of-the-art (SOTA) FPGA-based accelerators, SH-GAT can achieve speedup by up to 3283$ \times $, 13$ \times $, and 2.3$ \times $.

High-performance sparse matrix multipliers are essential for deep learning applications, and as big data analytics continues to evolve, specialized accelerators are also needed to efficiently handle sparse matrix operations. This paper proposes a modified, configurable, outer product based architecture for sparse matrix multiplication, and explores design space of the proposed architecture. The performance of various architecture configurations has been examined for input samples with similar characteristics. The proposed architecture has been implemented on Xilinx Kintex-7 FPGA using 32-bit single precision floating-point arithmetic and also in 8-bit, 16-bit and 32-bit fixed-point arithmetic formats. The effect of quantization in the proposed architecture has been analyzed extensively and the results have been reported. The performance of the proposed architecture has been compared with state-of-the-art implementations, and an improvement of 9.21% has been observed in the performance.

In a fusion reactor, the plasma based on a deuterium-tritium reaction generates high energy neutron flux interacting with the materials of the plasma facing components. In order to study the irradiated behavior of these materials, the International Fusion Materials Irradiation Facility (IFMIF) was conceived to generate these fusion relevant neutrons through d -Li stripping source. IFMIF is presently in its Engineering Validation and Engineering Design Activities (EVEDA) phase under the Broader Approach agreement signed between EURATOM and Japanese Government in 2007. This agreement mandates the IFMIF/EVEDA project to validate the design of the different systems of IFMIF and to produce an integrated engineering design of IFMIF, together with the data necessary for future decisions on its construction and operation. While the Engineering Validation Activity (EVA) of the Lithium Target Facility and the Test Facility was completed by constructing prototypes, the EVA of the Accelerator Facility with the Linear IFMIF Prototype Accelerator (LIPAc) is still on-going at the Rokkasho Fusion Institute, Japan. This paper overviews the achievements in the previous phase ended on 31 March 2020 and the progress in the current phase to complete the commissioning of the LIPAc. [ABSTRACT FROM AUTHOR]

Polynomial multiplications based on the number theoretic transform (NTT) are critical in lattice-based post-quantum cryptography algorithms. Therefore, this paper presents a platform-agnostic unified hardware accelerator design (Unif-NTT) to compute the forward and inverse operations of the NTT for the CRYSTALS-Kyber algorithm. Moreover, a unified design (Unif-BU) of the Cooley-Tukey and Gentleman-Sande butterflies is presented using two adders, multipliers, subtractors, routing multiplexers and barret-based modular reduction units. Finally, a dedicated controller is implemented for efficient control functionalities. The implementation results are realized on field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) platforms. The Unif-NTT requires 1664 and 1792 clock cycles for one forward and inverse NTT computations, respectively. It can operate up to a maximum frequency of $212MHz$ and $2.5GHz$ over Virtex-7 FPGA and 28nm ASIC platforms, respectively. The Unif-NTT is 26% more efficient in Area-Time-Product compared to the most area-optimized NTT accelerator from the state-of-the-art. The Unif-NTT design is suited for applications that demand reasonable hardware resources with processing speed.

We propose in this paper an efficient FALCON accelerator called EFX based on a HW/SW co-design where FALCON is a post-quantum cryptographic (PQC) scheme tailored as a digital signature algorithm (DSA). Our findings reveal that FALCON exhibits unique characteristics and structures which distinguish it from other PQC-DSAs. A key finding is that, unlike its counterparts, FALCON doesn’t prioritize a single, time-consuming task; instead, it processes a variety of tasks with comparable execution times. Consequently, the conventional methods focusing on accelerating dominant few tasks, which are generally effective for other algorithms, prove less efficient for FALCON, especially concerning the minimization of the silicon area used. To overcome this, we strategically focus on the granular optimization of lower-level operations rather than on broader functional segments, aiming to boost performance while conserving hardware space. Moreover, to mitigate the potential degradation due to limitation of hardware resources, we have implemented a pipelined execution strategy for the FALCON functions and refined the sampling function–a critical task that is challenging to accelerate due to inherent sequential algorithm–enabling it to run concurrently on both software and hardware, thus reducing latency. Our hardware design, synthesized at $300MHz$ using Samsung’s $28nm$ and $45nm$ process technologies, demonstrates superior performance in generating FALCON signatures, with a $3.58 \times $ improvement in clock cycles over an existing hardware accelerator. EFX occupies 38K $um ^{2}$ and 74K $um ^{2}$ for $28nm$ and $45nm$ processes, respectively, comparatively small compared to other PQC accelerators.

Deep learning has brought great development to radar emitter identification technology. In addition, specific emitter identification (SEI), as a branch of radar emitter identification, has also benefited from it. However, the complexity of most deep learning algorithms makes it difficult to adapt to the requirements of the low power consumption and high-performance processing of SEI on embedded devices, so this article proposes solutions from the aspects of software and hardware. From the software side, we design a Transformer variant network, lightweight convolutional Transformer (LW-CT) that supports parameter sharing. Then, we cascade convolutional neural networks (CNNs) and the LW-CT to construct a one-dimensional-CNN-Transformer(1D-CNN-Transformer) lightweight neural network model that can capture the long-range dependencies of radar emitter signals and extract signal spatial domain features meanwhile. In terms of hardware, we design a low-power neural network accelerator based on an FPGA to complete the real-time recognition of radar emitter signals. The accelerator not only designs high-efficiency computing engines for the network, but also devises a reconfigurable buffer called “Ping-pong CBUF” and two-level pipeline architecture for the convolution layer for alleviating the bottleneck caused by the off-chip storage access bandwidth. Experimental results show that the algorithm can achieve a high recognition performance of SEI with a low calculation overhead. In addition, the hardware acceleration platform not only perfectly meets the requirements of the radar emitter recognition system for low power consumption and high-performance processing, but also outperforms the accelerators in other papers in terms of the energy efficiency ratio of Transformer layer processing.

Triethanolamine (TEA) is a multifunctional organic additive, applied chiefly to a grinding aid and accelerator for cement. Its effect on cement paste in a sulfate-rich environment remains still unclear and elusive. In this paper, the expansion and mechanical performance of cement paste under external sulfate attack were measured. Thermodynamic model lent itself to estimate the correlation between triethanolamine and generated products content ahead of quantified phase analysis. The transformation of internal component was surveyed by multiple technologies of thermal gravimetric (TG), scanning electron microscope (SEM), X-ray diffraction (XRD), and nuclear magnetic resonance (NMR), while inductively coupled plasma (ICP) was applied to investigate the evolution of interstitial ion concentration. Furthermore, the changes of pore structure over immersion time were separately figured and tabulated by virtue of mercury intrusion porosimetry (MIP). The above analysis shows that when cement paste suffers sulfate attack, triethanolamine intensifies the formation of calcite and exacerbates the decalcification of C-S-H, promoting a large quantity of insoluble precipitation including mirabilite of abundant crystalline water which accounts essentially for severe damage. Determined after comprehensive evaluation, the addition of TEA is conducive to the emergence of physical sulfate attack and an increment of the total porosity and permeability, contributing to an extension of microcracks and a more fragile structure, ultimately makes cement paste appear as a reduction in strength and stiffness. • Triethanolamine correlates adversely with the resistance to sulfate attack of cement paste • The complex of sulfate and aluminum ions occupied by the TEA intensifies decalcification of C-S-H • Triethanolamine loosens internal structure and permeability paths inside cement paste within sulfate attack [ABSTRACT FROM AUTHOR]

This paper presents the potential use of eggshell powder (ESP) as green accelerator in ground palm oil fuel ash (GPOFA) concrete. Three categories of ESPs namely uncarbonised ESP (UC-ESP), carbonised ESP (C-ESP) and decarbonised ESP (DC-ESP) corresponding to no calcination and calcination at temperatures of 750 and 1000 °C, respectively, were prepared and studied. In addition, ESPs was used as cement replacement (0, 5, 10, 15, and 20 wt%) in GPOFA concrete and their performance were examined in term of reactivity, workability, heat hydration, compressive strength and microstructure performance. It was found that the presence of UC-ESP, C-ESP and DC-ESP can provide a low, medium and superior accelerator behaviour in the early age of GPOFA concrete. Overall, the GPOFA concrete combined with DC-ESP revealed an excellence SiO 2 -CaO reactivity, giving a twice compressive strength at early age and provides inductive hydration behaviour with low hydration temperature and significant improvement in dense gels formulation. Hence, this study provides a positive impact for rapid construction technology. As a conclusion, modified ESP is a highly potential as partial cement replacement and accelerator for concrete. • Eggshell powder (ESP) calcined at different temperatures are studies. • ESP is used as accelerator for palm oil fuel ash (POFA) concrete. • SiO 2 -CaO derived from GPOFA and calcined ESP provided an excellence accelerator in concrete. [ABSTRACT FROM AUTHOR]

Improving urban green economic efficiency is a necessary response to environmental constraints and the transformation of economic development mode, and how to improve green economic efficiency through smart city pilot has become an important consideration. In this study, we construct the Date Envelopment Analysis-Slack Based Model to measure the green economic efficiency, and further evaluate the impacts of smart city on green economic efficiency using the propensity score matching-Differences-in-Differences (PSM-DID) model. The mainly results are as follows. The urban green economic efficiency can be improved by smart city pilot, and be improved by smart city through technology effect, structure effect and energy effect. Smart city with the dual attributes, information technology and environmental regulation, acts as a role of accelerator that both promote economic efficiency and environment, and thus accelerates the improvement of green economic efficiency. Smart city plays a significant role in cities with high level of talent aggregation and financial development, low level of population density, network infrastructure and urban expansion. The results of this paper provide the policy implications for the construction of smart city and sustainable development. • Smart city pilot can improve the urban green economic efficiency. • Smart city plays the role through the effects of technology, structure and energy. • Smart city is an accelerator both promotes economic efficiency and environment. • The effect of smart city varies across urban structure and characteristics. [ABSTRACT FROM AUTHOR]

This article examines the impact of various accelerators on the vulcanization process and mechanical properties of natural rubber. The study reveals that different accelerators have different effects on the cure time and strength of the rubber. For example, thiurams and dithiocarbamates result in faster cure time, while sulphenamides, particularly TBBS, provide better tensile strength. The article also emphasizes the importance of using the correct ratios of rubber chemicals and extenders to achieve desired product characteristics. Overall, the findings suggest that the choice of accelerator plays a significant role in determining the properties of vulcanized rubber. [Extracted from the article]

Low-level radio frequency (LLRF) systems have been designed to regulate the accelerator field in the cavity; these systems have been used in the free electron laser (FLASH) and European X-ray free-electron laser (E-XFEL). However, the reliable operation of these cavities is often hindered by two primary sources of noise and disturbances: Lorentz force detuning (LFD) and mechanical vibrations, commonly known as microphonics. This article presents an innovative solution in the form of a narrowband active noise controller (NANC) designed to compensate for the narrowband mechanical noise generated by certain supporting machines, such as vacuum pumps and helium pressure vibrations. To identify the adaptive filter coefficients in the NANC method, a least mean squares (LMS) algorithm is put forward. Furthermore, a variable step size (VSS) method is proposed to estimate the adaptive filter coefficients based on changes in microphonics, ultimately compensating for their effects on the cryomodule. An accelerometer with an SPI interface and some transmission boards are manufactured and mounted at the cryomodule test bench (CMTB) to measure the microphonics and transfer them via Ethernet cable from the cryomodule side to the LLRF crate side. Several locations had been selected to find the optimal location for installing the accelerometer. The proposed NANC method is characterized by low computational complexity, stability, and high tracking ability. By addressing the challenges associated with noise and disturbances in cavity operation, this research contributes to the enhanced performance and reliability of LLRF systems in particle accelerators. [ABSTRACT FROM AUTHOR]

Incubators and accelerators have proliferated, but their impact on new ventures' performance remains unclear. This article explores whether all ventures benefit equally from participating in accelerator programs. We propose that the entrepreneurs' human capital resources influence the benefits extracted from accelerator program participation. Using application data from the accelerator programs across developed and developing countries, we find participation in accelerator programs positively impacts the ventures' innovation performance but has a mixed impact on social performance. Founders with high education benefit from participating in accelerator programs for innovation and social performance. However, entrepreneurial experience and vast industry experience do not significantly influence ventures' social and innovation-related performance from accelerator participation. The result is consistent for both solo and team founders. Plain English Summary: Entrepreneurs with high education and experience get more value-added benefits from accelerators. The accelerator programs can help create a 'community of organizations, institutions, and individuals that impact the enterprise and the enterprise's customers and suppliers; entrepreneurs' resources help create an environment that increases the potential of the new ventures. Additionally, a team of entrepreneurs with education, industry, and entrepreneurial experience can help with the venture's performance. Therefore, accelerator programs should focus on firms with highly educated entrepreneurs since entrepreneurs with high education and experience get more value-added benefits from accelerators. For the corporate managers engaged in corporate/intrapreneurship, employees with industry and entrepreneurial experience can be a great resource, and human resource managers can help with recruiting these individuals. Policymakers should pay close attention to younger firms since they are vulnerable. Further, policymakers should pay close attention to ventures with entrepreneurs with educational experience since entrepreneurs' industry and entrepreneurial experience can complement their lacking. [ABSTRACT FROM AUTHOR]

The analysis presented in this concise review is directed towards evaluating the contemporary trends and practical implementations of the ELU-4 electronic linear accelerator across a broad spectrum of scientific and technological domains. The ELU-4 linear electron accelerator represents a key technological achievement in the field of accelerator technology in general and linear electronic accelerators in particular. Various aspects of the use of ELU-4 are considered, starting from its application in medicine, ecology, verification of computer models for calculating the effects of radiation, space applications, research on the effect of electronic irradiation on various materials and devices, including semiconductor devices, ending with its fundamental research of materials. Current data presented in scientific articles and reports from the last ten years are researched and analysed. This succinct review not only underscores the conventional applications of this accelerator but also underscores its potential in nascent fields of science and technology. The incorporation of ELU-4 into diverse research and engineering endeavors presents notable prospects for innovation and the advancement of scientific knowledge frontiers. [ABSTRACT FROM AUTHOR]

This paper conducts a comprehensive study on intermittent computing within IoT environments, emphasizing the interplay between different dataflows—row, weight, and output—and a variety of non-volatile memory technologies. We then delve into the architectural optimization of these systems using a spatial architecture, namely IDEA, with their processing elements efficiently arranged in a rhythmic pattern, providing enhanced performance in the presence of power failures. This exploration aims to highlight the diverse advantages and potential applications of each combination, offering a comparative perspective. In our findings, using IDEA for the row stationary dataflow with AlexNet on the CIFAR10 dataset, we observe a power efficiency gain of 2.7% and an average reduction of 21% in the required cycles. This study elucidates the potential of different architectural choices in enhancing energy efficiency and performance in IoT systems.

Radio-frequency quadrupoles (RFQs) are multi-purpose linear particle accelerators that simultaneously bunch and accelerate charged particle beams. They are ubiquitous in accelerator physics, especially as injectors to higher-energy machines, owing to their impressive efficiency. The design and optimization of these devices can be lengthy due to the need to repeatedly perform high-fidelity simulations. Several recent papers have demonstrated that machine learning can be used to build surrogate models (fast-executing replacements of computationally costly beam simulations) for order-of-magnitude computing time speedups. However, while these pilot studies are encouraging, there is room to improve their predictive accuracy. Particularly, beam summary statistics such as emittances (an important figure of merit in particle accelerator physics) have historically been challenging to predict. For the first time, we present a surrogate model trained on 200 000 samples that yields $\lt$ 6% mean average percent error for the predictions of all relevant beam output parameters from defining RFQ design parameters, solving the problem of poor emittance predictions by identifying and including hidden variables which were not accounted for previously. These surrogate models were made possible by using the Julia language and GPU computing; we briefly discuss both. We demonstrate the utility of surrogate modeling by performing a multi-objective optimization using our best model as a callback in the objective function to select an optimal RFQ design. We consider trade-offs in RFQ performance for various choices of Pareto-optimal design variables—common issues for any multi-objective optimization scheme. Lastly, we make recommendations for input data preparation, selection, and neural network architectures that pave the way for future development of production-capable surrogate models for RFQs and other particle accelerators.