1. A Compact 32-bit Architecture for an AES System
- Author
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Surapong Pongyupinpanich, Somsanouk Pathumvanh, and Somsak Choomchuay
- Subjects
Information Systems and Management ,Computer Networks and Communications ,business.industry ,Computer science ,Advanced Encryption Standard ,AES implementations ,32-bit ,Encryption ,AES instruction set ,Embedded system ,Hardware_ARITHMETICANDLOGICSTRUCTURES ,Electrical and Electronic Engineering ,business ,Field-programmable gate array ,Computer hardware ,Information Systems - Abstract
This paper describes a compact 32-bit architecture developed for the Rijndael ciphering/deciphering system. The implementation is complied with NIST Advanced Encryption Standard (AES). The design processes any 128-bit block data with 128-bit key. For the compact hardware, the field inversion circuit and the key scheduling circuits are shared by both the encryption and decryption process. The on-the-fly KeyScheduling implementation offers fast processing speed but with core size trade-off. According to the evaluation made on the targeted FPGA, the design can offer the throughput of 768 mbps at 264 MHz clock speed.
- Published
- 1970