1,072 results
Search Results
2. Assessing Efficiency Benefits of Edge Intelligence
- Author
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Lenherr, Nicola, Pawlitzek, René, Michel, Bruno, Goos, Gerhard, Founding Editor, Hartmanis, Juris, Founding Editor, Bertino, Elisa, Editorial Board Member, Gao, Wen, Editorial Board Member, Steffen, Bernhard, Editorial Board Member, Yung, Moti, Editorial Board Member, González-Vidal, Aurora, editor, Mohamed Abdelgawad, Ahmed, editor, Sabir, Essaid, editor, Ziegler, Sébastien, editor, and Ladid, Latif, editor
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- 2022
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3. DataRaceOnAccelerator – A Micro-benchmark Suite for Evaluating Correctness Tools Targeting Accelerators
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Schmitz, Adrian, Protze, Joachim, Yu, Lechen, Schwitanski, Simon, Müller, Matthias S., Goos, Gerhard, Founding Editor, Hartmanis, Juris, Founding Editor, Bertino, Elisa, Editorial Board Member, Gao, Wen, Editorial Board Member, Steffen, Bernhard, Editorial Board Member, Woeginger, Gerhard, Editorial Board Member, Yung, Moti, Editorial Board Member, Schwardmann, Ulrich, editor, Boehme, Christian, editor, B. Heras, Dora, editor, Cardellini, Valeria, editor, Jeannot, Emmanuel, editor, Salis, Antonio, editor, Schifanella, Claudio, editor, Manumachu, Ravi Reddy, editor, Schwamborn, Dieter, editor, Ricci, Laura, editor, Sangyoon, Oh, editor, Gruber, Thomas, editor, Antonelli, Laura, editor, and Scott, Stephen L., editor
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- 2020
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4. Deep Reinforcement Learning for Auto-optimization of I/O Accelerator Parameters
- Author
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Pham, Trong-Ton, Djan, Dennis Mintah, Goos, Gerhard, Founding Editor, Hartmanis, Juris, Founding Editor, Bertino, Elisa, Editorial Board Member, Gao, Wen, Editorial Board Member, Steffen, Bernhard, Editorial Board Member, Woeginger, Gerhard, Editorial Board Member, Yung, Moti, Editorial Board Member, Gao, Wanling, editor, Zhan, Jianfeng, editor, Fox, Geoffrey, editor, Lu, Xiaoyi, editor, and Stanzione, Dan, editor
- Published
- 2020
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5. Examining Performance Portability with Kokkos for an Ewald Sum Coulomb Solver
- Author
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Halver, Rene, Meinke, Jan H., Sutmann, Godehard, Goos, Gerhard, Founding Editor, Hartmanis, Juris, Founding Editor, Bertino, Elisa, Editorial Board Member, Gao, Wen, Editorial Board Member, Steffen, Bernhard, Editorial Board Member, Woeginger, Gerhard, Editorial Board Member, Yung, Moti, Editorial Board Member, Wyrzykowski, Roman, editor, Deelman, Ewa, editor, Dongarra, Jack, editor, and Karczewski, Konrad, editor
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- 2020
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6. Advances toward solutions for marine plastic pollution in southern California: Key recommendations of the white papers produced during the 2021 Scripps-Rady Ocean Plastic Pollution Challenge
- Author
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Center for Marine Biodiversity and Conservation, Scripps Institution of Oceanography at University of California San Diego and Center for Social Innovation and Impact, Rady School of Management at University of California San Diego
- Subjects
challenge ,accelerator ,plastic pollution - Abstract
The Scripps-Rady Ocean Plastic Pollution Challenge was a unique 6-month accelerator program focused on identifying effective, evidence-based approaches to curb the flow of plastic into the ocean, with a specific focus on marine conservation and marine cultural preservation areas along California’s coast. The inaugural program ran January - June, 2021, and participants engaged in a series of virtual short courses, team-based research, and a final two-day challenge to pitch solutions to an expert panel.A key component of the Scripps-Rady Challenge was team-based research from March - May, 2021. Each team was assigned one of the following research topics: changing human behavior, evaluating policy solutions, and data mapping. Working closely with their dedicated mentors, teams researched various aspects of their respective topics such as a review of past efforts and programs, an identification of key stakeholders, and an analysis of major knowledge gaps.This document includes: 1) a synthesis of all the findings of the white papers, including a table that divides them by stakeholder groups, and 2) a summary of each paper’s major findings and recommendations.
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- 2021
7. ACCDSE: A Design Space Exploration Framework for Convolutional Neural Network Accelerator
- Author
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Li, Zhisheng, Wang, Lei, Dou, Qiang, Tang, Yuxing, Guo, Shasha, Zhou, Haifang, Lu, Wenyuan, Barbosa, Simone Diniz Junqueira, Series editor, Chen, Phoebe, Series editor, Filipe, Joaquim, Series editor, Kotenko, Igor, Series editor, Sivalingam, Krishna M., Series editor, Washio, Takashi, Series editor, Yuan, Junsong, Series editor, Zhou, Lizhu, Series editor, Xu, Weixia, editor, Xiao, Liquan, editor, Li, Jinwen, editor, Zhang, Chengyi, editor, and Zhu, Zhenzhen, editor
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- 2018
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8. Large Scale Graph Processing in a Distributed Environment
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Upadhyay, Nitesh, Patel, Parita, Cheramangalath, Unnikrishnan, Srikant, Y. N., Hutchison, David, Series Editor, Kanade, Takeo, Series Editor, Kittler, Josef, Series Editor, Kleinberg, Jon M., Series Editor, Mattern, Friedemann, Series Editor, Mitchell, John C., Series Editor, Naor, Moni, Series Editor, Pandu Rangan, C., Series Editor, Steffen, Bernhard, Series Editor, Terzopoulos, Demetri, Series Editor, Tygar, Doug, Series Editor, Weikum, Gerhard, Series Editor, Heras, Dora B., editor, Bougé, Luc, editor, Mencagli, Gabriele, editor, Jeannot, Emmanuel, editor, Sakellariou, Rizos, editor, Badia, Rosa M., editor, Barbosa, Jorge G., editor, Ricci, Laura, editor, Scott, Stephen L., editor, Lankes, Stefan, editor, and Weidendorfer, Josef, editor
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- 2018
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9. A Heterogeneous Runtime Environment for Scientific Desktop Computing
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Oliveira, Nuno, Medeiros, Pedro D., Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Dutra, Inês, editor, Camacho, Rui, editor, Barbosa, Jorge, editor, and Marques, Osni, editor
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- 2017
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10. Resource Aggregation for Task-Based Cholesky Factorization on Top of Heterogeneous Machines
- Author
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Cojean, T., Guermouche, A., Hugo, A., Namyst, R., Wacrenier, P. A., Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Desprez, Frédéric, editor, Dutot, Pierre-François, editor, Kaklamanis, Christos, editor, Marchal, Loris, editor, Molitorisz, Korbinian, editor, Ricci, Laura, editor, Scarano, Vittorio, editor, Vega-Rodríguez, Miguel A., editor, Varbanescu, Ana Lucia, editor, Hunold, Sascha, editor, Scott, Stephen L., editor, Lankes, Stefan, editor, and Weidendorfer, Josef, editor
- Published
- 2017
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11. Instruction Set Architectures for Quantum Processing Units
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Britt, Keith A., Humble, Travis S., Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Kunkel, Julian M., editor, Yokota, Rio, editor, Taufer, Michela, editor, and Shalf, John, editor
- Published
- 2017
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12. Directive-Based Compilers for GPUs
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Ghike, Swapnil, Gran, Rubén, Garzarán, María J., Padua, David, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Brodman, James, editor, and Tu, Peng, editor
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- 2015
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13. Snowmass 2021 White Paper: Electron Ion Collider for High Energy Physics
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Abdul Khalek, R., D Alesio, U., Arratia, Miguel, Bacchetta, A., Battaglieri, M., Begel, M., Boglione, M., Boughezal, R., Boussarie, Renaud, Bozzi, G., Chekanov, S. V., Francesco Giovanni Celiberto, Chirilli, G., Cridge, T., Cruz-Torres, R., Corliss, R., Cotton, C., Davoudiasl, H., Deshpande, A., Dong, Xin, Emmert, A., Fazio, S., Forte, S., Furletova, Yulia, Gal, Ciprian, Gwenlan, Claire, Guzey, V., Harland-Lang, L. A., Helenius, I., Hentschinski, M., Hobbs, Timothy J., Höche, S., Hou, T. -J, Ji, Y., Jing, X., Kelsey, M., Klasen, M., Kang, Zhong-Bo, Kovchegov, Y. V., Kumar, K. S., Lappi, Tuomas, Lee, K., Lee, Yen-Jie, Li, H. -T, Li, X., Lin, H. -W, Liu, H., Liu, Z. L., Liuti, S., Lorcé, C., Lunghi, E., Marcarelli, R., Magill, S., Makris, Y., Mantry, S., Melnitchouk, W., Mezrag, C., Moch, S., Moutarde, H., Mukherjee, Swagato, Murgia, F., Nachman, B., Nadolsky, P. M., Nam, J. D., Neill, D., Neill, E. T., Nocera, E., Nycz, M., Olness, F., Petriello, F., Pitonyak, D., Plätzer, S., Prestel, Stefan, Prokudin, Alexei, Qiu, J., Radici, M., Radhakrishnan, S., Sadofyev, A., Rojo, J., Ringer, F., Salazar, Farid, Sato, N., Schenke, Björn, Schlichting, Sören, Schweitzer, P., Sekula, S. J., Shao, D. Y., Sherrill, N., Sichtermann, E., Signori, A., Şimşek, K., Simonelli, A., Sznajder, P., Tezgin, K., Thorne, R. S., Tricoli, A., Venugopalan, R., Vladimirov, A., Vicini, Alessandro, Vitev, Ivan, Wiegand, D., Wong, C. -P, Xie, K., Zaccheddu, M., Zhao, Y., Zhang, J., Zheng, X., Zurita, P., Centre de Physique Théorique [Palaiseau] (CPHT), École polytechnique (X)-Centre National de la Recherche Scientifique (CNRS), Institut de Recherches sur les lois Fondamentales de l'Univers (IRFU), and Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université Paris-Saclay
- Subjects
electron ,Nuclear Theory ,accelerator ,[PHYS.NUCL]Physics [physics]/Nuclear Theory [nucl-th] ,p: polarized beam ,FOS: Physical sciences ,electron nucleon: colliding beams ,electron nucleus ,[PHYS.NEXP]Physics [physics]/Nuclear Experiment [nucl-ex] ,High Energy Physics - Experiment ,Nuclear Theory (nucl-th) ,High Energy Physics - Experiment (hep-ex) ,High Energy Physics - Phenomenology ,High Energy Physics - Phenomenology (hep-ph) ,[PHYS.HPHE]Physics [physics]/High Energy Physics - Phenomenology [hep-ph] ,[PHYS.HEXP]Physics [physics]/High Energy Physics - Experiment [hep-ex] ,Physics::Accelerator Physics ,ion ,Nuclear Experiment (nucl-ex) ,Nuclear Experiment - Abstract
Electron Ion Collider (EIC) is a particle accelerator facility planned for construction at Brookhaven National Laboratory on Long Island, New York by the United States Department of Energy. EIC will provide capabilities of colliding beams of polarized electrons with polarized beams of proton and light ions. EIC will be one of the largest and most sophisticated new accelerator facilities worldwide, and the only new large-scale accelerator facility planned for construction in the United States in the next few decades. The versatility, resolving power and intensity of EIC will present many new opportunities to address some of the crucial and fundamental open scientific questions in particle physics. This document provides an overview of the science case of EIC from the perspective of the high energy physics community., Submitted to the Proceedings of the US Community Study on the Future of Particle Physics (Snowmass 2021)
- Published
- 2022
14. Design and Implementation of Novel Flexible Crypto Coprocessor and Its Application in Security Protocol
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Ni, Shice, Dou, Yong, Chen, Kai, Deng, Lin, Xu, Weixia, editor, Xiao, Liquan, editor, Zhang, Chengyi, editor, Li, Jinwen, editor, and Yu, Liyan, editor
- Published
- 2013
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15. The Design of Video Accelerator Bus Wrapper
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Xu, Yan, Nan, Longmei, Guo, Pengfei, Xu, Jinfu, Xu, Weixia, editor, Xiao, Liquan, editor, Zhang, Chengyi, editor, Li, Jinwen, editor, and Yu, Liyan, editor
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- 2013
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16. Blink: Not Your Father’s Database!
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Barber, Ronald, Bendel, Peter, Czech, Marco, Draese, Oliver, Ho, Frederick, Hrle, Namik, Idreos, Stratos, Kim, Min-Soo, Koeth, Oliver, Lee, Jae-Gil, Li, Tianchao Tim, Lohman, Guy, Morfonios, Konstantinos, Mueller, Rene, Murthy, Keshava, Pandis, Ippokratis, Qiao, Lin, Raman, Vijayshankar, Szabo, Sandor, Sidle, Richard, Stolze, Knut, van der Aalst, Wil, editor, Mylopoulos, John, editor, Rosemann, Michael, editor, Shaw, Michael J., editor, Szyperski, Clemens, editor, Castellanos, Malu, editor, Dayal, Umeshwar, editor, and Lehner, Wolfgang, editor
- Published
- 2012
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17. Suffering, recovery and participant experience in a video game development accelerator
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Gidley, Devon, Palmer, Mark, and Gharib, Amani
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- 2023
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18. Physiochemical characterization of agricultural waste biochars for partial cement replacement
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Ofori-Boadu, Andrea Nana, Bryant, DeAndria, Bock-Hyeng, Christian, Assefa, Zerihun, Aryeetey, Frederick, Munkaila, Samira, and Fini, Elham
- Published
- 2022
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19. What do female and male entrepreneurs value in business accelerators?
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Kwapisz, Agnieszka
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- 2022
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20. Pathology of acceleration programs in corporate accelerators of Iran
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Heshmati, Saeed and Shafiee, Maysam
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- 2021
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21. The value of business accelerators and incubators – an entrepreneur’s perspective
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Lange, Ginger S. and Johnston, Wesley J.
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- 2020
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22. Accelerating Attention Mechanism on FPGAs based on Efficient Reconfigurable Systolic Array.
- Author
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WENHUA YE, XU ZHOU, JOEY ZHOU, CEN CHEN, and KENLI LI
- Subjects
TRANSFORMER models ,GATE array circuits ,COMPUTER vision ,MACHINE translating ,NATURAL languages - Abstract
Transformer model architectures have recently received great interest in natural language, machine translation, and computer vision, where attention mechanisms are their building blocks. However, the attention mechanism is expensive because of its intensive matrix computations and complicated data flow. The existing hardware architecture has some disadvantages for the computing structure of attention, such as in- flexibility and low efficiency. Most of the existing papers accelerate attention by reducing the amount of computation through various pruning algorithms, which will affect the results to a certain extent with different sparsity. This paper proposes the hardware accelerator for the multi-head attention (MHA) on field-programmable gate arrays (FPGAs) with reconfigurable architecture, efficient systolic array, and hardware-friendly radix-2 softmax. We propose a novel method called Four inputs Processing Element (FPE) to double the computation rate of the data-aware systolic array (SA) and make it efficient and load balance. Especially, the computation framework is well designed to ensure the utilization of SA efficiently. Our design is evaluated on a Xilinx Alveo U250 card, and the proposed architecture achieves 51.3x, 17.3x improvement in latency, and 54.4x, 17.9x energy savings compared to CPU and GPU. [ABSTRACT FROM AUTHOR]
- Published
- 2023
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23. Thermal Characterization of Kraft Lignin Phenol-Formaldehyde Resin for Paper Impregnation.
- Author
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Mahendran, Arunjunaj Raj, Wuzella, Günter, and Kandelbauer, Andreas
- Subjects
- *
FORMALDEHYDE , *PHENOL , *UREA-formaldehyde resins , *THERMAL analysis , *DRYING - Abstract
Both kraft lignin phenol-formaldehyde (KLPF) and phenol-formaldehyde (PF) resins were synthesized and the curing kinetics of the resins was determined using thermal analysis data. The kinetic parameters were predicted using two popular model-free kinetic (MFK) methods: the advanced form of the Vyazovkin method and the Kissinger–Akahira–Sunose method. From the experimental and predicted values, the rate of kraft lignin phenol-formaldehyde curing was less compared to the phenol-formaldehyde resin. To increase the cure rate different cure additives were tried. Among these, only potassium carbonate (KC) showed a positive effect: An increase in additive concentration to 4% reduced the curing time to almost 50% as compared to pure KLPF resin at 160°C. Comparison of the predicted values from MFK calculations with isothermal experimental data showed that both MFK approaches were suitable to predict the curing characteristics. [ABSTRACT FROM AUTHOR]
- Published
- 2010
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24. Corporate accelerators: fostering innovation while bringing together startups and large firms
- Author
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Kupp, Martin, Marval, Moyra, and Borchers, Peter
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- 2017
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25. Clean Cities ClimAccelerator, a systemic change through co-creation and collaboration.
- Author
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Horta-Bellido, Ana, Mazorra, Javier, Navarro-Carrillo, Elisa, Armuña, Cristina, and Feijóo, Claudio
- Subjects
CUSTOMER cocreation ,NEW business enterprises ,BUSINESS ecosystems ,STAKEHOLDER theory ,ENTREPRENEURSHIP - Abstract
Nowadays, there is an increased interest in startups’ creation and acceleration programs. A key part of these programs consists of exposing these startups to a dynamic ecosystem, where startups have difficulties to access on their own. Additionally, if it is considered a market composed by public entities, it is even more challenging. Especially for startups aiming to work in/with the public sector, cities in p articular, including not only corporates, academia and investors introduce a wide variety of public institutions. This paper displays the Clean Cities ClimAccelerator project as a case study on a European-wide startup acceleration program focused on the climate challenges faced by cities, where all actors collaborate for a systemic change. This paper aims to describe, analyze, and assess how the interaction between all actors involved is developed through the concepts indicated. The results presented here may facilitate improvements in the dynamics and as guidelines to implement within a multi-level and multi-stakeholder ecosystem through cocreation and collaboration. [ABSTRACT FROM AUTHOR]
- Published
- 2023
26. Survey of convolutional neural network accelerators on field-programmable gate array platforms: architectures and optimization techniques.
- Author
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Hong, Hyeonseok, Choi, Dahun, Kim, Namjoon, Lee, Haein, Kang, Beomjin, Kang, Huibeom, and Kim, Hyun
- Abstract
With the recent advancements in high-performance computing, convolutional neural networks (CNNs) have achieved remarkable success in various vision tasks. However, along with improvements in model accuracy, the size and computational complexity of the models have significantly increased with the increasing number of parameters. Although graphics processing unit (GPU) platforms equipped with high-performance memory and specialized in parallel processing are commonly used for CNN processing, the significant power consumption presents challenges in their utilization on edge devices. To address these issues, research is underway to design CNN models using field-programmable gate arrays (FPGAs) as accelerators. FPGAs provide a high level of flexibility, allowing efficient optimization of convolution operations, which account for a significant portion of the CNN computations. Additionally, FPGAs are known for their low power consumption compared to GPUs, making them a promising energy-efficient platform. In this paper, we review and summarize various approaches and techniques related to the design of FPGA-based CNN accelerators. Specifically, to comprehensively study CNN accelerators, we investigate the advantages and disadvantages of various methods for optimizing CNN accelerators and previously designed efficient accelerator architectures. We expect this paper to serve as an important guideline for future hardware research in artificial intelligence. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
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27. FPGA Optimized Accelerator of DCNN with Fast Data Readout and Multiplier Sharing Strategy.
- Author
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TuoMa, Zhiwei Li, Qingjiang Li, Haijun Liu, Zhongjin Zhao, and YinanWang
- Subjects
DEEP learning ,CONVOLUTIONAL neural networks ,FIELD programmable gate arrays ,IMAGE recognition (Computer vision) ,DIGITAL signal processing ,MICROGRIDS - Abstract
With the continuous development of deep learning, Deep Convolutional Neural Network (DCNN) has attracted wide attention in the industry due to its high accuracy in image classification. Compared with other DCNN hardware deployment platforms, Field Programmable Gate Array (FPGA) has the advantages of being programmable, low power consumption, parallelism, and low cost. However, the enormous amount of calculation of DCNN and the limited logic capacity of FPGA restrict the energy efficiency of theDCNNaccelerator. The traditional sequential sliding window method can improve the throughput of the DCNN accelerator by data multiplexing, but this method’s datamultiplexing rate is low because it repeatedly reads the data between rows. This paper proposes a fast data readout strategy via the circular sliding window data reading method, it can improve the multiplexing rate of data between rows by optimizing the memory access order of input data. In addition, themultiplication bit width of the DCNN accelerator ismuch smaller than that of the Digital Signal Processing (DSP) on the FPGA, whichmeans that there will be a waste of resources if amultiplication uses a single DSP. Amultiplier sharing strategy is proposed, the multiplier of the accelerator is customized so that a singleDSP block can complete multiple groups of 4, 6, and 8-bit signed multiplication in parallel. Finally, based on two strategies of appeal, an FPGA optimized accelerator is proposed.The accelerator is customized byVerilog language and deployed onXilinxVCU118.When the accelerator recognizes the CIRFAR-10 dataset, its energy efficiency is 39.98 GOPS/W, which provides 1.73 × speedup energy efficiency over previous DCNN FPGA accelerators. When the accelerator recognizes the IMAGENET dataset, its energy efficiency is 41.12 GOPS/W, which shows 1.28×−3.14 × energy efficiency compared with others. [ABSTRACT FROM AUTHOR]
- Published
- 2023
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28. Leveraging Bit-Serial Architectures for Hardware-Oriented Deep Learning Accelerators with Column-Buffering Dataflow.
- Author
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Cheng, Xiaoshu, Wang, Yiwen, Ding, Weiran, Lou, Hongfei, and Li, Ping
- Subjects
CONVOLUTIONAL neural networks ,DEEP learning ,ARRAY processing - Abstract
Bit-serial neural network accelerators address the growing need for compact and energy-efficient deep learning tools. Traditional neural network accelerators, while effective, often grapple with issues of size, power consumption, and versatility in handling a variety of computational tasks. To counter these challenges, this paper introduces an approach that hinges on the integration of bit-serial processing with advanced dataflow techniques and architectural optimizations. Central to this approach is a column-buffering (CB) dataflow, which significantly reduces access and movement requirements for the input feature map (IFM), thereby enhancing efficiency. Moreover, a simplified quantization process effectively eliminates biases, streamlining the overall computation process. Furthermore, this paper presents a meticulously designed LeNet-5 accelerator leveraging a convolutional layer processing element array (CL PEA) architecture incorporating an improved bit-serial multiply–accumulate unit (MAC). Empirically, our work demonstrates superior performance in terms of frequency, chip area, and power consumption compared to current state-of-the-art ASIC designs. Specifically, our design utilizes fewer hardware resources to implement a complete accelerator, achieving a high performance of 7.87 GOPS on a Xilinx Kintex-7 FPGA with a brief processing time of 284.13 μs. The results affirm that our design is exceptionally suited for applications requiring compact, low-power, and real-time solutions. [ABSTRACT FROM AUTHOR]
- Published
- 2024
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- View/download PDF
29. Who am I as an Entrepreneur? Exploring Formation of Entrepreneurial Identity.
- Author
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Elvekrok, Ingunn and Tobiassen, Anita Ellen
- Subjects
IDENTITY (Psychology) ,BUSINESSPEOPLE ,MARKETING models ,ENTREPRENEURSHIP education ,SELF-perception - Abstract
This paper explores how participation in accelerator programs, which are aimed at scaling ventures, influences the self-perceptions of the participants. An entrepreneur's identity is considered important in both theory and practice, but few studies have investigated how the identities of entrepreneurs/founders are affected by their participation in a program that is aimed mainly at the venture and not the person behind the venture. By providing access to resources, mentorship, and support, which help entrepreneurs test hypotheses and problems, as well as identify markets and business models for their ventures, an accelerator helps entrepreneurs increase their confidence, skills, and knowledge. These factors are important because they enable entrepreneurs to better understand themselves and their perceived opportunity space and choice of actions. Data were collected through in-depth interviews with 14 entrepreneurs that had participated in two different accelerators with slightly different programs. The findings indicate that the accelerators influenced both the personal identify and role identity of the participating entrepreneurs. However, the impact of the accelerator varied according to the self-perceptions of the entrepreneurs' pre-participation and how far they had come in developing their business concepts. Their admittance to an accelerator in itself boosted their identities. We found no difference between the private accelerator program (PA) and the governmental program (GA). The paper contributes to the literature on entrepreneurial identity formation and the effects of accelerators. [ABSTRACT FROM AUTHOR]
- Published
- 2023
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30. Standardize or customize business acceleration programs? The multistage model of Archimedes accelerator.
- Author
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Livieratos, Antonios D. and Siemos, Vasilis
- Subjects
BUSINESS models ,INFORMATION & communication technologies ,TECHNOLOGICAL innovations ,STANDARDIZATION ,BUSINESS ecosystems - Abstract
Accelerators have rapidly emerged as prominent players in the entrepreneurial ecosystem. In designing acceleration programs, a key strategic decision is the extent of customization. Recognizing a trade-off between customization and standardization, the paper presents a multistage model developed to serve the needs of the newly established business accelerator of the National and Kapodistrian University of Athens. Aiming to harvest benefits of standardization while keeping several advantages found in tailor-made acceleration programs, a 3-stage model is proposed. Each stage matches a different level of maturity and startup selection positions applicants into one of the three stages. For those positioned in the first two stages the aim is to progressively (and selectively) assist them through to the next stages. As authors act as change agents aiming to solve practical problems, an action research approach is adopted. The paper presents initial results of a research aiming to validate the proposed multistage acceleration model. [ABSTRACT FROM AUTHOR]
- Published
- 2020
31. CNN Accelerator Using Proposed Diagonal Cyclic Array for Minimizing Memory Accesses.
- Author
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Hyun-Wook Son, Al-Hamid, Ali A., Yong-Seok Na, Dong-Yeong Lee, and Hyung-Won Kim
- Subjects
FIELD programmable gate arrays ,CONVOLUTIONAL neural networks ,DIGITAL signal processing - Abstract
This paper presents the architecture of a Convolution Neural Network (CNN) accelerator based on a new processing element (PE) array called a diagonal cyclic array (DCA). As demonstrated, it can significantly reduce the burden of repeated memory accesses for feature data and weight parameters of the CNN models, which maximizes the data reuse rate and improve the computation speed. Furthermore, an integrated computation architecture has been implemented for the activation function, max-pooling, and activation function after convolution calculation, reducing the hardware resource. To evaluate the effectiveness of the proposed architecture, a CNN accelerator has been implemented for You Only Look Once version 2 (YOLOv2)-Tiny consisting of 9 layers. Furthermore, the methodology to optimize the local buffer size with little sacrifice of inference speed is presented in this work. We implemented the proposed CNN accelerator using a Xilinx Zynq ZCU102 Ultrascale+ Field Programmable Gate Array (FPGA) and ISE Design Suite. The FPGA implementation uses 34,336 Look Up Tables (LUTs), 576 Digital Signal Processing (DSP) blocks, and an on-chip memory of only 58 KB, and it could achieve accuracies of 57.92% and 56.42% mean Average Precession @0.5 thresholds for intersection over union (mAP@0.5) using quantized 16- bit and 8-bit full integer data manipulation with only 0.68% as a loss for 8- bit version and computation time of 137.9 and 69 ms for each input image respectively using a clock speed of 200 MHz. These speeds are expected to be doubled five times using a clock speed of 1 GHz if implemented in a silicon System on Chip (SoC) using a sub-micron process. [ABSTRACT FROM AUTHOR]
- Published
- 2023
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32. PYNQ Framework Based Object Recognition Implementation Using Convolution Neural Network (CNN).
- Author
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Jie Wang and Li Xu
- Subjects
CONVOLUTIONAL neural networks ,OBJECT recognition (Computer vision) ,ARM microprocessors - Abstract
In this paper, we presented a PYNQ framework Based object recognition implementation using Convolution Neural Network (CNN) in Xilinx FPGA. A hardware-software codesign framework is used to implement the CNN for object recognition. Training CNN model on PC, and implementation object recognition under embedded system on PYNQZ1 FPGA. Compare to a single ARM processor core on FPGA, we achieve 43.2 times speedup ratio for object recognition implementation. The performance demonstrates that this model can be highly improved by exploring the hardware resources of the FPGA. [ABSTRACT FROM AUTHOR]
- Published
- 2022
- Full Text
- View/download PDF
33. A laser–plasma platform for photon–photon physics: the two photon Breit–Wheeler process
- Author
-
G Pérez-Callejo, F C Salgado, Matthew Zepf, C. D. Murphy, C. Colgan, Y. Katzir, C. I. D. Underwood, Andreas Nürnberg, S. Bohlen, D Hollatz, S. J. Rose, H Harsh, Aaron Alejo, Christopher D. Gregory, Andreas Seidel, Kristjan Poder, Gianluca Sarri, M. J. V. Streeter, Jens Osterhoff, R. Watt, F. Roeder, S. Astbury, C Roedel, Sven Steinke, G. M. Samarin, John J. L. Morton, J. Hinojosa, P. W. Hatfield, Michael Campbell, B. Kettle, Alexander Thomas, P. P. Rajeev, Christopher Spindloe, E. Gerstmayr, C. D. Baird, Dominik Dannheim, Simon Spannagel, Stuart Mangles, Centre d'Etudes Lasers Intenses et Applications (CELIA), Centre National de la Recherche Scientifique (CNRS)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université de Bordeaux (UB), Engineering & Physical Science Research Council (EPSRC), Commission of the European Communities, Science and Technology Facilities Council (STFC), and Université de Bordeaux (UB)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Centre National de la Recherche Scientifique (CNRS)
- Subjects
Photon ,General Physics and Astronomy ,Physics::Optics ,7. Clean energy ,01 natural sciences ,law.invention ,ENERGY ,COLLIDER ,Two-photon excitation microscopy ,Physics in General ,law ,pixel ,strong field ,Focus on Strong Field Quantum Electrodynamics with High Power Lasers and Particle Beams ,photon-photon ,010303 astronomy & astrophysics ,two-photon ,Physics ,02 Physical Sciences ,QED ,collimator ,photon ,Breit–Wheeler ,wake field ,LIGHT ,Physical Sciences ,beam ,Particle Physics - Experiment ,Breit–Wheeler process ,Paper ,accelerator ,Fluids & Plasmas ,Physics, Multidisciplinary ,Other Fields of Physics ,bremsstrahlung ,photon–photon ,Nuclear physics ,Breit-Wheeler ,0103 physical sciences ,photon photon ,ddc:530 ,010306 general physics ,plasma ,laser–plasma ,Breit–Wheele ,Science & Technology ,hybrid ,scattering ,silicon ,Plasma ,laser-plasma ,Laser ,calibration ,Accelerators and Storage Rings ,[PHYS.PHYS.PHYS-GEN-PH]Physics [physics]/Physics [physics]/General Physics [physics.gen-ph] ,laser ,Pair production ,pair production ,nonlinear ,Physics::Accelerator Physics ,LWFA - Abstract
We describe a laser-plasma platform for photon-photon collision experiments to measure fundamental quantum electrodynamic processes such as the linear Breit-Wheeler process with real photons. The platform has been developed using the Gemini laser facility at the Rutherford Appleton Laboratory. A laser wakefield accelerator and a bremsstrahlung convertor are used to generate a collimated beam of photons with energies of hundreds of MeV, that collide with keV x-ray photons generated by a laser heated plasma target. To detect the pairs generated by the photon-photon collisions, a magnetic transport system has been developed which directs the pairs onto scintillation-based and hybrid silicon pixel single particle detectors. We present commissioning results from an experimental campaign using this laser-plasma platform for photon-photon physics, demonstrating successful generation of both photon sources, characterisation of the magnetic transport system and calibration of the single particle detectors, and discuss the feasibility of this platform for the observation of the Breit-Wheeler process. The design of the platform will also serve as the basis for the investigation of strong-field quantum electrodynamic processes such as the nonlinear Breit-Wheeler and the Trident process, or eventually, photon-photon scattering. We describe a laser–plasma platform for photon–photon collision experiments to measure fundamental quantum electrodynamic processes. As an example we describe using this platform to attempt to observe the linear Breit–Wheeler process. The platform has been developed using the Gemini laser facility at the Rutherford Appleton Laboratory. A laser Wakefield accelerator and a bremsstrahlung convertor are used to generate a collimated beam of photons with energies of hundreds of MeV, that collide with keV x-ray photons generated by a laser heated plasma target. To detect the pairs generated by the photon–photon collisions, a magnetic transport system has been developed which directs the pairs onto scintillation-based and hybrid silicon pixel single particle detectors (SPDs). We present commissioning results from an experimental campaign using this laser–plasma platform for photon–photon physics, demonstrating successful generation of both photon sources, characterisation of the magnetic transport system and calibration of the SPDs, and discuss the feasibility of this platform for the observation of the Breit–Wheeler process. The design of the platform will also serve as the basis for the investigation of strong-field quantum electrodynamic processes such as the nonlinear Breit–Wheeler and the Trident process, or eventually, photon–photon scattering.
- Published
- 2021
34. SH-GAT: Software-hardware co-design for accelerating graph attention networks on FPGA.
- Author
-
Wang, Renping, Li, Shun, Tang, Enhao, Lan, Sen, Liu, Yajing, Yang, Jing, Huang, Shizhen, and Hu, Hailong
- Subjects
COMPUTER software ,ARTIFICIAL intelligence ,TECHNOLOGICAL innovations ,MACHINE learning ,ALGORITHMS - Abstract
Graph convolution networks (GCN) have demonstrated success in learning graph structures; however, they are limited in inductive tasks. Graph attention networks (GAT) were proposed to address the limitations of GCN and have shown high performance in graph-based tasks. Despite this success, GAT faces challenges in hardware acceleration, including: 1) The GAT algorithm has difficulty adapting to hardware; 2) challenges in efficiently implementing Sparse matrix multiplication (SPMM); and 3) complex addressing and pipeline stall issues due to irregular memory accesses. To this end, this paper proposed SH-GAT, an FPGA-based GAT accelerator that achieves more efficient GAT inference. The proposed approach employed several optimizations to enhance GAT performance. First, this work optimized the GAT algorithm using split weights and softmax approximation to make it more hardware-friendly. Second, a load-balanced SPMM kernel was designed to fully leverage potential parallelism and improve data throughput. Lastly, data preprocessing was performed by pre-fetching the source node and its neighbor nodes, effectively addressing pipeline stall and complexly addressing issues arising from irregular memory access. SH-GAT was evaluated on the Xilinx FPGA Alveo U280 accelerator card with three popular datasets. Compared to existing CPU, GPU, and state-of-the-art (SOTA) FPGA-based accelerators, SH-GAT can achieve speedup by up to 3283 × , 13 × , and 2.3 ×. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
- View/download PDF
35. Low-latency remote-offloading system for accelerator.
- Author
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Saito, Shogo, Fujimoto, Kei, and Shiraga, Akinori
- Abstract
Specific workloads are increasingly offloaded to accelerators such as a graphic processing unit (GPU) and field-programmable gate array (FPGA) for real-time processing and computing efficiency. Because accelerators are expensive and consume much power, it is desirable to increase the efficiency of accelerator utilization by sharing accelerators among multiple servers over a network. However, task offloading over a network has the problem of latency due to network processing overhead in remote offloading. This paper proposes a low-latency system for accelerator offloading over a network. To reduce the overhead of remote offloading, we propose a system composed of (1) fast recombination processing of chunked data with a simple protocol to reduce the number of memory copies, (2) polling-based packet receiving check to reduce overhead due to interrupts in interaction with a network interface card, and (3) a run-to-completion model in network processing and accelerator offloading to reduce overhead with context switching. We show that the system can improve performance by 66.40% compared with a simple implementation using kernel protocol stack and confirmed the performance improvement with a virtual radio access network use case as a low-latency application. Furthermore, we show that this performance can also be achieved in practical usage in data center networks. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
- View/download PDF
36. Neural network accelerator with fast buffer design for computer vision.
- Author
-
Hsia, Shih-Chang and Zhang, Yu-Xiang
- Abstract
Recently, the neural networks with convolution computation is widely used for image classification and recognition. For real-time implementation, the video buffer is required to store the image temperately. However, traditional buffers like CLSB (content line shift buffer) may experience delays during the read process, particularly when encountering line breaks or image changes. As for N × N convolution, the delay time is N−1 clocks for every row changing. As the image width is W, the delay time is 2W + N clocks for every frame changing. These delays can impact the efficiency and performance of the neural network. To overcome this challenge, this paper presented novel buffer design to avoid the delay at the line ends and frame change. By proactively fetching data ahead of time, the buffer can dynamically schedule the read operation and ensure that the subsequent data are correctly placed for efficient processing. This improvement in read latency contributes to enhanced performance and better utilization of computational resources within the hardware system. Then the full convolutional network accelerator is implemented with the fast buffer design and common computational kernel to save the hardware cost based on LeNet model. The results show that the accuracy can achieve 99.1% with MNIST dataset verification. By eliminating the waiting time, the modified buffer allows for more efficient processing in the image, and the fame rate for a computer vision can achieve 46 per second, to meet the real-time requirement. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
- View/download PDF
37. Application of Unsymmetrical Ureas as a Catalytic Additive for Curing Epoxy Resins (Review).
- Author
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Eldyaeva, G. B. and Tkachuk, A. I.
- Abstract
This paper presents a review of scientific and technical literature on the main production methods, various fields of application, and use of unsymmetrical ureas as an accelerator for the curing processes of epoxy compositions. Mechanisms of reactions between ureas and the widely used latent hardener dicyandiamide are presented, and the characteristics of resulting epoxy resins, as well as prepregs based on them, are considered. The possibility of using substituted ureas as an independent cross-linking agent for epoxy resins is mentioned. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
- View/download PDF
38. Intermittent-Aware Design Exploration of Systolic Array Using Various Non-Volatile Memory: A Comparative Study.
- Author
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Taheri, Nedasadat, Tabrizchi, Sepehr, and Roohi, Arman
- Subjects
ELECTRIC power failures ,SPATIAL systems ,MATHEMATICAL optimization ,COMPARATIVE studies ,ENERGY consumption - Abstract
This paper conducts a comprehensive study on intermittent computing within IoT environments, emphasizing the interplay between different dataflows—row, weight, and output—and a variety of non-volatile memory technologies. We then delve into the architectural optimization of these systems using a spatial architecture, namely IDEA, with their processing elements efficiently arranged in a rhythmic pattern, providing enhanced performance in the presence of power failures. This exploration aims to highlight the diverse advantages and potential applications of each combination, offering a comparative perspective. In our findings, using IDEA for the row stationary dataflow with AlexNet on the CIFAR10 dataset, we observe a power efficiency gain of 2.7% and an average reduction of 21% in the required cycles. This study elucidates the potential of different architectural choices in enhancing energy efficiency and performance in IoT systems. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
- View/download PDF
39. Investigation into the Operation Modes of RF Systems of Booster–Nuclotron Synchrotrons in Optimizing the Capture and Acceleration of Carbon Ion Beams.
- Author
-
Brovko, O. I., Volodin, A. A., Grebentsov, A. Yu., Prozorov, O. V., Syresin, E. M., and Sidorin, A.O.
- Abstract
This paper describes experiments with the main parameters of the RF accelerating systems of the Booster and the Nuclotron of the Nuclotron based Ion Collider fAcility (NICA) complex, which affect the capture and acceleration, as well as the additional hardware solutions used in this case. The operating modes of accelerating stations of the Booster and the Nuclotron are considered. In particular, the paper describes the principle of formation of the law of the change in the amplitude of the accelerating voltage during the adiabatic capture of particles both in the Booster and in the Nuclotron, as well as the features of setting the sequence of synchronization pulses. [ABSTRACT FROM AUTHOR]
- Published
- 2023
- Full Text
- View/download PDF
40. High-performance computing for SKA transient search: Use of FPGA-based accelerators
- Author
-
Aafreen, R., Abhishek, R., Ajithkumar, B., Vaidyanathan, Arunkumar M., Barve, Indrajit V., Bhattramakki, Sahana, Bhat, Shashank, Girish, B. S., Ghalame, Atul, Gupta, Y., Hayatnagarkar, Harshal G., Kamini, P. A., Karastergiou, A., Levin, L., Madhavi, S., Mekhala, M., Mickaliger, M., Mugundhan, V., Naidu, Arun, Oppermann, J., Pandian, B. Arul, Patra, N., Raghunathan, A., Roy, Jayanta, Sethi, Shiv, Shaw, B., Sherwin, K., Sinnen, O., Sinha, S. K., Srivani, K. S., Stappers, B., Subrahmanya, C. R., Prabu, Thiagaraj, Vinutha, C., Wadadekar, Y. G., Wang, Haomiao, and Williams, C.
- Published
- 2023
- Full Text
- View/download PDF
41. Efficient number theoretic transform accelerator for CRYSTALS-Kyber.
- Author
-
Toan Nguyen, Hoang Anh, Hung Nguyen, Trang Hoang, and Linh Tran
- Subjects
FIELD programmable gate arrays ,ADDITION (Mathematics) ,CRYPTOGRAPHY - Abstract
The national institute of standards and technology (NIST) has presented its draft of the module-lattice-based key-encapsulation mechanism standard (MLBKEMS), choosing cryptographic suite for algebraic lattices (CRYSTALS)- Kyber as the base encryption. Existing hardware implementations of modern cryptography will need to process the new standard efficiently. The primary process in CRYSTALS-Kyber key-encapsulation mechanism (KEM) is the number theoretic transform (NTT), which requires heavy computing power. This paper contributes an efficient hardware accelerator for NTT and inverse NTT (INTT) by CRYSTAL-Kyber parameters. The proposed design utilizes the K-RED algorithm for reducing polynomial multiplication. It also incorporates the Brent-Kung method for efficient modular addition and subtraction operation with an address generator to control the sequences of computation. On the Xilinx Artix 7 field programmable gate array (FPGA), our design achieves 262 MHz clock speed, utilizing only 1405 LUTs. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
- View/download PDF
42. The Prototype of a Magnetic Field Compensator.
- Author
-
Alekseev, V. I., Baskov, V. A., Dronov, V. A., Gorbov, L. A., L'vov, A. I., Koltsov, A. V., Polyansky, V. V., Sidorin, S. S., and Khafizova, E. A.
- Abstract
The paper describes the design of a prototype magnetic field compensator intended to eliminate the influence of the edge magnetic field of the S-25P Pakhra accelerator magnet, Lebedev Physical Institute, on the electron beam during its output. The results of the study showed that this design could reduce an external magnetic field of B
0 ~ 0.1 T to zero values inside the prototype. [ABSTRACT FROM AUTHOR]- Published
- 2024
- Full Text
- View/download PDF
43. Comparative Study of Keccak SHA-3 Implementations.
- Author
-
Dolmeta, Alessandra, Martina, Maurizio, and Masera, Guido
- Subjects
COMPARATIVE studies ,RESEARCH personnel ,CRYPTOGRAPHY ,SCALABILITY ,DECISION making - Abstract
This paper conducts an extensive comparative study of state-of-the-art solutions for implementing the SHA-3 hash function. SHA-3, a pivotal component in modern cryptography, has spawned numerous implementations across diverse platforms and technologies. This research aims to provide valuable insights into selecting and optimizing Keccak SHA-3 implementations. Our study encompasses an in-depth analysis of hardware, software, and software–hardware (hybrid) solutions. We assess the strengths, weaknesses, and performance metrics of each approach. Critical factors, including computational efficiency, scalability, and flexibility, are evaluated across different use cases. We investigate how each implementation performs in terms of speed and resource utilization. This research aims to improve the knowledge of cryptographic systems, aiding in the informed design and deployment of efficient cryptographic solutions. By providing a comprehensive overview of SHA-3 implementations, this study offers a clear understanding of the available options and equips professionals and researchers with the necessary insights to make informed decisions in their cryptographic endeavors. [ABSTRACT FROM AUTHOR]
- Published
- 2023
- Full Text
- View/download PDF
44. Memory-Tree Based Design of Optical Character Recognition in FPGA.
- Author
-
Yu, Ke, Kim, Minguk, and Choi, Jun Rim
- Subjects
OPTICAL character recognition ,ARTIFICIAL intelligence ,ENGLISH letters ,HETEROGENEOUS computing ,COMPUTER vision ,COMPUTER systems - Abstract
As one of the fields of Artificial Intelligence (AI), Optical Character Recognition (OCR) systems have wide application in both industrial production and daily life. Conventional OCR systems are commonly designed and implement data computation on the basis of microprocessors; the performance of the processor relates to the effect of the computation. However, due to the "Memory-wall" problem and Von Neumann bottlenecks, the drawbacks of traditional processor-based computing for OCR systems are gradually becoming apparent. In this paper, an approach based on the Memory-Centric Computing and "Memory-Tree" algorithm has been proposed to perform hardware optimization of traditional OCR systems. The proposed algorithm was first designed in software implementation using C/C++ and OpenCV to verify the feasibility of the idea and then the RTL conversion of the algorithm was done using the Xilinx Vitis High Level Synthesis (HLS) tool to implement the hardware. This work chose Xilinx Alveo U50 FPGA Accelerator to complete the hardware design, which can be connected to the x86 CPU in the PC by PCIe to form heterogeneous computing. The results of the hardware implementation show that the system this work designed can recognize characters of English capital letters and numbers within 34.24 us. The power of FPGA is 18.59 W, which saves 77.87% of energy consumption compared to the 84 W of the processor in PC. [ABSTRACT FROM AUTHOR]
- Published
- 2023
- Full Text
- View/download PDF
45. An Improved Match Method of Capacitive Divider for Measurement of Nanosecond-Range HV Pulses.
- Author
-
Yu, Bin-Xiong, Su, Jian-Cang, Li, Rui, Zhao, Liang, Zeng, Bo, Cheng, Jie, and Liu, Jin-Liang
- Subjects
MEASUREMENT ,SIGNAL-to-noise ratio ,ELECTRIC lines ,ELECTRIC potential measurement ,PULSED power systems - Abstract
In this paper, a new match circuit of the capacitive divider is studied. Using the proposed match circuit, the signal measured by the capacitive divider will not be secondarily attenuated near the accelerator, and the secondary attenuation is done at the terminal end of the cable which is located in a shielding room with a good electromagnetic environment. So, the proposed circuit has a better anti-interference capability than the traditional terminal-end match circuit. The result of the theoretic analysis shows that the proposed match circuit is equivalent with the traditional terminal-end match circuit when the parameters of the circuit are well chosen. Rectangular pulse response of the proposed match circuit is tested based on an equivalent circuit. It shows that the proposed match circuit has a good pulse response characteristic for rectangular pulse with a rise time of 5 ns, and the output waveform of the match circuit has a flattop jitter less than 1%. The match circuit proposed in this paper is utilized to measure the diode voltage of the accelerator in our laboratory. It is found that the high-frequency interference on the output waveform measured by the new match circuit is much smaller than that measured by the traditional terminal-end match circuit, which proves that the match circuit proposed in this paper is an effective method for increasing the signal-to-noise ratio of capacitive divider for measurement of nanosecond-range HV pulse. [ABSTRACT FROM AUTHOR]
- Published
- 2019
- Full Text
- View/download PDF
46. Preparation and performance of phosphogypsum-based polymer foam lightweight soil.
- Author
-
YANG Fan, LIU Yamei, CHEN Shengying, JIANG Wei, ZHANG Zhe, and XU Fang
- Subjects
FOAM ,WATER softening ,POLYMERS ,ABSORPTION coefficients ,PHOSPHOGYPSUM ,GYPSUM - Abstract
In this paper, phosphogypsum-based polymer foam lightweight soil was prepared by taking phosphogypsum as fine aggregate and adding coagulant and prefabricated foam. The changes in the properties of the material were studied deeply in terms of flow rate, setting time, mechanical properties, water absorption and softening coefficient, combined with XRD and SEM for microscopic testing. The results show that mortar test blocks with excellent performance can be prepared under the conditions of sand-to-ash ratio 0.6, water-to-material ratio 0.5 and quicklime 4%. The initial and final setting times are 210 and 260 minutes, the compressive strength of the specimen can reach 2.8 MPa after 3 days, and 11.9 MPa after 28 days. Foam lightweight soil with different wet density can be prepared by adjusting the amount of prefabricated foam, providing a new way for phosphogypsum resource application. [ABSTRACT FROM AUTHOR]
- Published
- 2023
47. 基于深度强化学习的雷达智能抗干扰决策 FPGA 加速器设计.
- Author
-
李梓瑜, 葛 芬, 张劲东, and 赵家琛
- Abstract
Copyright of Journal of Data Acquisition & Processing / Shu Ju Cai Ji Yu Chu Li is the property of Editorial Department of Journal of Nanjing University of Aeronautics & Astronautics and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
- Published
- 2023
- Full Text
- View/download PDF
48. High-Throughput and Power-Efficient Convolutional Neural Network Using One-Pass Processing Elements.
- Author
-
Sivasankari, B., Shunmugathammal, M., Appathurai, Ahilan, and Kavitha, M.
- Subjects
CONVOLUTIONAL neural networks - Abstract
In recent decades, convolutional neural network (CNN) has become essential in many real-time applications due to its massive computational ability. But its use in portable devices is limited due to its high computation requirements. This paper proposes a novel One-Pass Processing Element (OPPE) to mitigate this limitation. The proposed OPPE removes redundant computations by eliminating those with zeros that leads to low area as well as low power consumption. The proposed OPPE model is evaluated with the help of VGG-16-based CNN accelerator. The proposed OPPE design reduces the number of four-input LUTs by 5.19%, 15.91%, 10.06% and 4.93% and the power consumption by 4.26%, 7.36%, 5.81% and 1.55% when compared with the conventional processing element (PE), activation gating PE, weight gating PE and zero gating PE, respectively. The proposed CNN accelerator design using OPPE achieves high throughput with less resource utilization. [ABSTRACT FROM AUTHOR]
- Published
- 2022
- Full Text
- View/download PDF
49. Analysis and design of a 2.45 GHz RF power source for a miniature electron cyclotron resonance ion source.
- Author
-
Rahimpour, Hamid, Mirzaei, HamidReza, and Satri, Masoomeh Yarmohammadi
- Subjects
RADIO frequency ,CYCLOTRON resonance ,ELECTRONIC amplifiers ,HEAVY ion accelerators ,STATISTICAL hypothesis testing - Abstract
A high-power solid-sate based radio frequency power source is introduced in this paper. Solid-state based amplifiers are much more efficient than microwave tubes and can be used in compact electron cyclotron resonance (ECR) ion sources. A reliable negative bias voltage controller is proposed to drive the power source's main power amplifier, which can deliver up to 300 W power to the ion chamber. The selected high-power transistor is internally matched on the input side but the output side is matched in this paper to deliver maximum power to the load. The bias circuit was fabricated on an FR4 substrate and measurement results were obtained to verify the functionality of the bias sequencer. Analog simulations were done by LTSPICE and high-frequency simulations are performed with the momentum RF simulator of Advanced Design System (ADS). The output power of the proposed structure is tunable with 0.5 dB resolution and can deliver 300 mW to 300 W power to the ion chamber. [ABSTRACT FROM AUTHOR]
- Published
- 2022
- Full Text
- View/download PDF
50. THE MAGNETIC FIELD PRODUCED BY A PROTONS BEAM WITH THE THREE-AXIAL GAUSS DISTRIBUTION.
- Author
-
Bednarekt, Stanisław and Płoszajsk, Julian
- Subjects
MAGNETIC fields ,PROTON beams ,GAUSS'S law (Gravitation) - Abstract
Copyright of Bulletin de la Société des Sciences et des Lettres de Lodz is the property of Lodz Scientific Society / Lodzkie Towarzystwo Naukowe and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
- Published
- 2018
- Full Text
- View/download PDF
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