1,938 results
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2. Supply Of Heme Chip Cellulose Acetate Paper Based Microchip, Eppendorf Tube 1 5 Microltr, Micropipette Tips 50 Microltr, Micropipette Tips 200 Microltr, Test Tube Stands, Pricking Niddles Lancet, Glass Slide, Micropipette 10-100 Microltr, Micropipette 100
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Cellulose ,Integrated circuits ,Heme ,Semiconductor chips ,Ethylenediaminetetraacetic acid ,Standard IC ,Business, international - Abstract
Tenders are invited for Supply of Heme Chip cellulose acetate paper based microchip, Eppendorf Tube 1 5 Microltr, Micropipette Tips 50 Microltr, Micropipette Tips 200 Microltr, Test Tube Stands, Pricking [...]
- Published
- 2024
3. Supply Of Power Supply Card 6030 Canon, Cmos Battery Round, Cmos Battery Ups, Mosfet, Paper Pick Up Roller Qty : 35
- Subjects
Metal oxide semiconductor field effect transistors ,Integrated circuits ,Circuit components ,Semiconductor chips ,Standard IC ,Semiconductor device ,Business, international - Abstract
Tenders are invited for Supply of Power Supply Card 6030 Canon, Cmos Battery Round, Cmos Battery Ups, Mosfet, Paper Pick Up Roller Qty : 35 Tender Category : Goods OpeningDate [...]
- Published
- 2023
4. Supply Of Capacitor Fixed Paper Dielectric 0 6uf, Resistor Voltage Sensitive 680v Vdc, Transistor N Channel Mosfet Type Irfp 26, Transistor Bc 107 B, Transistor Type 2n 5401 Drg No 48 033 12, Transistor Type Cdil Csc 1815 Gr Ptr, Opto Coupler, Transistor
- Subjects
Metal oxide semiconductor field effect transistors ,Integrated circuits ,Circuit components ,Semiconductor chips ,Electronic components industry ,Capacitors ,Standard IC ,Semiconductor device ,Business, international - Abstract
Tenders are invited for Supply of Capacitor Fixed Paper Dielectric 0 6uf, Resistor Voltage Sensitive 680v Vdc, Transistor N Channel Mosfet Type Irfp 26, Transistor Bc 107 B, Transistor Type [...]
- Published
- 2023
5. Supply of Capacitor Fixed Paper Dielectric 0 6uf, Resistor Voltage Sensitive 680v Vdc, Semiconductor Device Diode Type Tvs Ih 6, Transistor N Channel Mosfet Type Irfp 26, Dc Convertor Dc Dc Connector Vicor Bmr, Transistor Bc 107 B, Transistor Type 2n 5401
- Subjects
Metal oxide semiconductor field effect transistors ,Integrated circuits ,Semiconductor chips ,Electronic components industry ,Capacitors ,Connectors ,Standard IC ,Connector ,Business, international - Abstract
Tenders are invited for Supply of Capacitor Fixed Paper Dielectric 0 6uf, Resistor Voltage Sensitive 680v Vdc, Semiconductor Device Diode Type Tvs Ih 6, Transistor N Channel Mosfet Type Irfp [...]
- Published
- 2023
6. Pumpless deterministic lateral displacement separation using a paper capillary wick.
- Author
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Aghajanloo, Behrouz, Ejeian, Fatemeh, Frascella, Francesca, Marasso, Simone L., Cocuzza, Matteo, Tehrani, Alireza Fadaei, Nasr Esfahani, Mohammad Hossein, and Inglis, David W.
- Subjects
- *
MICROFLUIDICS , *FLOW separation , *MICROFLUIDIC devices , *CELL separation , *CAPILLARIES , *INTEGRATED circuits - Abstract
Deterministic lateral displacement (DLD) is a passive separation method that separates particles by hydrodynamic size. This label-free method is a promising technique for cell separation because of its high size resolution and insensitivity to flow rate. Development of capillary-driven microfluidic technologies allows microfluidic devices to be operated without any external power for fluid pumping, lowering their total cost and complexity. Herein, we develop and test a DLD-based particle and cell sorting method that is driven entirely by capillary pressure. We show microchip self-filling, flow focusing, flow stability, and capture of separated particles. We achieve separation efficiency of 92% for particle–particle separation and more than 99% efficiency for cell–particle separation. The high performance of driven flow and separation along with simplicity of the operation and setup make it a valuable candidate for point-of-care devices. [ABSTRACT FROM AUTHOR]
- Published
- 2023
- Full Text
- View/download PDF
7. iST: [Paper Publish] IPFA 2022
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Integrated circuits ,Semiconductor chips ,Epitaxy ,Standard IC - Abstract
June 20 -- Integrated Service Technology Inc. issued the following news release: DateÜ2022/7/18-20 PlaceÜMarina Bay Sands, Singapore IPFA(International symposium on the physical & failure analysis of integrated circuits) is a [...]
- Published
- 2022
8. Supply Of Ssd Xstr N Chan Mrf 174, Bty 11 Mah N1 Mh, Syscon A7fh, Hmc Thick Filter B Pass, Hmc Thick Fltr Bmc 1527, Ssd Lin Max 764, Xtal Filter Bp 6kz, Dc Dc Vicor, Mosfet Type Irep 260, Capacitor Fixed Paper 250v, Ic 4n 35 - Regram Spares. Qty :
- Subjects
Metal oxide semiconductor field effect transistors ,Integrated circuits ,Circuit components ,Semiconductor chips ,Electronic components industry ,Capacitors ,Standard IC ,Semiconductor device ,Business, international - Abstract
Tenders are invited for Supply of ssd xstr n chan mrf 174, bty 11 mah n1 mh, syscon a7fh, hmc thick filter b pass, hmc thick fltr bmc 1527, ssd [...]
- Published
- 2023
9. Supply Of|z1 4375 104 453 14 A7fh Syscon Ic, Z1 5910 017865 Cap Fxd Paper Die Elect 0 6uf 250v, Z1 4295 123 202 95 Mosfet Irfp 260, Z6 1160 014 234 71 Filter Conn Assy 3n, Z1 3020 004210 Gear Belt, Z1 Da3b2701800b3c1 Ic Dilar Icum91214a1b Boq Title
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Metal oxide semiconductor field effect transistors ,Integrated circuits ,Circuit components ,Semiconductor chips ,Standard IC ,Semiconductor device ,Business, international - Abstract
Tenders are invited for Supply of /z1 4375 104 453 14 a7fh syscon ic, z1 5910 017865 cap fxd paper die elect 0 6uf 250v, z1 4295 123 202 95 [...]
- Published
- 2023
10. MLCAD: A Survey of Research in Machine Learning for CAD Keynote Paper.
- Author
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Rapp, Martin, Amrouch, Hussam, Lin, Yibo, Yu, Bei, Pan, David Z., Wolf, Marilyn, and Henkel, Jorg
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MACHINE learning , *CIRCUIT complexity , *COMPUTER-aided design , *ARTIFICIAL neural networks , *INTEGRATED circuits , *CONFIGURATION space , *MULTICASTING (Computer networks) - Abstract
Due to the increasing size of integrated circuits (ICs), their design and optimization phases (i.e., computer-aided design, CAD) grow increasingly complex. At design time, a large design space needs to be explored to find an implementation that fulfills all specifications and then optimizes metrics like energy, area, delay, reliability, etc. At run time, a large configuration space needs to be searched to find the best set of parameters (e.g., voltage/frequency) to further optimize the system. Both spaces are infeasible for exhaustive search typically leading to heuristic optimization algorithms that find some tradeoff between design quality and computational overhead. Machine learning (ML) can build powerful models that have successfully been employed in related domains. In this survey, we categorize how ML may be used and is used for design-time and run-time optimization and exploration strategies of ICs. A metastudy of published techniques unveils areas in CAD that are well explored and underexplored with ML, as well as trends in the employed ML algorithms. We present a comprehensive categorization and summary of the state of the art on ML for CAD. Finally, we summarize the remaining challenges and promising open research directions. [ABSTRACT FROM AUTHOR]
- Published
- 2022
- Full Text
- View/download PDF
11. ETS 2021 BEST PAPER
- Author
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Hellebrand, Sybille and Sonza Reorda, Matteo
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Microelectronics ,Integrated circuits ,Microelectrònica ,Spintronics ,Circuits integrats ,Espintrònica ,Enginyeria electrònica::Microelectrònica [Àrees temàtiques de la UPC] - Published
- 2022
12. Vertical integration of multi-electrodes inside a single sheet of paper and the control of the equivalent circuit for high-density flexible supercapacitors.
- Author
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Kim, Yeon Woo, Oh, In Hyeok, Choi, Seyoung, Nam, Inho, and Chang, Suk Tai
- Subjects
- *
VERTICAL integration , *FLEXIBLE printed circuits , *SUPERCAPACITORS , *INTEGRATED circuits , *ENERGY storage , *WAXES - Abstract
[Display omitted] • A method for fabricating integrated multi-electrodes inside a single sheet of paper. • A paper used in two dimensions used as a three-dimensional scaffold. • The control of the equivalent circuit without changing external circuits and wires. Paper is an excellent substrate for flexible devices due to its various advantages such as flexibility, porosity, lightness, and thinness. Its inherent characteristics can be also exploited to overcome the limitations of conventional substrates, such as weak adhesion and large mass densities. Here, we propose a method for fabricating vertically integrated multi-electrodes within only a single sheet of paper. Despite the randomly distributed fibrous networks in a paper, the multi-layered electrodes were uniformly formed and completely separated by applying a removable hydrophobic wax barrier confinement inside a single sheet of paper. The integrated multi-layer electrodes inside a single sheet of paper mean that conventional two-dimensional planes can be used as three-dimensional scaffolds. The highly integrated electrodes and circuit systems are located within only a sheet of paper, making a new possibility to design maximizing the energy storage performance, integrated circuit systems, and significantly decreasing the thickness of the system without external complex structure. In consequence, this unique platform can circumvent most of the fabrication challenges related to two-dimensional energy storage sheets. [ABSTRACT FROM AUTHOR]
- Published
- 2023
- Full Text
- View/download PDF
13. Design-for-Trust Techniques for Digital Microfluidic Biochip Layout With Error Control Mechanism ⋆ * A preliminary version of this paper appeared in the Proc. of IEEE Region 10 Symposium (TENSYMP), 2019 [1].
- Author
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Gountia, Debasis and Roy, Sudip
- Abstract
Among recent technological advances, microfluidic biochips have been leading a prominent solution for healthcare and miniaturized bio-laboratories with the assurance of high sensitivity and reconfigurability. On increasing more unreliable communication networks day-by-day, technological shifts in the fields of communication and security are now converging. In today's cyber threat landscape, these microfluidic biochips are ripe targets of powerful cyber-attacks from different hackers or cyber-criminals. Hence, securing such systems is of paramount importance. This paper presents the security aspects of digital microfluidic biochip layout to protect the confidentiality of layout data from unscrupulous people and man-in-the-middle attacks. We propose an authentication mechanism with an error control mechanism that provides reliability, authentication, trustworthy and safety for both storage and communication of GDS, i.e., Graphical Design System, file generally used for digital microfluidic biochip layouts. Simulation results articulate the efficacy of the proposed security model without the overhead of the bioprotocol completion time. The proposed scheme, which used AES as an encryption algorithm with a 256-bit encryption key, has also shown a speedup of 6.0 (with 85% efficiency) faster than the prior efficient scheme. We hope to develop a secure layout design flow for biochips to achieve better resistance to any attack. [ABSTRACT FROM AUTHOR]
- Published
- 2022
- Full Text
- View/download PDF
14. A digital delay locked loop with a monotonic delay line.
- Author
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Liu, Jen‐Chieh and Yang, Chuan
- Subjects
DELAY lines ,DIGITAL integrated circuits ,ELECTRONIC paper ,COMPLEMENTARY metal oxide semiconductors ,UNITS of time - Abstract
This paper proposes a digital delay locked loop (DLL) with a monotonic delay line (DL). This DLL adopts the calibration mode to reduce the non‐monotonic effects for the coarse‐tuning delay line (CTDL) and the fine‐tuning delay line (FTDL). The calibration mode detects the delay time of the delay unit, the timing resolution of CTDL, to adjust the delay range of the FTDL. Thus, the calibration mode can limit the overlap range of the delay time between the CTDL and the FTDL. The proposed DLL was implemented using a 0.18‐μm CMOS process, and the RMS and the peak‐to‐peak jitters of the DLL were 0.21% and 1.72%, respectively, at 560 MHz. [ABSTRACT FROM AUTHOR]
- Published
- 2023
- Full Text
- View/download PDF
15. NVIDIA publishes papers on deployment of TeraView's EOTPR system.
- Subjects
FAILURE analysis ,INTEGRATED circuits ,SEMICONDUCTOR industry ,TERAHERTZ technology - Abstract
NVIDIA has published papers on the deployment of TeraView's EOTPR system, which is used for semiconductor chip-level failure analysis. The papers detail case studies on integrated circuit failures and highlight the effectiveness of the EOTPR product in identifying the causes of these issues. NVIDIA has integrated EOTPR into their failure analysis workflow and is working to improve its throughput and workflow for volume analysis. TeraView, the provider of the EOTPR system, expresses gratitude for NVIDIA's confidence in their technology and collaboration. In other news, ORCA Computing has acquired the Integrated Photonics Division of GXC, a provider of private cellular network solutions. The acquisition allows ORCA to bring hybrid photonic materials to market, enhancing the performance of their quantum computing products. GXC will transfer its photonics-related assets to ORCA, and GXC Photonics staff will merge with ORCA's existing teams. [Extracted from the article]
- Published
- 2024
16. Load balancing in the internet of things using fuzzy logic and shark smell optimization algorithm
- Author
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Rui, Xin, Wu, Junying, Zhao, Jianbin, and Khamesinia, Maryam Sadat
- Published
- 2021
- Full Text
- View/download PDF
17. Visual management of medical things with an advanced color-change RFID tag.
- Author
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Sun, Ran, Rahmadya, Budi, Kong, Fangyuan, and Takeda, Shigeki
- Subjects
RADIO frequency identification systems ,RADIO waves ,ENERGY harvesting ,INTEGRATING circuits ,INTEGRATED circuits ,SALT - Abstract
This paper proposes a visual management scheme of medical things with a color-change radio frequency identification (RFID) tag. The color-change RFID tag employs a specific RFID tag integrated circuit (IC) and a laminated pH-indicating paper. The IC has energy harvesting and switched ground functions, which enable it to generate electricity to the laminated pH-indicating paper. This phenomenon causes electrolysis of NaCl solution absorbed in the laminated pH-indicating paper. Electrolysis generates alkaline matter to change the color of the pH-indicating paper. This paper gives a new and sensitive structure of the laminated pH-indicating paper. The proposed advanced color-change RFID tag with new laminated pH-indicating paper succeeds in changing its color noticeably at a 1 m distance using an RFID reader radiating 1 W radio waves. The color change was observed 3–5 s after starting radio wave irradiation. The results of this experiment also confirm that the changed color can be held for over 24 h. Furthermore, two demonstrations of the visual management system of medical things (patient clothes and sanitizers) are presented. [ABSTRACT FROM AUTHOR]
- Published
- 2021
- Full Text
- View/download PDF
18. Special issue on selected papers on experimental research on emerging electronic and optical materials for device applications.
- Author
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Sarkar, Angsuman, Nirmal, D., and Sarkar, Chandan Kumar
- Subjects
OPTICAL materials ,ELECTRONIC materials ,OPTICAL devices ,MATERIALS science ,INTEGRATED circuits - Abstract
This special issue contains papers obtained through open call-for-papers as well as from the selected extended versions of the papers presented in the 4th International Conference "2021 Devices for Integrated Circuit (DevIC)", held at Kalyani Government Engineering College from May 19-20, 2021. This special issue publishes a collection of papers that were submitted to the Journal of Materials Science: Materials in Electronics on the theme of experimental electronic and optical materials for nano-dimensional device applications. [Extracted from the article]
- Published
- 2022
- Full Text
- View/download PDF
19. Optimization of the 3D multi-level SOT-MRAMs.
- Author
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Lin, Hui and Jiang, Yanfeng
- Subjects
MOORE'S law ,SEMICONDUCTOR storage devices ,INTEGRATED circuits ,ERROR rates - Abstract
With the development of electronic technology, semiconductor memory is gradually shifting toward smaller area with less power consumption. SOT-MRAM is one of the competitive substitutes for DRAM and SRAM due to its superior endurance and switching speed. In contrast to STT-MRAM, the separation of read and write routes allows SOT-MRAM to have a lower error rate and higher lifetime, but this comes at the expense of the memory density. In recent years, vertical integrated circuits have relied on TSV to complete 3D stacking to ease the pressure of Moore's Law on scaling circuits. SOT-MRAM can take advantage of 3D stacking to reduce power and latency. More importantly, the density of SOT-MRAM can be improved at the same time. In the paper, simulation is conducted based on DESTINY, with the TSV model supplemented to NVSIM to evaluate the performance of MRAM 3D structures. The 3D SOT-MRAM structure in DESTINY can be implemented with a bus layer and interconnect structure between layers, which greatly reduces the expense of area. However, the 3D structure requires a more complex interconnect structure to truly meet the requirements of high density. For this reason, 3D model of unit interconnection using TSV is presented in the paper. Memory has several components, of which the memory array is the one with the largest area share. This paper explores the spatial structure of the array and proposes a new model which allows more complex interconnect structures to be accomplished on the same area. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
- View/download PDF
20. Privacy-Preserving Federated Deep Learning Diagnostic Method for Multi-Stage Diseases.
- Author
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Jinbo Yang, Hai Huang, Lailai Yin, Jiaxing Qu, and Wanjuan Xie
- Subjects
ARTIFICIAL neural networks ,MACHINE learning ,INTEGRATED circuits ,DATA privacy ,ALGORITHMS ,NATURAL languages ,DEEP learning - Abstract
Diagnosing multi-stage diseases typically requires doctors to consider multiple data sources, including clinical symptoms, physical signs, biochemical test results, imaging findings, pathological examination data, and even genetic data. When applying machine learning modeling to predict and diagnose multi-stage diseases, several challenges need to be addressed. Firstly, the model needs to handle multimodal data, as the data used by doctors for diagnosis includes image data, natural language data, and structured data. Secondly, privacy of patients' data needs to be protected, as these data contain the most sensitive and private information. Lastly, considering the practicality of the model, the computational requirements should not be too high. To address these challenges, this paper proposes a privacy-preserving federated deep learning diagnostic method for multi-stage diseases. This method improves the forward and backward propagation processes of deep neural network modeling algorithms and introduces a homomorphic encryption step to design a federated modeling algorithm without the need for an arbiter. It also utilizes dedicated integrated circuits to implement the hardware Paillier algorithm, providing accelerated support for homomorphic encryption in modeling. Finally, this paper designs and conducts experiments to evaluate the proposed solution. The experimental results show that in privacy-preserving federated deep learning diagnostic modeling, the method in this paper achieves the same modeling performance as ordinary modeling without privacy protection, and has higher modeling speed compared to similar algorithms. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
- View/download PDF
21. Assessment of 2D-FET Based Digital and Analog Circuits on Paper.
- Author
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Vatalaro, Massimo, De Rose, Raffaele, Lanuzza, Marco, Iannaccone, Giuseppe, and Crupi, Felice
- Subjects
- *
DIGITAL electronics , *FIELD-effect transistors , *INTEGRATING circuits , *MOLYBDENUM disulfide , *INTEGRATED circuits , *PHYSICAL mobility , *ANALOG circuits - Abstract
Two-dimensional (2D) materials represent an emerging technology for transistor electronics in view of their attractive electrical and mechanical properties. This work investigates molybdenum disulfide (MoS 2) based field-effect transistors (FETs) fabricated on paper substrate for designing both digital and analog circuits, such as inverter, current mirror, and Physical Unclonable Function (PUF) bitcell. Electrical measurements of fabricated devices are exploited to setup a look-up-table (LUT)-based Verilog-A model to be integrated in a commercial circuit simulator. Obtained results prove the potential of paper-based MoS 2 FETs as building blocks of next-generation integrated circuits for a wide range of practical applications. [ABSTRACT FROM AUTHOR]
- Published
- 2021
- Full Text
- View/download PDF
22. 37.1: Invited Paper: Nanosheet High Mobility SnO2‐SnO Complementary TFTs for System‐on‐Display and Monolithic Three‐Dimensional Integrated Circuit.
- Author
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Chin, Albert, Yen, Te Jui, and Gritsenko, Vladimir
- Subjects
THREE-dimensional integrated circuits ,INTEGRATED circuits ,TIN oxides - Abstract
The top‐gate 4.5‐nm‐thick SnO2 nanosheet nTFT has the high 136 cm2/Vs field‐effect mobility (μFE), sharp 1.5×108 on‐current/off‐current (ION/IOFF), and fast turn‐on subthreshold slope (SS) of 108 mV/decade. The top‐gate 7‐nm‐thick nanosheet SnO pTFT has a high μFE of 4.4 cm2/Vs, large ION/IOFF of 1.2×105, and SS of 526 mV/decade. These CTFTs will enable the system‐on‐panel (SoP) and Monolithic Three‐Dimensional (3D) Integrated Circuit (IC). [ABSTRACT FROM AUTHOR]
- Published
- 2022
- Full Text
- View/download PDF
23. FATE: A Flexible FPGA-Based Automatic Test Equipment for Digital ICs.
- Author
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Zhang, Jin, Liu, Zhenghui, Hu, Xiao, Liu, Peixin, Hu, Zhiling, and Kuang, Lidan
- Subjects
AUTOMATIC test equipment ,INTEGRATED circuit design ,DIGITAL integrated circuits ,INTEGRATED circuits manufacturing ,DIGITAL signal processing ,INTEGRATED circuits - Abstract
The limits of chip technology are constantly being pushed with the continuous development of integrated circuit manufacturing processes and equipment. Currently, chips contain several billion, and even tens of billions, of transistors, making chip testing increasingly challenging. The verification of very large-scale integrated circuits (VLSI) requires testing on specialized automatic test equipment (ATE), but their cost and size significantly limit their applicability. The current FPGA-based ATE is limited in its scalability and support for few test channels and short test vector lengths. As a result, it is only suitable for testing specific chips in small-scale circuits and cannot be used to test VLSI. This paper proposes a low-cost hardware and software solution for testing digital integrated circuits based on design for testability (DFT) on chips, which enables the functional and performance test of the chip. The solution proposed can effectively use the resources within the FPGA to provide additional test channels. Furthermore, the round-robin data transmission mode can also support test vectors of any length and it can satisfy different types of chip test projects through the dynamic configuration of each test channel. The experiment successfully tested a digital signal processor (DSP) chip with 72 scan test pins (theoretically supporting 160 test pins). Compared to our previous work, the work in this paper increases the number of test channels by four times while reducing resource utilization per channel by 37.5%, demonstrating good scalability and versatility. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
- View/download PDF
24. A Method for Automatically Predicting the Radiation-Induced Vulnerability of Unit Integrated Circuits.
- Author
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Dong, Rui, Lu, Hongliang, Yang, Caozhen, Zhang, Yutao, Yao, Ruxue, Wang, Yujian, and Zhang, Yuming
- Subjects
INTEGRATED circuit design ,SINGLE event effects ,ARTIFICIAL neural networks ,SOFT errors ,SEMICONDUCTOR technology ,INTEGRATED circuits - Abstract
With the rapid development of semiconductor technology, the reduction in device operating voltage and threshold voltage has made integrated circuits more susceptible to the effects of particle radiation. Moreover, as process sizes decrease, the impact of charge sharing effects becomes increasingly severe, with soft errors caused by single event effects becoming one of the main causes of circuit failures. Therefore, the study of sensitivity evaluation methods for integrated circuits is of great significance for promoting the optimization of integrated circuit design, improving single event effect experimental methods, and enhancing the irradiation reliability of integrated circuits. In this paper, we first established a device model for the charge sharing effect and simulated it under reasonable conditions. Based on the simulation results, we then built a neural network model to predict the charge amounts in primary and secondary devices. We also propose a comprehensive automated method for calculating soft errors in unit circuits and validated it through TCAD simulations, achieving an error margin of 2.8–4.3%. This demonstrated the accuracy and effectiveness of the method we propose. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
- View/download PDF
25. 2nd International Workshop on Networked Immersive Audio: Call for Papers.
- Subjects
INTEGRATED circuits ,NOISE ,SEMINARS ,COOPERATION ,COMPUTER software - Abstract
Copyright of VDT Magazin is the property of Fortes Medien GmbH and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
- Published
- 2024
26. Corrigendum to "Microfluidic colorimetric detection platform with sliding hybrid PMMA/paper microchip for human urine and blood sample analysis" [Talanta 231 (2021) 122362].
- Author
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Laurenciano, Carl Jay D., Tseng, Chin-Chung, Chen, Szu-Jui, Lu, Song-Yu, Tayo, Lemmuel L., and Fu, Lung-Ming
- Subjects
- *
BLOOD testing , *BLOOD sampling , *INTEGRATED circuits , *HUMAN beings - Published
- 2021
- Full Text
- View/download PDF
27. Supply Of Electronic Components, Voltage Regulator, Full Bridge Fet Driver, Buck Regulator, Dual D-type Flip-flop, Precision Current Limit Buck Regulator, Power Mosfet, Digital To Analog Converter, 32-kbit Serial I2c Bus Eeprom , Ic , Smd Type , Plastic M
- Subjects
Paper mills ,Metal oxide semiconductor field effect transistors ,Integrated circuits ,Circuit components ,Semiconductor chips ,Standard IC ,Semiconductor device ,Business, international - Abstract
Tenders are invited for Supply of Electronic Components, Voltage Regulator, Full Bridge FET Driver, Buck Regulator, Dual D-type flip-flop, Precision Current Limit Buck Regulator, Power MOSFET, Digital to Analog converter, [...]
- Published
- 2023
28. HIGH SPEED LOW POWER ANALYSIS OF 12 TRANSISTORS 2x4 LINE DECODER USING 45GPDK TECHNOLOGY.
- Author
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JAVVADI, SRUTHI PAVANI, HANUMAN, C. R. S., PARASA, SIVADURGARAO, and NARAGANENI, SANNAJAJI
- Subjects
LOGIC design ,GENERIC products ,PRODUCT design ,TRANSISTORS ,INTEGRATED circuits - Abstract
This paper proposes the high speed low power analysis of 12 transistors 2x4 Low Power (LP) and Low Power Inverting (LPI) Decoders by using Dual Value Logic (DVL) and Complementary Metal Oxide Semiconductor (CMOS) Logic. A huge challenge faced by this era of developing is power reduction. The LP circuit design is a requesting issue in high performance digital frameworks, for example, microchips, DSPs and other different applications. Power and speed are the main highlights considered while comparing any design. Diminishing chip area is additionally truly impressive factor, designers need to recall when suggesting any novel design. 2x4 LP and LPI Decoders using 12T (Transistor) is used for conversion of binary inputs to associated output bits in a pattern. A novel design (CMOS logic and DVL logic) of 2x4 LP and LPI Decoders using 12T is proposed with area optimization, LP and high speed in this paper. Delay and power is evaluated between the novel design and CMOS logic. The novel design of 12T LP and LPI 2x4 Decoders is 60.72% optimized for power in contrast to CMOS logic design at a typical value of 1.8V. The proposed method has been validated using Cadence 45 GPDK (Generic Product Design Key) Virtuoso Tool. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
- View/download PDF
29. A High-Quality and Space-Efficient Design for Memristor Emulation.
- Author
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Kumar, Atul and Chaturvedi, Bhartendu
- Subjects
ANALOG circuits ,INTEGRATED circuits ,MEMRISTORS ,LOW voltage systems ,CAPACITORS - Abstract
The paper presents a new design for a compact memristor emulator that uses a single active component and a grounded capacitor. This design incorporates a current backward transconductance amplifier as the active element, enabling the emulation of both grounded and floating memristors in incremental and decremental modes. The paper provides an in-depth analysis of the circuit, covering ideal, non-ideal, and parasitic factors. The theoretical performance of the memristor emulator is confirmed through post-layout simulations with 180 nm generic process design kit (gpdk) technology, demonstrating its capability to operate at low voltages (±1 V) with minimal power consumption. Additionally, the emulator shows strong performance under variations in process, voltage, and temperature (PVT) and functions effectively at a frequency of 2 MHz. Experimental validation using commercially available integrated circuits further supports the proposed design. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
- View/download PDF
30. The Analysis and Research of the Integrated, 30 A MOSFET Gate Driver Dedicated to High-Frequency Applications.
- Author
-
Legutko, Piotr
- Subjects
INTEGRATED circuits ,BUSINESS losses ,TRANSISTORS ,VOLTAGE - Abstract
This paper presents basic properties and laboratory tests of a commercial integrated high-frequency MOSFET gate driver IXRFD631 operating in the frequency range up to 30 MHz. The MOSFET driver has been tested for two operating states: in the idle state (no load) and at the gate load of a DE275-501N16A series MOSFET transistors. The obtained laboratory results were compared with three other commercial integrated drivers: DEIC420, DEIC515 and IXRFD630 (which are the base structures), and two previous solutions from the author (4xUCC27516 and 8xUCC27526). Additionally, this paper presents the characteristics of power losses and efficiency, measurements of switching and propagation times of the tested gate drivers. Also, this paper presents the output voltage waveforms of the integrated driver IXRFD631 for two operating states. The integrated circuit IXRFD631 of the gate driver is characterized by an efficiency of up to 70% for the tested frequency range, the power losses for two operating states (at idle state—15 W, at gate MOSFET load—43 W) and switching times of 2 ns for an operating frequency of 30 MHz. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
- View/download PDF
31. Technique of High-Field Electron Injection for Wafer-Level Testing of Gate Dielectrics of MIS Devices.
- Author
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Andreev, Dmitrii V., Andreev, Vladimir V., Konuhova, Marina, and Popov, Anatoli I.
- Subjects
DIELECTRIC devices ,DIELECTRIC breakdown ,INTEGRATED circuits ,PERMITTIVITY ,MANUFACTURING processes - Abstract
We propose a technique for the wafer-level testing of the gate dielectrics of metal–insulator–semiconductor (MIS) devices by the high-field injection of electrons into the dielectric using a mode of increasing injection current density up to a set level. This method provides the capability to control a change in the charge state of the gate dielectric during all the testing. The proposed technique makes it possible to assess the integrity of the thin dielectric and at the same time to control the charge effects of its degradation. The method in particular can be used for manufacturing processes to control integrated circuits (ICs) based on MIS structures. In the paper, we propose an advanced algorithm of the Bounded J-Ramp testing of the gate dielectric and receive its approval when monitoring the quality of the gate dielectrics of production-manufactured MIS devices. We found that the maximum value of positive charge obtained when tested by the proposed method was a value close to that obtained when the charge was injected into the dielectric under a constant current with a Bounded J value despite large differences in the rate of degradation of the dielectric. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
- View/download PDF
32. LC Tank Oscillator Based on New Negative Resistor in FDSOI Technology.
- Author
-
Mao, Yuqing, Charlon, Yoann, Leduc, Yves, and Jacquemod, Gilles
- Subjects
MOORE'S law ,ELECTRIC oscillators ,ANALOG circuits ,INTEGRATED circuits ,TRANSISTORS - Abstract
Although Moore's Law reaches its limits, it has never applied to analog and RF circuits. For example, due to the short channel effect (SCE), drain-induced barrier lowering (DIBL), and sub-threshold slope (SS)..., longer transistors are required to implement analog cells. From 22 nm CMOS technology and beyond, for reasons of variability, the channel of the transistors has no longer been doped. Two technologies then emerged: FinFET transistors for digital applications and UTBB FDSOI transistors, suitable for analog and mixed applications. In a previous paper, a new topology was proposed utilizing some advantages of the FDSOI technology. Thanks to this technology, a novel cross-coupled back-gate (BG) technique was implemented to improve analog and mixed signal cells in order to reduce the surface of the integrated circuit. This technique was applied to a current mirror to reduce the small channel effect and to provide high-output impedance. It was demonstrated that it is possible to overcompensate the SCE and DIBL effects and to create a negative output resistor. This paper presents a new LC tank oscillator based on this current mirror functioning as a negative resistor. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
- View/download PDF
33. Design, Fabrication, and Characterization of a PTAT Sensor Using CMOS Technology.
- Author
-
Szermer, Michał, Jankowski, Mariusz, and Janicki, Marcin
- Subjects
LINE drivers (Integrated circuits) ,TEMPERATURE sensors ,DETECTOR circuits ,INTEGRATED circuits ,DETECTORS - Abstract
This paper presents the design of an integrated temperature sensor. The sensor was manufactured using the 3 µm CMOS technology. The proportional to absolute temperature sensor output signal was produced by two MOS transistors with biasing and buffering circuits. The sensor output voltage was linearly proportional to the absolute temperature in a wide range of temperature values. The measurement results coincide very well with the results of the process corner analysis. Certain non-linearities occurring at high temperature values are investigated in this paper in more detail. Additionally, the influence of neighboring circuits present in the manufactured integrated circuit on the sensor temperature response is studied. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
- View/download PDF
34. Tersus GNSS Releases ExtremeRTK White Paper.
- Subjects
PROFESSIONS ,INTEGRATED circuits - Abstract
The article offers suggestions for the white paper on ExtremeRTK Technology from Tersus.
- Published
- 2022
35. Reliability Study of Metal-Oxide Semiconductors in Integrated Circuits.
- Author
-
Malozyomov, Boris V., Martyushev, Nikita V., Bryukhanova, Natalia Nikolaevna, Kondratiev, Viktor V., Kononenko, Roman V., Pavlov, Pavel P., Romanova, Victoria V., and Karlina, Yuliya I.
- Subjects
INTEGRATED circuits ,ACTIVATION energy ,LITERATURE reviews ,SEMICONDUCTORS ,SEMICONDUCTOR devices ,RELIABILITY in engineering - Abstract
This paper is devoted to the study of CMOS IC parameter degradation during reliability testing. The paper presents a review of literature data on the issue of the reliability of semiconductor devices and integrated circuits and the types of failures leading to the degradation of IC parameters. It describes the tests carried out on the reliability of controlled parameters of integrated circuit TPS54332, such as quiescent current, quiescent current in standby mode, resistance of the open key, and instability of the set output voltage in the whole range of input voltages and in the whole range of load currents. The calculated values of activation energies and acceleration coefficients for different test temperature regimes are given. As a result of the work done, sample rejection tests have been carried out on the TPS54332 IC under study. Experimental fail-safe tests were carried out, with subsequent analysis of the chip samples by the controlled parameter quiescent current. On the basis of the obtained experimental values, the values of activation energy and acceleration coefficient at different temperature regimes were calculated. The dependencies of activation energy and acceleration coefficient on temperature were plotted, which show that activation energy linearly increases with increasing temperature, while the acceleration coefficient, on the contrary, decreases. It was also found that the value of the calculated activation energy of the chip is 0.1 eV less than the standard value of the activation energy. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
- View/download PDF
36. Compact Low Loss Ribbed Asymmetric Multimode Interference Power Splitter.
- Author
-
Liang, Yanfeng, Lv, Huanlin, Liu, Baichao, Wang, Haoyu, Liu, Fangxu, Liu, Shuo, Cong, Yang, Li, Xuanchen, and Guo, Qingxiao
- Subjects
FINITE difference method ,INTEGRATED circuits - Abstract
Optical power splitters (OPSs) are utilized extensively in integrated photonic circuits, drawing significant interest in research on power splitters with adjustable splitting ratios. This paper introduces a compact, low-loss 1 × 2 asymmetric multimode interferometric (MMI) optical power splitter on a silicon-on-insulator (SOI) platform. The device is simulated using the finite difference method (FDM) and eigenmode expansion solver (EME). It is possible to attain various output power splitting ratios by making the geometry of the MMI central section asymmetric relative to the propagation axis. Six distinct optical power splitters are designed with unconventional splitting ratios in this paper, which substantiates that the device can achieve any power splitter ratios (PSRs) in the range of 95:5 to 50:50. The dimensions of the multimode section were established at 2.9 × (9.5–10.9) μm. Simulation results show a range of unique advantages of the device, including a low extra loss of less than 0.4 dB, good fabrication tolerance, and power splitting ratio fluctuation below 3% across the 1500 nm to 1600 nm wavelength span. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
- View/download PDF
37. Design, preparation, and characterization of a novel ZnO/CuO/Al energetic diode with dual functionality: Logic and destruction.
- Author
-
Jialu Yang, Jiaheng Hu, Yinghua Ye, Jianbing Xu, Yan Hu, and Ruiqi Shen
- Subjects
ZINC oxide ,INTEGRATED circuits ,SEMICONDUCTOR characterization ,ELECTROCHEMICAL analysis ,DATA analysis - Abstract
Self-destructing chips have promising applications for securing data. This paper proposes a new concept of energetic diodes for the first time, which can be used for self-destructive chips. A simple two-step electrochemical deposition method is used to prepare ZnO/CuO/Al energetic diode, in which N-type ZnO and P-type CuO are constricted to a PN junction. This paper comprehensively discusses the material properties, morphology, semiconductor characteristics, and exploding performances of the energetic diode. Experimental results show that the energetic diode has typical rectification with a turn-on voltage of about 1.78 V and a reverse leakage current of about 3 x 10
-4 A. When a constant voltage of 70 V loads to the energetic diode in the forward direction for about 0.14 s or 55 V loads in the reverse direction for about 0.17 s, the loaded power can excite the energetic diode exploding and the current rises to about 100 A. Due to the unique performance of the energetic diode, it has a double function of rectification and explosion. The energetic diode can be used as a logic element in the normal chip to complete the regular operation, and it can release energy to destroy the chip accurately. [ABSTRACT FROM AUTHOR]- Published
- 2024
- Full Text
- View/download PDF
38. A Deep Reinforcement Learning Floorplanning Algorithm Based on Sequence Pairs †.
- Author
-
Yu, Shenglu, Du, Shimin, and Yang, Chang
- Subjects
DEEP reinforcement learning ,MACHINE learning ,REINFORCEMENT learning ,BASE pairs ,INTEGRATED circuits ,SEQUENCE spaces - Abstract
In integrated circuit (IC) design, floorplanning is an important stage in obtaining the floorplan of the circuit to be designed. Floorplanning determines the performance, size, yield, and reliability of very large-scale integration circuit (VLSI) ICs. The results obtained in this step are necessary for the subsequent continuous processes of chip design. From a computational perspective, VLSI floorplanning is an NP-hard problem, making it difficult to be efficiently solved by classical optimization techniques. In this paper, we propose a deep reinforcement learning floorplanning algorithm based on sequence pairs (SP) to address the placement problem. Reinforcement learning utilizes an agent to explore the search space in sequence pairs to find the optimal solution. Experimental results on the international standard test circuit benchmarks, MCNC and GSRC, demonstrate that the proposed deep reinforcement learning floorplanning algorithm based on sequence pairs can produce a superior solution. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
- View/download PDF
39. A Fast Simulation Method for Evaluating the Single-Event Effect in Aerospace Integrated Circuits.
- Author
-
Zhang, Xiaorui, Liu, Yi, Xu, Changqing, Liao, Xinfang, Chen, Dongdong, and Yang, Yintang
- Subjects
INTEGRATED circuits ,COMPUTER simulation ,SIMULATION methods & models ,PROBLEM solving - Abstract
With the continuous progress in integrated circuit technology, single-event effect (SEE) has become a key factor affecting the reliability of aerospace integrated circuits. Simulating fault injection using the computer simulation technique effectively reflects the SEE in aerospace integrated circuits. Due to various masking effects, only a small number of faults will result in errors; the traditional method of injecting one fault in one workload execution is inefficient. The method of injecting multiple faults in one workload execution will make it impossible to judge which fault results in errors because the propagation characteristic of SEE and faults may affect each other. This paper proposes an improved multi-point fault injection method to improve simulation efficiency and solve the problems of the general multi-point fault injection method. If one workload execution does not result in errors, multiple faults can be verified by one workload execution. If one workload execution results in errors, a specific grouping method can be used to determine which faults result in errors. The experimental results show that the proposed method achieves a good acceleration effect and significantly improves the simulation efficiency. [ABSTRACT FROM AUTHOR]
- Published
- 2023
- Full Text
- View/download PDF
40. Government support, talent, coupling of innovation chain and capital chain: empirical analysis in integrated circuit enterprises.
- Author
-
Chen, Qiuling and Wang, Tianchi
- Subjects
GOVERNMENT aid ,INTEGRATED circuits ,INTELLECTUAL capital ,GOVERNMENT business enterprises ,INCENTIVE (Psychology) ,MOMENTS method (Statistics) - Abstract
Purpose: This study aims to investigate the impact of government support on the coupling coordination degree of innovation chain and capital chain in integrated circuit (IC) enterprises and to explore the mechanism for considering talent in the influence path. Design/methodology/approach: This paper uses coupling coordination degree model to estimate the coupling of two chains, and applies dynamic panel system generalized method of moments (system-GMM) to analyze the impact of government support on coupling of two chains and conducts dynamic panel threshold regression to explore the threshold effect of talent in the influence of government support on coupling coordination degree. Findings: Serious imbalance in the coupling of two chains is a major obstacle in IC enterprises. Government support significantly reduces the coupling coordination degree. The talent in IC enterprises has a significant threshold effect. When the number of talent is lower than the threshold value, government support has a negative impact. Once the number of talent reaches a certain level, government support can significantly enhance the coupling of two chains. Compared with state-owned enterprises, government support has a greater negative impact on the coupling of the two chains in non-state-owned enterprises. The former needs more talent to take advantage of government support. Originality/value: This paper applies the concept of coupling into enterprises and deeply studies the coupling coordination degree of two chains. The influence mechanism of government support and talent on the coupling of two chains is explored, which reveals that government support cannot achieve the expected incentive effect without the support of talent. We also discuss the heterogeneous effect of government support and of talent in enterprises of different ownership types. [ABSTRACT FROM AUTHOR]
- Published
- 2023
- Full Text
- View/download PDF
41. Failure to Deliver.
- Author
-
GOODMAN, PETER S.
- Subjects
- *
INTEGRATED circuits , *VIRAL transmission , *COVID-19 pandemic , *TOILET paper , *STAY-at-home orders - Abstract
The article discusses how the COVID-19 pandemic exposed vulnerabilities in the global supply chain, which had become heavily reliant on just-in-time shipping and manufacturing in China to cut costs. It traces the roots of these issues back to decades earlier when Western businesses increasingly turned to China for manufacturing and market opportunities, illustrating the precarious nature of global trade systems.
- Published
- 2024
42. Artificial Intelligence: Evolution, Developments, Applications, and Future Scope.
- Author
-
Raj, Ravi and Kos, Andrzej
- Subjects
ARTIFICIAL intelligence ,INTEGRATED circuits ,LANDSCAPE changes ,HUMAN beings - Abstract
Copyright of Przegląd Elektrotechniczny is the property of Przeglad Elektrotechniczny and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
- Published
- 2023
- Full Text
- View/download PDF
43. A modeling method of algorithm-hardware based on SysML.
- Author
-
Yue, Liu, Chun, Zhao, and Lin, Zhang
- Subjects
RANDOM numbers ,SYSTEMS engineering ,ENGINEERING systems ,INTEGRATED circuits ,SIMULATION methods & models - Abstract
In the process of complex product design, modeling in different fields and different disciplines is often involved. Designers often face many different development kits, platforms, and theories, among which significant differences exist. Especially in the process of algorithm-hardware implementation, it is necessary to have mastery of the knowledge including algorithm, hardware, circuit, and system engineering. In this paper, a modeling method of algorithm-hardware based on SysML is proposed to reduce the difficulty of algorithm-hardware modeling. By using the method, the designers who do not know the knowledge of hardware can also easily build the algorithm-hardware model. In this method, a method of graphical system modeling based on SysML is used, where the elements of the algorithm-hardware model are described by SysML graphical models. Then, the SysML graphical models are converted to Very-High-Speed Integrated Circuit Hardware Description Language. At last, a detecting algorithm of random number is complemented by the modeling method in this paper and the simulation results are presented at the conclusion. [ABSTRACT FROM AUTHOR]
- Published
- 2022
- Full Text
- View/download PDF
44. Monolithic three‐dimensional integration of aligned carbon nanotube transistors for high‐performance integrated circuits.
- Author
-
Fan, Chenwei, Cheng, Xiaohan, Xu, Lin, Zhu, Maguang, Ding, Sujuan, Jin, Chuanhong, Xie, Yunong, Peng, Lian‐Mao, and Zhang, Zhiyong
- Subjects
INTEGRATED circuits ,TRANSISTORS ,FIELD-effect transistors ,FUNCTIONAL integration ,CHARGE carrier mobility ,CARBON nanotubes - Abstract
Carbon nanotube field‐effect transistors (CNT FETs) have been demonstrated to exhibit high performance only through low‐temperature fabrication process and require a low thermal budget to construct monolithic three‐dimensional (M3D) integrated circuits (ICs), which have been considered a promising technology to meet the demands of high‐bandwidth computing and fully functional integration. However, the lack of high‐quality CNT materials at the upper layer and a low‐parasitic interlayer dielectric (ILD) makes the reported M3D CNT FETs and ICs unable to provide the predicted high performance. In this work, we demonstrate a multilayer stackable process for M3D integration of high‐performance aligned carbon nanotube (A‐CNT) transistors and ICs. A low‐κ (~3) interlayer SiO2 layer is prepared from spin‐on‐glass (SOG) through processes with a highest temperature of 220°C, presenting low parasitic capacitance between two transistor layers and excellent planarization to offer an ideal surface for the A‐CNT and device fabrication process. A high‐quality A‐CNT film with a carrier mobility of 650 cm2 V–1 s–1 is prepared on the ILD layer through a clean transfer process, enabling the upper CNT FETs fabricated with a low‐temperature process to exhibit high on‐state current (1 mA μm–1) and peak transconductance (0.98 mS μm–1). The bottom A‐CNT FETs maintain pristine high performance after undergoing the ILD growth and upper FET fabrication. As a result, 5‐stage ring oscillators utilizing the M3D architecture show a gate propagation delay of 17 ps and an active region of approximately 100 μm2, representing the fastest and the most compact M3D ICs to date. [ABSTRACT FROM AUTHOR]
- Published
- 2023
- Full Text
- View/download PDF
45. A Study of Advancing Ultralow-Power 3D Integrated Circuits with TEI-LP Technology and AI-Enhanced PID Autotuning.
- Author
-
Jeon, Sangmin, Kwak, Hyunseok, and Lee, Woojoo
- Subjects
INTEGRATED circuits ,TEMPERATURE inversions ,TEMPERATURE effect ,SEMICONDUCTOR industry ,HIGH temperatures - Abstract
The 3D integrated circuit (3D-IC) is garnering significant attention from academia and industry as a key technology leading the post-Moore era, offering new levels of efficiency, power, performance, and form-factor advantages to the semiconductor industry. However, thermal management in 3D-ICs presents a critical challenge that must be overcome to ensure prosperity for this technology. Unlike traditional thermal management solutions that perceive heat generation in 3D-ICs negatively and aim to eliminate it, this paper proposes, for the first time, a thermal management method that positively utilizes heat to achieve low-power operation in 3D-ICs. This approach is based on a novel discovery that circuits can reduce power consumption at higher temperatures by leveraging the temperature effect inversion (TEI) phenomenon in ultralow-voltage (ULV) operating circuits, a characteristic of low-power techniques (TEI-LP techniques). Along with a detailed explanation of this discovery, this paper introduces new thermal management technologies for practical application in 3D-ICs. Furthermore, to achieve optimal energy efficiency with the proposed technology, we develop a temperature controller essential for this purpose. The developed controller is a deep learning-based PID autotuner. This paper proves the theoretical validity of the AI control algorithm designed for this purpose and demonstrates the functional correctness and power-saving effectiveness of the developed controller through intensively conducted simulations. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
- View/download PDF
46. Simultaneous analysis of gadolinium and surface imaging using a fiber-coupled acoustic wave-assisted microchip LIBS system.
- Author
-
Batsaikhan, Munkhbat, Ohba, Hironori, Karino, Takahiro, Akaoka, Katsuaki, and Wakaida, Ikuo
- Subjects
LASER-induced breakdown spectroscopy ,INTEGRATED circuits ,SURFACE analysis ,SOUND waves ,ACOUSTIC imaging ,NUCLEAR power plants ,MOLECULAR spectra - Abstract
This paper reports a pioneering attempt at simultaneously analyzing gadolinium (Gd) distribution and surface imaging of surrogate debris samples with homogeneous and heterogeneous composition using a fiber-coupled acoustic wave-assisted microchip laser-induced breakdown spectroscopy (AW-mLIBS) system. This system must be applied to the remote analysis of fuel debris at the Fukushima Daiichi Nuclear Power Station (FDNPS). In the AW-mLIBS system, a microchip LIBS was used to measure the Gd distribution maps in the mixed oxide samples. Whereas, during elemental mapping by microchip LIBS, the laser-plasma acoustic waves were simultaneously recorded by microphone and applied for surface imaging of the samples. Additionally, the laser-plasma acoustic waves can be used to adjust the best-focusing position of the microchip LIBS because the acoustic wave amplitude is the strongest at the near best-focusing position. According to the measurement results, the emission spectra of the surrogate debris showed that the optical emission lines at 501.5 nm and 510.3 nm were suitable for Gd detection in the fuel debris sample. For Gd quantification, calibration curves were established from the intensity ratio of Gd/Ce emission lines, yielding the detection limits for Gd in the range of 0.04–0.09 wt% with a relative standard deviation of 3.9%. The surface imaging for the surrogate debris samples was successfully performed by collecting the laser-plasma acoustic waveforms during LIBS elemental mapping. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
- View/download PDF
47. High-performance cation electrokinetic concentrator based on a γ-CD/QCS/PVA composite and microchip for evaluating the activity of P-glycoprotein without any interference from serum albumin.
- Author
-
Zhang, Runhui, Xu, Jun, Deng, Jieqi, Ouyang, Wei, Chen, Hanren, Tang, Qing, Zheng, Shiquan, and Liu, Lihong
- Subjects
SERUM albumin ,POLYVINYL alcohol ,P-glycoprotein ,CARRIER proteins ,INTEGRATED circuits ,ANIMAL sacrifice ,ANIMAL experimentation ,ALBUMINS - Abstract
The development of cation electrokinetic concentrators (CECs) has been hindered by the lack of commercial anion-exchange membranes (AEMs). This paper introduces a γ-cyclodextrin-modified quaternized chitosan/polyvinyl alcohol (γ-CD/QCS/PVA) composite as an AEM, which is combined with a microchip to fabricate a CEC. Remarkably, the CEC only concentrates cationic species, thereby overcoming the interference of the highly abundant, negatively charged serum albumin in the blood sample. P-Glycoprotein (P-gp) is recognized as an efflux transporter protein that influences the pharmacokinetics (PK) of various compounds. The CEC was used to evaluate the activity of P-gp by detecting the positively charged rhodamine 123 (Rho123 is a classical substrate of P-gp) with no interference from serum albumin in the serum sample. Using the CEC, the enrichment factor (EF) of Rho123 exceeded 10
5 -fold under DC voltage application. The minimal sample consumption of the CEC (<10 μL) enables reduction of animal sacrifice in animal experiments. Here, the CEC has been applied to evaluate the transport activity of P-gp in in vitro and in vivo experiments by detecting Rho123 in the presence of P-gp inhibitors or agonists. The results are in good agreement with those reported in previous reports. Therefore, the CEC presents a promising application potential, owing to its simple fabrication process, high sensitivity, minimal sample consumption, lack of interference from serum albumin and low cost. [ABSTRACT FROM AUTHOR]- Published
- 2024
- Full Text
- View/download PDF
48. Magnetic alignment technology for wafer bonding.
- Author
-
Ye, Lezhi, Song, Xuanjie, and Yue, Chang
- Subjects
SEALING (Technology) ,SEMICONDUCTOR wafer bonding ,SEMICONDUCTOR manufacturing ,SEMICONDUCTOR wafers ,SEMICONDUCTOR design ,INTEGRATED circuits - Abstract
Purpose: Wafer bonding is a key process for 3 D advanced packaging of integrated circuits. It requires very high accuracy for the wafer alignment. To solve the problems of large movement stroke, position calibration error and low production efficiency in optical alignment, this paper aims to propose a new wafer magnetic alignment technology (MAT) which is based on tunnel magneto resistance effect. MAT can realize micro distance alignment and reduces the design and manufacturing difficulty of wafer bonding equipment. Design/methodology/approach: The current methods and existing problems of wafer optical alignment are introduced, and the mechanism and realization process of wafer magnetic alignment are proposed. Micro magnetic column (MMC) marks are designed on the wafer by the semiconductor manufacturing process. The mathematical model of the space magnetic field of the MMC is established, and the magnetic field distribution of the MMC alignment is numerically simulated and visualized. The relationship between the alignment accuracy and the MMC diameter, MMC remanence, MMC thickness and sensor measurement height was studied. Findings: The simulation analysis shows that the overlapping double MMCs can align the wafer with accuracy within 1 µm and can control the bonding distance within the micrometer range to improve the alignment efficiency. Originality/value: Magnetic alignment technology provides a new idea for wafer bonding alignment, which is expected to improve the accuracy and efficiency of wafer bonding. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
- View/download PDF
49. Advances in Physical Unclonable Functions Based on New Technologies: A Comprehensive Review.
- Author
-
Cao, Yuan, Xu, Jianxiang, Wu, Jichun, Wu, Simeng, Huang, Zhao, and Zhang, Kaizhao
- Subjects
PHYSICAL mobility ,REVERSE engineering ,PRINTED electronics ,TECHNICAL literature ,INTEGRATED circuits - Abstract
A physical unclonable function (PUF) is a technology designed to safeguard sensitive information and ensure data security. PUFs generate unique responses for each challenge by leveraging random deviations in the physical microstructures of integrated circuits (ICs), making it incredibly difficult to replicate them. However, traditional silicon PUFs are now susceptible to various attacks, such as modeling attacks using conventional machine learning techniques and reverse engineering strategies. As a result, PUFs based on new materials or methods are being developed to enhance their security. However, in the realm of survey papers, it has come to our attention that there is a notable scarcity of comprehensive summaries and introductions concerning these emerging PUFs. To fill this gap, this article surveys PUFs based on novel technologies in the literature. In particular, we first provide an insightful overview of four types of PUFs that are rooted in advanced technologies: bionic optical PUF, biological PUF, PUF based on printed electronics (PE), and PUF based on memristors. Based on the overview, we further discuss the evaluation results of their performance based on specific metrics and conduct a comparative analysis of their performance. Despite significant progress in areas such as limited entry and regional expertise, it is worth noting that these PUFs still have room for improvement. Therefore, we have identified their potential shortcomings and areas that require further development. Moreover, we outline various applications of PUFs and propose our own future prospects for this technology. To sum up, this article contributes to the understanding of PUFs based on novel technologies by providing an in-depth analysis of their characteristics, performance evaluation, and potential improvements. It also sheds light on the wide range of applications for PUFs and presents enticing prospects for future advancements in this field. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
- View/download PDF
50. FPGA based telecommand system for balloon-borne scientific payloads.
- Author
-
Devarajan, Anand, Bangaru, Kapardhi, and Ojha, Devendra
- Subjects
COMPUTER hardware description languages ,FIELD programmable gate arrays ,INTEGRATED circuits - Abstract
Telecommand (TC) plays a crucial role in the success of high-altitude balloon experiments. Bose, Ray-Chaudhuri, Hocquenghem (BCH) codes are commonly employed to ensure reliable command operation. The Balloon Facility (BF) of Tata Institute of Fundamental Research (TIFR) uses a TC system based on BCH (31,16) coding technique, to control balloon and payload operations. This paper presents prototyping and implementation of TC encoder and decoder using Spartan 6 Field Programmable Gate Array (FPGA). The code is written in Very high-speed integrated circuit Hardware Description Language (VHDL). Simulation and synthesis are done using Xilinx ISE 14.7 design suite. Simulation results show the design is robust. The TC encoder is implemented in a commercial FPGA development board and the TC decoder is implemented in a specially designed FPGA board, successfully. This paper presents the salient features of the TC system in use and the implementation of the system using FPGA. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
- View/download PDF
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