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Physical attacks are a serious threat to the Internet of Things devices. Differential power analysis attacks are the most well-known physical attacks that exploit physical information leaked from hardware devices to retrieve secret information. Fault analysis attacks, a type of physical attack, are often considered more powerful than side-channel attacks if an attacker can inject the attacker’s intended faults. In fact, a few times of fault injections have enabled the attacker to retrieve the secret key. In this study, we propose a new model to validate the resistance of block ciphers to Differential Fault Analysis (DFA) attacks by assuming an ideal block cipher in which the differential probability is the same for all input and output differences. We show that Advanced Encryption Standard (AES) is near ideal for DFA attack resistance according to the experimental results.

Cryptographic techniques are necessary for the security of Adhoc Network. These cryptographic Algorithms are obligatory for protection of the user data so that only the permitted user are allowed to access it. This review paper outlines the comparison of various algorithms i.e AES, Rijndael AES and Pipelined AES. These algorithms estimate the performance on the basis of data throughput and clock frequency.

Nowadays, Wi-Fi is a very popular Technology. Faster data transfer and Security both are very important for Wi-Fi. At present, Advanced Encryption Standard (AES) is used for Wi-Fi that is more secured than other encryption algorithms but it is not so fast because of it's complex functions. On the other hand, Blowfish is a very faster encryption algorithm but it cannot apply on Wi-Fi because of it's security problems. In this paper, a hybrid algorithm of Blowfish and Rivest Cipher 6 (RC6) is proposed that solves the security problems of Blowfish and also maintains the fastness of Blowfish and makes it able to use it in place of AES. It uses two innovative criteria. One is ingenious confusion process using two random numbers "a" and "w" that removes reflectively weak key attack and Known plaintext attack of Blowfish. The other is usage of one S-Box by overlapping process that eliminates the collision key attack of Blowfish. Sub key generation process of this algorithm also removes the Brute Force attack of AES. This paper tries to give an efficient algorithm that enhances the performance of Blowfish algorithm by adding a function of RC6 with it. The adding process is trickily handed here that makes the proposed algorithm as fast as Blowfish and also secured like existing AES. The proposed algorithm takes less encryption –decryption time like Blowfish and also secured like AES. Throughput, Average time for different data lengths and attack removal process are used to measure the efficiency of this proposed algorithm.

On January 2, 1997, the National Institute of Standards and Technology in the US announced that they intend to initiate the development of a new world-wide encryption standard to replace the Data Encryption Standard (DES). A call for candidates was announced world-wide with the deadline of 15th June 1998. Totally, 15 candidates were submitted from the US, Canada, Europe, Asia and Australia. The author is the designer of one of the candidates, and a codesigner of another proposal.

This paper introduces an improved advanced encryption standard (AES) cipher algorithm by proposing a new algorithm based on magic square to decrease the AES execution time. This is done by replacing Mixcolumn function with magic square of order 6. This paper raises the security level of AES cryptosystem by using another key, which is generated using magic square while decreasing the execution time. For application of encrypting a colouring image, visual studio and MATLAB programs have been used as means for computing results. The results of complexity, time execution, National Institute of Standards and Technology (NIST) tests, histogram, differential attacks and peak signal to noise ratio (PSNR) are computed and compared with the original AES cryptosystem, the original and the proposed algorithms. The proposed algorithm results in reasonable findings under several evaluation metrics. For instance, the complexity of our proposed algorithm is higher than the basic AES while decreases the time execution. The experimental results show that the suggested algorithm provides an efficient and secure way for image encryption. The suggested algorithm leads to leverage the complexity of cipher process as well as to make the linear and differential cryptanalysis harder by pre-process the input image initial step of the proposed AES.

The dissemination of the COVID-19 viruses now extends the usage of video consultations to share perspectives and virtual medical consultations, save expenses and health procedures, track the success of care proposals with detail, consistency, and ease from moment to time. The research aims to study the secur-ity of video consultations. We will also present the advantages and disadvantages of video consultations and the complications of their implementation. This paper mainly proposes a practical, high-efficiency video encoding technique for the new video encoding technique (HEVC) used in video consultations. The technology offered uses the RC5 block encryption algorithm for encrypting the sensitive bits of HEVC with low complexity, short encoding times in real-time implementa-tions, format-compliant HEVC, and constant bitrate. In addition, this paper pre-sents experimental results comparing the proposed HEVC RC5-based selective encryption (SE) algorithm with the other algorithms used in various operating modes using the Advanced Encryption Standard (AES). Also, this paper provides the security analysis of the proposed HEVC RC5-based SE algorithm for video consultation, including;the correlation analysis between the ciphered video and the original one, the histogram of the ciphered video, and the cipher cycle analysis. The security analysis results ensured that the proposed HEVC RC5-based SE algorithm for video consultation is safe and stable.

This study focuses on challenges faced during optimization of the performance of multiple users under encrypted data storage. Traditional single storage instance schemes are much concerned about the application scenarios rather than data sensitivity. This paper provides an optimization function for analyzing the performance parameters of developed queueing system. On the other hand, simulation results are further examined in order to optimize the average waiting time, average queue length, and total number of data packets. In addition, deduplication check provides more storage by eliminating duplicate files, and the remaining files further get encrypted by two cryptographic algorithms, namely advanced encryption standard (AES) and Rivest–Shamir–Adleman (RSA), respectively. Moreover, this paper emphasises performance of data in terms of storage and security; on the same basis, its comparison and implementation has been done. At last, conclusion is given.

Now-a-days all documents are in a digital format as well as everyone need to maintain their data in electronic mode with the help of cloud servers. A cloud server provides lots of facilities to users such as remote data maintenance, huge data handling and so on. But in the case of security many cloud servers are providing probabilistic results alone. So, that a new cloud server data maintenance scheme is required to provide a high-level data security to the cloud system in an efficient manner. This paper introduces a new crypto-approach called Novel Hybrid Encryption Mode (NHEM), in which this algorithm integrates several latest approaches of crypto logics into it and provides a top-end security level to the cloud data. This NHEM is derived from the base factors of two cryptographic algorithms called Advanced Encryption Standard with 512-bit size of key frequency with Message Digest (MD5) algorithm. By using the integration of these two powerful approaches, a novel approach called NHEM is designed and it provides a huge support to preserve security on cloud medium. The cloud data needs to be protected from unwanted threats and intruders by means of raising an interruption attacks on server. The proposed approach of Novel Hybrid Encryption Mode concentrates more on access control logics and the crypto norms with respect to privacy measures. In this paper, the proposed scheme assures the data is too robust and no one can attack the data without proper credentials as well as the outcome proofs are clearly given on the resulting unit of this paper. The Advanced Encryption Standard algorithm is a well-known and powerful crypto scheme and the MD5 algorithm is also considered to be the unique unidirectional algorithm to provide security level in energetic manner. These two algorithms are combined together with the bit frequency of 512 to achieve the highest accuracy levels in data security over cloud environment as well as the resulting portion clearly illustrates that with proper graphical outcome.

Currently, embedded systems can be found everywhere in quotidian life. In the development of embedded systems, information security is one of the important factors. Encryption is an efficient technique to protect information against attacks. However, because of constraints, existing encryption functions are not compatible and do not agree with real-time applications in embedded systems. In this paper, an improved cryptographic approach with a high level of security and high speed is put forward. Our work uses an efficient version of a hybrid scheme comprising an Advanced Encryption Standard (AES) - Elliptic Curve Cryptography (ECC) for medical image encryption, which combines the benefits of the symmetric AES to speed-up data encryption and asymmetric ECC in order to secure the interchange of a symmetric session key. The contribution of this paper consists of the following two main points: First, we put forward an optimized ECC hardware architecture to respect the compromise between area, power dissipation, and speed. Thus, we primarily utilize only two multipliers to develop the Point Addition (PA) block and the Point Doubling (PD) block, which reduces time complexity. Then, a 32-bit multiplier and a 32-bit inverter architecture based on shifts and XORs are proposed to reduce power consumption and area occupancy. Second, for image encryption, we primarily propose to modify the AES by eliminating the mix-columns transformation and replacing it with a permutation based on the shifts of columns, which decreases time complexity while maintaining the Shannon diffusion and the confusion principle. Then, an adjustment of the rearrangement of the general structure is given to enhance the entropy value. The global cryptosystem is implemented using a co-design approach where the modified AES runs on the NIOS II processor, and the scalar ECC multiplication is designed as a hardware accelerator. The suggested cryptographic system spends much less execution time, which is a significant factor for being applied in practice. Security analysis is successfully performed, and our experiments prove that our proposed technique provides the basics of cryptography with more simplicity and correctness. In fact, the results of the evaluation prove the effectiveness, rapidity and high security of the suggested algorithm.

The generic approach toward SRAM based in-memory computations has been to activate multiple memory rows simultaneously and read out a logic function of the constituent rows. In general, these schemes introduce errors in computations due to their analog nature, limiting their usage to error-resilient applications such as machine learning. In contrast, in-memory bulk bit-wise Boolean computations are suitable not only for error-resilient applications, but also those that require accurate computations like encryption. Prior works have indeed accomplished such bit-wise computations, however, they require modifications to the normal SRAM read operations leading to degraded read-stability or lower sense-margin. In this paper, we propose interleaving the word-lines (i-SRAM) as the basic approach for embedding bit-wise computations in SRAM arrays. Further, our i-SRAM read operation is identical to the normal memory read operation without loss of read-robustness or sense-margin. Even at deeply scaled nodes, as long as normal SRAM read stability is ascertained, the presented proposal works equally well. As opposed to prior works, this is a key benefactor in allowing the proposal to be seamlessly integrated in state-of-the-art SRAM compilers. We propose different configurations of i-SRAM for 6T and 8T-bit-cells, with minimal area overhead. We further demonstrate upto $\sim 2 \times $ improvement in energy and $\sim 8 \times $ improvement in throughput for a binary neural network (BNN) and $\sim 3.5 \times $ improvement in energy and $\sim 3 \times $ improvement in throughput for AES encryption using the proposed i-SRAM in a modified von-Neuamnn machine.

The information security is one of the most important issues in the design of any communication network.One of the most common encryption algorithms is the Advanced Encryption Standard (AES).The main problem facing the AES algorithm is the high time consumption due to the large number of rounds used for performing the encryption operation. The more time the encryption system consumes to encrypt the data, the more chances the hackers have to break the system.This paper presents two effective algorithms that can be used to solve the mentioned problem and to achieve an effective processing time reduction using pipelined and parallel techniques to perform the encryption steps. These algorithms are based on using certain techniques to make the system able to encrypt many different states (the data will be encrypted) in the same time with no necessity to wait for the previous encryption operation to be completed. These two algorithms are very effective especially for big data size. This paper describes in detail the AES encryption system algorithm and a detailed explanation for the proposed algorithms. Moreover, the research shows the implementation of the three algorithms: the traditional, the pipelined, and the parallel algorithms, and finally a comparison between them.

Nowadays, secure speech communications have become a fundamental issue, due to the rapid development of digital communications and networking technologies. People want high security level during their communications, especially for military and business purpose. For instance, in order to operate properly and effective in a hostile environment is mandatory to have a secure military communication. The methods that are currently available for voice encryption include the use of cryptographic algorithms (which ensure secure data transmission and reception). However, taking into consideration the problem of the bandwidth of the communication channel (which appears frequently in military applications), it is important to identify encryption algorithms that ensure high throughput and low bit-rate speech compression methods. Various speech encryption methods have strict requirements such as power consumption, size, voltage supply, which are difficult to fulfil. A solution to meet these constraints is to perform optimization at all levels, starting from the algorithm design, continuing with the system and circuit structure and reaching also the design of the cell library. More exactly, these optimizations depend on the modification of the encryption algorithm selected for the applications (in order to reduce its computational complexity), the algorithm chosen, the arithmetic unit selected (fixed-point or floating-point), the mapping between the selected architecture and the cryptographic algorithm. This paper describes a comparison regarding the performance of various speech encryption algorithms implemented on Digital Signal Processor (DSP) platform. These algorithms are from different categories, such as: stream ciphers (Grain v1, Trivium, Mickey 2.0 and SOSEMANUK), block ciphers (Advanced Encryption Standard - AES and Data Encryption Standard - DES) and dedicated algorithms for voice encryption (Robust Secure Coder, scrambling encryption and encryption algorithm based on chaotic map and Blowfish). All the previously mentioned algorithms where implemented on Blackfin 537 (a fixed point DSP) and careful optimizations were performed to fulfil real time requirements. The goal of this paper was to evaluate all these algorithms to determine which one is the best suited for applications that require secure real time communications.

Imagine that, in order to avoid patent fees, licensing agreements, or export restrictions, someone permutes the plaintext bits, ciphertext bits, or key bits of a block cipher. All security properties of the block cipher would be preserved. There are many possible such permutations (e.g. 23116.32 for the Advanced Encryption Standard, AES-256). It might seem infeasible to detect this fraud, and even harder to determine the permutation matrices used. Instead of a block cipher, it could be the compression function of a cryptographic hash, or any other cryptographic function. This paper presents an algorithm whereby this fraud could be easily detected, by means of a SAT-Solver—a standard off-the-shelf software package that solves small-to-medium sized instances of the logical satisfiability problem. This paper also presents how this problem can be modeled in a system of polynomial equations (e.g. in the context of algebraic cryptanalysis). Moreover, this problem is related to the “isomorphism of polynomials” problem and that connection is explored at length.

The advancement of technology in recent times has posed a number of serious threats to the integrity of the systems, networks, and programs utilized in different fields such as Healthcare organizations. Such threats have compounded with the development of cybersecurity, a move which involves protecting the systems from imminent threats that materialize in the form of digital attacks. Inadvertently, cybersecurity has become an important aspect of digital protection from ill-intentioned people who exploit the vulnerability of systems. This paper addresses the impact of cybersecurity in healthcare organizations. While on it, the paper will also present the various types of security threats in the industry and utilizing AES (Advanced Encryption Standard) as a protective measure for health-based organizations.

As the amount of data is increasing rapidly, its storage and security issues also increase. Hadoop is currently a popular framework for big data storage and processing. Since, security is not a primary consideration in Hadoop when it was initially developed makes the data stored in Hadoop distributed file system (HDFS) vulnerable to attacks. For protecting these data, numerous encryption techniques has been developed. This paper analyses and presents a comparison on advanced encryption standard (AES), a symmetric cipher and Rivest-Shamir-Adleman (RSA), an asymmetric cipher cryptographic algorithms. Finally, this paper proposes a hybrid method that combines both RSA and AES technique to improve the performance of encryption-decryption on HDFS files and thereby increases the security of big data in Hadoop framework. The proposed technique is found to be feasible and is able to enhance the confidentiality of HDFS files stored in Hadoop framework and is also able to overcome the limitations when using the AES encryption technique alone.

In today’s era of communication, sharing of information is unavoidable. Analysis of security and reliability while communicating is essential. Information may get altered, copied and copyright can be infringed. Previously, digital watermarking and different encryption techniques like AES, DES, HASH and MAC were used as a primary security technique for information hiding. But, in all these methods, there are some vulnerabilities, because of which information may be hacked or changed while transmission. In addition to the security of the information, there should also be an error-free transmission of data. This review paper discusses various image encryption techniques which are using joint error correction and encryption methods. Based on the literature review, a novel method for joint encryption and encoding is suggested. Low-Density Parity-Check (LDPC) code, a highly recommended technique in 5G, is used for reliability. Chaotic sequence based on a logistic map is used for security. Proposed technique also uses the S-Box of AES algorithm for enhancing the security obtained by combining LDPC and Chaotic sequence. This paper aims to provide a general overview of image encryption techniques. Based on the study, a new system for joint encryption and encoding using LDPC, Chaotic map and AES S-Box is suggested.

Broadcasting applications such as video surveillance systems are using High Definition (HD) videos. The use of high-resolution videos increases significantly the data volume of video coding standards such as High-Efficiency Video Coding (HEVC) and Advanced Video Coding (AVC), which increases the challenge for storing, processing, encrypting, and transmitting these data over different communication channels. Video compression standards use state-of-the-art techniques to compress raw video sequences more efficiently, such techniques require high computational complexity and memory utilization. With the emergent of using HEVC and video surveillance systems, many security risks arise such as man-in-the-middle attacks, and unauthorized disclosure. Such risks can be mitigated by encrypting the traffic of HEVC. The most widely used encryption algorithm is the Advanced Encryption Standard (AES). Most of the computational complexity in AES hardware-implemented is due to S-box or sub-byte operation and that because it needs many resources and it is a non-linear structure. The proposed AES S-box ROM design considers the latest HEVC used for homeland security video surveillance systems. This paper presents different designs for VHDL efficient ROM implementation of AES S-box using IP core generator, ROM components, and using Functions, which are all supported by Xilinx. IP core generator has Block Memory Generator (BMG) component in its library. S-box IP core ROM is implemented using Single port block memory. The S-box lookup table has been used to fill the ROM using the .coe file format provided during the initialization of the IP core ROM. The width is set to 8-bit to address the 256 values while the depth is set to 8-bit which represents the data filed in the ROM. The whole design is synthesized using Xilinx ISE Design Suite 14.7 software, while Modelism (version10.4a) is used for the simulation process. The proposed IP core ROM design has shown better memory utilization compared to non-IP core ROM design, which is more suitable for memory-intensive applications. The proposed design is suitable for implementation using the FPGA ROM design. Hardware complexity, frequency, memory utilization, and delay are presented in this paper.

India accounts for the highest road accidents and traffic congestion globally. The necessity for a canny vehicle framework is of great importance. VANET, abbreviated as Vehicular ad hoc networks is a network created in an ad hoc manner where different vehicles can exchange useful information among each other with dedicated servers ensuring safe travel. Security in VANET has always been a challenge in implementing a real time intelligent transport system. VANET is a type of mobile ad-hoc, to give correspondences among close by vehicles and among vehicles and close by fixed hardware. Vehicular ad hoc networks are highly dynamic in nature and suffer from frequent path breakage due to the high velocity of the moving vehicle. Hence, there are many security challenges and different types of attacks that makes VANETs less secure. Therefore, providing secure dedicated short-range communication (DSRC) easefully with any loss of data or malicious nodes has been a major research area. The major concern being addressed in the paper is to provide secure communication and save lives in road accidents. The role of security is high and messages in DSRC send warning messages to other vehicles. If attackers change these messages, then accidents become a part of the network and users’ lives can be at risk. Different classes of attacks include monitoring attack, social attack, timing attack, application attack and network attack to name a few. Advanced encryption standard is a symmetric block encryption algorithm. There is no evidence to crack this algorithm till date. This paper will provide a detailed overview of VANET architecture, types of attacks on VANET, AES algorithm and its salient features and how this algorithm could be utilized to make intelligent transport systems secure.

With the gradual deepening of the informatization construction of Zhejiang Electric Power Trading Center, massive amounts of data have been accumulated, and it is imperative to build a big data analysis system for Zhejiang Electric Power Market. Zhejiang Electric Power Market Big Data Analysis System has data interaction with Zhejiang Electricity Trading System and Zhejiang Electricity Settlement System. In order to ensure the secure transmission of information between various systems, it is necessary to realize the controllability, confidentiality, availability, integrity and non-repudiation of information interaction. This paper proposes a new hybrid encryption method by combining AES encryption algorithm, RSA encryption algorithm and SHA256 encryption algorithm, and it is used in the information transmission of Zhejiang Electric Power Market Big Data Analysis System. It generates a specific hash value for the ciphertext to verify the integrity of the transmitted data by using SHA256 to generate a fixed-digit hash value. Through the program verification of the hybrid encryption method in this paper, it is proved that the usability, security and efficiency of this method can provide security for the information interaction of Zhejiang Electric Power Market Big Data Analysis System.

Power Analysis Attack (PAA) are a class of Side Channel Attacks (SCA) which is based on power consumption measurements whose major concern is the protection of secret data stored in cryptographic devices. This paper reports the advantages of Secure Double Rate Registers (SDRR) as a Register Transfer Level (RTL) countermeasure in order to increase the security of cryptographic devices against PAA. SDRR is exploited in AES 128 bit architecture, the random data in the entire clock cycle is evaluated by the combinational path. One of the main advantage is that our technique does not require duplication of combinational path to process the random data thereby limiting area overhead unlike previous RTL countermeasures. This work reported in this paper gives the comparative study between conventional advanced encryption standard (AES) algorithm with normal registers and AES algorithm with secure double rate registers (SDRR). This proposed system is implemented, simulated using Verilog HDL and synthesized by Xilinx tool.

The Internet of Things (IoT)services and application were increasing during the last years in several life fields causes need to provide a secure identifier for protecting sensing data passing between IoT sensors/devices and embedded-subsystem connected by networks. This paper was proposed an algorithm for helping in IoT communication security can used in different IOT entities used in unofficial industrial machine to machine (M2M) communications, smart energy-grids, home or buildings and other computing devices. This paper proposed a secure system using new proposed 4D chaotic system combined with the modified lightweight Advanced Encryption Standard (AES). The proposed 4-dimension (4D) chaos system Lyapunov was tested and pass for many initial periods and get a super chaos system (4 positive Lyapunov). Generated chaos keys (used JORN) were used in the lightweight AES and the Secure Hash Algorithm version 3 (SHA3-256). The Lightweight AES was design in case to reduce CPU computation cycles and complexity of AES. Results show that computation time for proposed system decreased (has 145% speedup more). The output of modified lightweight AES encryption System has the good statistical tests near to original AES that can avoid many attacks.

This paper presents a performance comparison of new authenticated encryption (AE) algorithms which are aimed at providing better security and resource efficiency compared to existing standards. Specifically, these algorithms improve the security of existing AE standards by providing a critical property termed nonce-misuse resistance. This paper addresses algorithm to architectural mappings of several candidates from the ongoing Competition for AE: Security, Applicability, and Robustness as well as a submission from the Crypto Forum Research Group. Implementations of the architectures on both field-programmable gate arrays and application-specific integrated circuits platforms are provided and compared with the architecture of a popular standard: Advanced Encryption Standard in Galois Counter mode (AES-GCM). Optimizations that are applicable to AE, in general, and nonce-misuse-resistant architectures, in particular, are presented. A hardware–software codesign approach to optimization is also discussed. The implementations via proposed optimizations demonstrate that new AE algorithms can provide comparable performance as standard AES-GCM while enhancing security and resource utilization for specific use-case scenarios.

To avoid delays arising from a need to decrypt a video prior to transcoding and then re-encrypt it afterwards, this paper assesses a selective encryption (SE) content protection scheme. The scheme is suited to both recent standardized codecs, namely H.264/Advanced Video Coding (AVC) and High Efficiency Video Coding (HEVC). Specifically, the paper outlines a joint crypto-transcoding scheme for secure transrating of a video bitstream. That is to say it generates new video bitrates, possibly as part of an HTTP Adaptive Streaming (HAS) content delivery network. The scheme will reduce the bitrate to one or more lower desired bit-rate without consuming time in the encryption/decryption process, which would be the case when full encryption is used. In addition, the decryption key no longer needs to be exposed at intermediate middleboxes, including when transrating is performed in a cloud datacenter. The effectiveness of the scheme is variously evaluated: by examination of the SE generated visual distortion; by the extent of computational and bitrate overheads; and by choice of cipher when encrypting the selected elements within the bitstream. Results indicate that there remains: a content; quantization level (after transrating of an encrypted video); and codec-type dependency to any distortion introduced. A further recommendation is that the Advanced Encryption Standard (AES) is preferred for SE to lightweight XOR encryption, despite it being taken up elsewhere as a real-time encryption method., Revision-3 Version of Multimedia Tools and Application (Springer)

Modern power analysis attacks (PAAs) and existing countermeasures pose unique challenges on the design of simultaneously secure, power efficient, and high-performance ICs. In a typical PAA, power information is collected with a monitoring circuit connected to the compromised device. The non-typical voltage variations induced on a power distribution network (PDN) by such a malicious probing are sensed with on-chip sensors and exploited in this paper for detecting PAAs in real-time using statistical analysis. A closed-form expression for the voltage variations caused by malicious probing is provided. Guidelines with respect to the PDN characteristics and number of sensors are proposed for securing power delivery. The PAA detection system is designed in a 45-nm standard CMOS process. Based on the simulation results, a PAA on an IBM benchmarked microprocessor is detected with the accuracy of 88% with 30 on-chip sensors. Power overhead of 0.34% and 14.3% is demonstrated in, respectively, the IBM microprocessor and a typical advanced encryption standard system. In a practical cryptographic device, security sensitive PDN regions can be identified, significantly reducing the number of the on-chip sensors.

Pseudorandom number generators (PRNGs) are important in cryptography and have been used in several security applications, such as authentication protocols, session keys, key distribution, and keystream for a one-time pad. Producing PRNGs is a critical issue because they should be uniform in distribution, unpredictable, and independent. Several PRNGs are available, but the problem lies in determining the one with the best performance. The performance of PRNGs is determined by passing a set of statistical tests' set by the National Institute of Standards and Technology (NIST). The NIST also recommends random number generation using advanced encryption standard and triple data encryption standard algorithms with the counter mode of operation. Furthermore, several block cipher algorithms (BCAs) and alternates that are present may produce strong PRNG than NIST recommendations. Therefore, in this paper, different BCAs are explored and implemented, and their results are analyzed and addressed. This paper may help in producing a strong key generation, which is deemed necessary for cryptographic authentication and other security applications.

Multimedia communication is revolutionizing all major spheres of human life. The advent of IoT and its applications in many fields like sensing, healthcare and industry, result exponential increase in multimedia data, that needs to be shared over insecure networks. IoT driven setups are however constrained in terms of resources as a result of their small size. From data security point of view a conventional algorithms cannot be used for data encryption on an IoT platform given the resource constraints. The work presented in this paper studies the performance of SIMON cryptographic algorithm and proposes a light-weight-cryptography algorithm based on SIMON for its possible use in an IoT driven setup. The focus is on speed enhancement benefitting from software prospective, making it different than common studies mostly reflecting hardware implementations. To achieve performance in practical prospective, the contribution looks into SIMON cipher’s characteristics considering utilizing it for internet of things (IoT) healthcare applications. The paper suggests further improvement to implement the original SIMON cryptography in order to reduce the encryption time and maintain the practical trade-off between security and performance. The proposed work has been compared to Advanced Encryption Standard (AES) and the original SIMON block cipher algorithms in terms of execution time, memory consumption. The results show that the proposed work is suitable for securing data in an IoT driven setup.

In the previous paper an approach devised with Inasu for Multiple Server Authentication RFC control in SAA protocol rules shows that Layer digital exchange can be used for major encryption and decryption. In this internet exchange module, POX controller is used in SDN with secret keys to build public key systems. AES works on design principle known as supplicant authorized system, which quickly handles applications and deployment. Comparing with Data Encryption Standard, AES has no usage of Feistel framework successfully because there are too many possible keys. This is the step of inserting the round key part of the expanded key into plain text controller POX. Block ciphers are usually created plain text messages and can be processed in POX round function. But first, in a critical expansion phase, the key is expanded to the called round key. In this paper each round function has three inputs (48, 56, and 128) function sign rate for first round function and round key. Different passwords have different cycles. DES has 48 rounds, AES128 has 10 rounds and AES256 has 14 rounds. The DES key expansion process extends a 56-bit input key into 256-bit round keys with the help of hilltop classification in POX controller executed in 802. 1X for 216 input secret keys thereby improving the accuracy, speed and time packet transfer of relevancy new flow development with SDN forward device. It supports multiple topologies and includes the kernel S02.1X topology.

Encryption is a major requirement in today’s world as it boosts the security of the data that everyone shares all over the Internet. Videos are the means of communication in several industries and can be private. Encrypting a video file to a text file using the AES encryption algorithm increases the security provided while sharing such content over the Internet. Currently, apps to encrypt text files and images exist for the Android OS, and this paper proposes the next step in that direction - an Android app for video encryption and decryption. The results obtained via the method proposed in this paper are nearly 10 times better than the existing results.

This paper involves identification of issues in existing data security algorithms so that a hybrid algorithm can be developed, which will be useful in quantum computing. It has been seen that, data security breaches are increasing, making cloud computing a vulnerable system for online data storage and processing. This paper involves discussion on researches conducted on the aspects of cloud and quantum computing and issues in existing data security techniques. Moreover, it has also been seen that the best cloud-based security framework AES is not going to work effectively with upcoming quantum computing scenario. Hence, it is necessary to keep on reiterating on ideas for enhancing data security features using hybrid algorithm.

We can easily observe that in the current era of communication, Computers, mobile phones, and the Internet are widely used mediums. In such an environment, information security is an important issue. The most common techniques used for information security are Cryptography and Steganography. Many research works have been done on image Steganography. These images have different kinds of formats like BMP, GIF, and PNG. Several compression methods are available which applied to the images having the format BMP, GIF, and PNG is comparatively less effective than the JPEG image. JPEG compression steganography method is complex to implement even then some algorithms have been developed for it. They provide single-level or two-level information securities. This paper presents a method in which is the combination of Cryptography and Steganography is used over android mobile phones. Here we are performing encryption two times on data to be hidden and then that encrypted data hidden both in text and image. We are using the Advanced Encryption Standard (AES) algorithm to hide text within a text, Discrete Cosine transform (DCT) for image steganography, and Data Encryption Standard (DES) for encryption of text. This paper gives the idea of three-level information security over the android environment.

Cryptography is an emerging topic that has gained momentum since data explosion. With the advent of data it has become more important to secure the data from external interference. Various algorithms has been deployed with a penultimate goal of securing data of which Advanced Encryption Standard (AES) is one. The paper provides a substantial modification over Advanced Encryption Standard, with the aim of security and easy implementation focusing on the Symmetric Key Cryptosystem and AES algorithm. The performance was compared using different parameters such as data block, block size, encryption/decryption speed, run-time, and compile time. The main reason for this experiment was to exploit the effectiveness of the newly modified AES over the actual AES using the real-life application. A new key implementation process, the right shift key technique, and the elimination of the Mix-Column process were introduced. This paper provides calculations based on the AES-128 bit version, but the proposed algorithm can work on other versions as well. The goal was to achieve fast execution time and less memory usage while keeping the security hard to breach. The result depicts that our method achieved 88% throughput and better net execution time. This is a substantial improvement in terms of efficiency from the traditional AES. Our implementation with detailed documentation is available at GitHub1.

The development and application of various Machine Learning algorithms demand high computing capabilities. As a result, field-programmable gate arrays (FPGAs) are being used as hardware accelerators, and more recently deployed in cloud servers by leading vendors to provide reconfigurable computing capabilities. Although such cloud-FPGA platform is bringing significant performance benefits, it also creates a unique attack surface where the hardware resources of an FPGA are shared by multiple users. Power attack targeting the power distribution network (PDN) is among the most threatening ones against multi-tenant FPGAs. In such attack, the malicious users leverage power plundering circuits to manipulate the PDN and cause a voltage drop, thus injecting timing faults to the victim applications. Besides, since most cloud-FPGAs are being used for computing-intensive tasks that consume a large amount of power, therefore, typical FPGA applications may still encounter timing faults even without power attacks. Unlike power attacks, we classify this problem as a reliability issue. To comprehensively mitigate the reliability and security issues caused by a non-malicious or malicious voltage drop, in this paper, we introduce a quantitative defense framework. The proposed framework provides a two-fold defense method: static and dynamic frequency scaling, to manage the clock frequency of the FPGA applications. The frequency scaling strategy is based on quantifying the relationship between the adversarial circuit and the voltage drop that can be injected. The proposed framework provides a delay-frequency pair table, which can be pre-configured to control the run-time clock frequency of the FPGA application. For practical applicability, the proposed framework utilizes the existing on-chip clock management components like mixed-model clock manager (MMCM) and phase-locked loop (PLL). Additionally, to assist the frequency scaling, we propose an on-chip sensor that can accurately quantify the real-time voltage drop. The performance of the proposed framework is validated with open-source benchmarks and real-world Advanced Encryption Standard (AES) implementation on an Xilinx NetFPGA. The experimental results demonstrate the effectiveness of the proposed method in mitigating security and reliability issues caused by a voltage drop. To comprehensively mitigate the reliability and security issues caused by a non-malicious or malicious voltage drop, in this paper, we introduce a quantitative defense framework. The proposed framework provides a two-fold defense method: static and dynamic frequency scaling, to manage the clock frequency of the FPGA applications. The frequency scaling strategy is based on quantifying the relationship between the adversarial circuit and the voltage drop that can be injected. The proposed framework provides a delay-frequency pair table, which can be pre-configured to control the run-time clock frequency of the FPGA application. For practical applicability, the proposed framework utilizes the existing on-chip clock management components like mixed-model clock manager (MMCM) and phase-locked loop (PLL). Additionally, to assist the frequency scaling, we propose an on-chip sensor that can accurately quantify the real-time voltage drop. The performance of the proposed framework is validated with open-source benchmarks and real-world Advanced Encryption Standard (AES) implementation on an Xilinx NetFPGA. The experimental results demonstrate the effectiveness of the proposed method in mitigating security and reliability issues caused by a voltage drop.

In the current times, there is extensive use of the global network throughout communities as a consequence of which, users have become vulnerable to growing attacks of browsers. The existing world calls for ensuring self-security and protection of surroundings, chiefly when it comes to the online realm, inside which hiding data has become a rampant occurrence, starting a field of investigation that covers requests including copyright protection rules for digital media technology, watermarking, fingerprinting, iris and steganography. In its root, cryptography technique was first established as a system to secure secret e-mail, with several various approaches developed for the purpose of data encrypt and decrypt for secret emails. Steganography basically refers to an art and science of invisible communication. In this paper, the author proposed two new encryption types that contribute to technology security and accuracy. Thus, this paper proposed a new intended the methods to be user-friendly, easy to handle, while at the same time improve the security. Consequently, the study of this paper is aims to develop a new type of two encryption were used namely Advanced Encryption Standard (AES) and Least Significant Bit (LSB) and identifies the needs of optimum steganographic algorithm and represents the steganographic methods that are suitable for specific applications.

Cryptography has an important role in securing information which has gained prominence due to the digitization. Exchange of sensitive personal data such as medical information tends to take place frequently throughout the globe; therefore, protecting data from unauthorized adversary access is imperative. Advanced encryption standard (AES) algorithm is one of the algorithms which is broadly employed because of its exemplary security and usage in extensive applications. This research proposes a modified folded pipelined architecture of an AES algorithm for resources constraint applications. The folding transformation controls the circuit functionalities by time-multiplexing operations to a single functional unit and reduces its area considerably. The proposed architecture is implemented using fewer resources, hence, improves area and the power requirements as compared to the conventional algorithm. The work presented in this paper is applicable for encrypting and decrypting personalized Electrocardiograph (ECG) signals for secure transmission. The architecture proposed in this paper reduces the area requirements by 83% and power by 96.8% enabling its hardware implementation more efficient than the conventional AES. Due to its low power and area requirements, the architecture presented in this paper can be used for portable Internet of things (IoT) applications as well.

In recent times Cloud Computing[CC] has emanated as a substitute paradigm for hosting and providing services over the Internet. Software as a Service (Saas) is one among such services that deliver services to the end-users on pay-as-you-go manner. In spite of all its advantages, security always seems to be major drawback. For securing the users' data on the cloud, this paper proposes an application model for any SaaS application hosted on a private cloud environment. The application is divided into two micro-services, where the first one is Application Layer Firewall and second one is a secured application to login and send sensitive data. The application layer firewall checks for any malicious activity and prevents the intruder to access the features present in the application. Subsequently, a Hidden Markov Model layer is implemented which is a probability-based intrusion detection technique. The second micro-service uses Advanced Encryption Standard (AES) encryption algorithm to encrypt documents having sensitive data, which have to be transferred within the private cloud. Further security is provided by proposing a novel Video Steganography approach using the Least Significant Bit (LSB) technique. This paper gives a detailed structure of hiding the data using multiple levels of security. Thus, this paper provides a holistic approach to implement a high level of security in SaaS applications.

With the rapid development of the Internet technology, data security is becoming more and more important. Data encryption is an important means to protect data security. AES is an important algorithm for encrypting data. However, when the amount of data needed to be encrypted is large, the traditional AES algorithm runs very slowly. This paper presents a parallel AES encryption algorithm based on MapReduce architecture, which can be applied in large-scale cluster environment. It can improve the efficiency of massive data encryption and decryption by parallelization. And the paper designs a parallel cipher block chaining mode to apply AES algorithm. Experiments show that the proposed algorithm has good scalability and efficient performance, and can be applied to the security of massive data in cloud computing environment.

AES algorithm has a large amount of data migration between storage side and computing side. Especially on mobile devices, where the data migration demand is expensive, however, the existing Von Neumann architecture cannot support such demand due to the separation of storage and computation. Memristor, a new device, which integrates storage and computing together, is expected to solve the problem with low power and short delay of AES. The XOR logic operation plays centric rule in AES for carry addition and data encryption. However, the current researches on the logic operation of memristors only stays at basic logic (AND, OR, NOT) level, and the XOR logic operations constructed by these basic logics generally have problems such as too large area, long calculation sequence and complicated control. Therefore, this paper provides a new way to design energy efficient XOR logic and uses it to implement adder and AES encryption algorithm. The results show that the XOR logic method in this paper uses the least number of memristors and the shortest calculation sequence length comparing with the two popular baselines. The XOR logic based on memristor effectively decreases the power consumption and delay by at most 99% and 50% respectively.

As we know that the world is been surrounded by the internet and interconnected to it and the different things or we can say the edge devices which helps us to connect to network and communicate to the different alternatives with the surroundings. In this paper we would be discussing about the different algorithms and their and disadvantages and how the advanced standard algorithm is been applied we has an great effect on cryptography and the different process carried out in the encryption and decryption process. In this paper the encryption and the decryption would be given in 128 bit format in hexadecimal, binary or any other format and the key expansion for getting the cipher text. in cryptography their are three classification for the expansion of the key which can be symmetric, asymmetric and the hash function in this paper we have discussed and the symmetric key is been given for both encryption and decryption process.as we know that we are using the 128 bit length which has 10 rounds and the initial round includes the state and the different transformation in the cryptograpy process which is the symmetric key expansion in which the same key is been applied to both encryption and decryption in binary, hexadecimal, etc. As it is lossless operation many applications can be derived using this algorithm as we are using symmetric key block cipher. We are limiting our paper with the 128 bit length of data in verilog language. For encryption and decryption the proposed paper describes the cryptograpy which would be having the fixed size. In this algorithm where we are using the symmetric key block cipher where the key would be given same with respect to encryption. Many applications it can be used as it is lossless operation. We limit our focus on 12b8 bit AES encryption and decryption where coded in VHDL coding. The proposed paper describes the private key cryptosystems which has a key with fixed size.

Steganography is a creative work of concealing secret data or message within an ordinary, non-secret file. This helps to prevent detection of the existence secret data. Steganography takes information hiding one step ahead than data encryption. Data encryption hides the data, but Steganography hides the existence of the data. In this paper, we combine both Data Steganography and Data Encryption, thus providing double layer security. The paper deals with Multimedia Steganography which enables working successfully with video files, without obscuring the quality of the resultant video. The proposed technique deals with Steganography in Transform domain, thus overcoming the drawbacks of the spatial domain techniques. An important drawback of spatial domain technique is that data is prone to different attacks, whereas Transform domain provides a robust aftermath. Applying the advantages of Transform domain, we have used DCT and DST technique on the cover video whilst using Encryption algorithm of Scrambling- AES on the message image, ensuring double layer security.

2019 International Conference on Smart Applications, Communications and Networking, SmartNets 2019 -- 17 December 2019 through 19 December 2019 -- -- 159416 2-s2.0-85084391773 The meaning of security is to protect something important from not authorized peoples. Cryptography is one of the security systems. Many applications could be used in the security systems like military applications, email, banking, information technology of database. The proposed system uses advanced encryption standard(AES) with secure hash algorithms(SHA-1) to produce a strong ciphertext. Moreover, this paper make the combination of (SHA-1) which is a one way encryption, as a key with (AES) algorithm which is a two way encryption as a ciphering generator to obtain confidentiality and integrity, In this paper presented implementation of Advanced Encryption Standard (AES) and Secure Hash (SHA-1) Algorithm by the use of FPGA Hardware card, However implementation of the AES algorithm and SHA-1 using LABVIEW environment with MATLAB system generator to generate stream data to FPGA hardware target. The output of the hash function is used as an input key for AES in order to improve data security, From the algorithms result of AES and SHA-1 obtained in FPGA, the system obtained how it is simple in modeling hashing and AES algorithms, generating hash codes and plain texts in (small and capital letters), symbols and numbers. The FPGA card used in this system (Spartan 3AN)with frequency (50%), the complete system take (1,147)size from the available space of (11,776) and accuracy (90%),the system work properly. © 2019 IEEE.

In today’s world web applications have become an instant means for information broadcasting. At present, man has become so dependent on web applications that everything done through electronic means like e-banking, e-shopping, online payment of bills etc. Due to an unauthorized admittance might threat customer’s or user’s confidentiality, integrity and authority. SQL injection considered as most Spartan dangerous coercions to the databases of web applications. current scenario databases are highly susceptible to SQL Injection[4] . SQL Injection is one of the most popular and dangerous hacking or cracking technique . In this work authors projected a novel approach to mitigate SQL Injection Attacks in a database. We have illustrated a technique or method prevent SQLIA by incorporating a hybrid encryption in form of Advanced Encryption Standard (AES) and Elliptical Curve Cryptography (ECC) [5]. In this research paper integrated approach of encryption method is followed to prevent the databases of the web applications against SQL Injection Attack. Incidentally if an invader gains access to the database, then it can cause severe damage and ends up with retrieves data or information. So to prevent these type of attacks a combined approach is projected , Advanced Encryption Standard (AES) at login phase to prevent the unauthorized access to databases and on the other hand Elliptical Curve Cryptography (ECC) to encode the database so that without the key no one can access the database information [3]. This research paper illustrates the technique to prevent SQL Injection Attack.

This is an extension of an ongoing research project on Fully Homomorphic Encryption. Arithmetic Circuit Homomorphic Encryption (ACHE) [1] was implemented based on (TFHE) Fast Fully Homomorphic Encryption over the Torus. Just like many Homomorphic Encryption methods, ACHE does not integrate with any authentication method. Thus, this was an issue that this paper attempts to resolve. This paper will focus on the implementation method of integrating RFC7664 [2] into ACHE. Next, the paper will further discuss latency incurred due to key generation, the latency of transmission of public and private keys. Last but not least, the paper will also discuss the key size generated and its significance.

This paper proposes a hybrid reversible image data hiding technique (RIDH), which is used to reconstruct an original image upon the extraction of the embedded data. Encryption and data hiding are two effective means of data protection. Encryption converts an original image into unreadable ciphertext and data hiding is used to embed additional data into image. Previous methods used secrete data hiding key for data hiding, now this paper proposes both encryption and decryption with rivest cipher 4 (RC4) and data hiding with advanced encryption standard (AES) without secrete data hiding key. Support vector machines (SVM) classifier is used to separate encrypted and non-encrypted blocks to reconstruct original image from embedded image by using feature calculation of each and every block. Evantually a trail results are given to approve the predominant execution of our method.

The high efficiency video coding (HEVC) partial encryption (PE) technique depends on encrypting the highly sensitive data on the video bit stream. The HEVC PE technique should keep the video format compliance, should be of the same bit rate, and ensure real-time constraints. The paper suggests an effective RC6 HEVC PE technique which encrypts sensible video data bits with low complexity overhead, fast encoding time for real-time applications, and fixed HEVC bitrate. These features result from using the low computational complexity RC6 block cipher for encrypting the selective video bins. The proposed RC6 HEVC PE encrypts the discrete cosine transform (DCT) coefficients sign bit, the DCT remaining absolute values suffixes that are binarized by Exp-Golomb (EGk) order zero, the motion vector difference (MVD) sign bits, and MVD absolute values suffixes that are binarized by EGk order one. Also, this paper introduces experimental results that compare between the proposed RC6 HEVC PE and HEVC PE algorithms that use the Advanced Encryption Standard in different operation modes. This paper presents more details about the security analysis of RC6 HEVC PE including encryption quality test, key space test, statistical analysis such as histogram and correlation coefficient analysis, and sensitivity analysis such as the key sensitivity analysis. The achieved test results ensured and confirmed the security, reliability, and robustness of RC6 HEVC PE technique.

With the development of Internet-of-Things technology, the electronic devices nowadays are embedded with “smart” functionalities, which enable them to upload data to the cloud for the easy access of the users. Such functionalities have been popular among commercial products. However, as we shall show in this paper, these functionalities, if not protected properly, can be vulnerable to attacks. An unprotected implementation leaks significant level of information related to the sensitive operations, which could pose threats to the security of the device. In this paper, we demonstrate a practical attack against a LoRaWAN communication module. This attack uses the deep-learning-based side-channel attack to recover the key for encrypting the payload data. By capturing less than 100 communication packets, the trained convolutional neural network is capable of recovering the full key for AES encryption.

This paper presents an implementation of Convolutional Neural Network (CNN) symmetric encryption. The results based on selected criteria are compared with Advanced Encryption Standard (AES). Authors are testing both implementations using the set of differently sized and content independent files. Compared metrics include the execution time, memory occupancy and processor load. Robustness of CNN encryption against the crypto attacks was not tested and it is out of the scope of this paper. Concluded results offer the usability prospects of selected neural network for symmetric cryptographic purposes. The results of the experiments have shown that CNN has the potential for cryptographic purposes under the conditions specified in this paper.

In the coming years, sensors will likely have a permeated every aspect of our life. Several works explain how the Internet of things (IoT) will have an impact on almost all aspects of our life and why security is at the top of the list of IoT challenges. Constrained nodes constitute a significant portion of devices in IoT. These nodes are characterized by severe constraints on power, memory, and processing resources, therefore, do not support conventional security protocols such as Transport Layer Security (TLS). Message Queue Telemetry Transport (MQTT) is a lightweight communication protocol particularly adapted for constrained nodes. Security solution, in MQTT protocol, can be achieved in multiple layers. To ensure end-to-end encryption, Authenticated Encryption with Associated Data (AEAD) is one of the most recommended solutions. Actually, the Advanced Encryption Standard (AES) is one of the most widely used standard encryption methods. However, constrained nodes processors did not have hardware support for AES and the physical-layer packet size of these nodes is limited. This paper proposes ChaCha20-Po1y1305 AEAD as a solution to secure constrained nodes communication over MQTT/MQTT-SN. ChaCha20 and Poly1305 are respectively lightweight stream cipher and one-time authenticator which continue gain popularity from crypto community. A prototype of the proposed solution is implemented on constrained nodes like Arduino UNO. The paper mainly provides results related to memory footprint and execution time. These results indicate that the proposed scheme requires small amount of memory and present low processing time.

IoT technology is growing very fast and one of the requirements of this technology is integrating different communications protocols and networks. In an IoT network, security of such a heterogeneous and large network is very important. Transport systems are part of this super network and in-vehicle protocols are used in such systems. Unfortunately, the Controller Area Network (CAN) protocol, the most popular protocol in the systems, designed without security in mind. In this paper, the Advanced Encryption Standard (AES), an encryption algorithm, is used to prevent masquerade and replay attacks in order to secure CAN protocol to an appropriate level. The paper has a plan to explore for an efficient implementation of AES encryption algorithm for the communication protocol. These implementations have been evaluated on an FPGA ML605 development board. The best implementation of the AES among 8-, 16-, 32- and 64-bit data paths has been investigated. The most important criteria for the protocol in these AES designs are such as consumed power, area, and cost in addition to providing better throughput. The 64-bit structure of the designed AES is selected which has the frequency of 21.4 MHz, significant throughput of 412.39 Mbps, reasonable area of 784 slice on Spartan III FPGA.

Non-linear substitution is the essential step in the most popular Advanced Encryption Standard symmetric-key cryptosystem. Designing substitution boxes (S-boxes) with good quality solution and execution time efficiency are the significant challenges for the researchers for eliminating vulnerable attacks due to the static behavior of S-box. The main aim of this paper is to design a dynamic S-box for attaining the properties of high non-linearity and low autocorrelation. In this paper, a dynamic sub-key dependent S-box design is proposed to overcome the drawbacks of static S-box. The dynamic sub-key is generated based on the data block, so the proposed system is mostly depend on the data to provide more secure against the intruder. The proposed system generate a strong S-box with the good quality solutions and high efficiency in the execution time. The mapping of the non-linear initial S-box with the final sub-key generated S-box based on the cat swarm optimization function, so that the final S-box design is obtained as high non-linearity and low autocorrelation. The simulation performance is analyzed in in terms of solution quality and execution time compared with other relevant approaches.

In secure cryptographic primitives, such as block ciphers, the reliability of hardware implementations needs to be closely considered because faults in the hardware implementations can potentially reduce or impact on the underlying security. In this paper, we present approaches to detect errors in hardware implementations of the inversion in GF(28). The proposed approaches are based on both nonredundant and redundant arithmetic, utilizing normal basis (nonredundant) and two redundant Galois field representations, i.e., polynomial ring representation and redundantly represented basis through tower fields. To the best of our knowledge, this is the first work focusing on the error detection architectures for redundant arithmetic-based inversion in GF(28). The presented signature-based schemes in this paper are general and can be applied to block ciphers with 8-bit S-boxes, such as Camellia, SMS4, the advanced encryption standard, and CLEFIA. We present the results of error simulations and application-specific integrated circuit implementations to demonstrate the utility of the presented schemes. Based on the specific implementation’s security/reliability objectives and the overhead/degradation tolerance for implementation/performance metrics, one can fine-tune and tailor the proposed work to achieve more reliable inversions in GF(28).