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Micro-Electro-Mechanical System (MEMS) capacitive accelerometers have received extensive attention in recent years due to their excellent performance indicators; especially in the fields of noise, power consumption, and bias instability, great development and progress have been made. In the field of noise, effective noise reduction is achieved by introducing oversampling modulation technology combined with digital noise reduction technology. In power consumption, the power consumption of the accelerometer is effectively reduced by using the successive approximation structure in the interface circuit and using the finite state machine for precise control. In bias instability, the effects of temperature offset and zero-point drift are suppressed by using a hybrid topology connection structure in the interface circuit, and an effective reduction of bias instability is achieved. In this paper, the research and progress of MEMS capacitive accelerometer in the field of noise, power consumption and bias instability are reviewed, and the articles published in recent years are listed and summarized and prospected. [ABSTRACT FROM AUTHOR]

Reliability and energy efficiency are two hostile objectives considered in designing task scheduling in most real-time multiprocessor systems on chip (MPSoC). Addressing and improving one of them may affect and degrade the efficiency of the other one and vice versa. In this paper, we intend to examine these challenges and ultimately achieve an optimal energy consumption and reliability state. This paper presents a novel scheduling technique that can adapt to the limitations of real-time systems and have optimal energy consumption and reliability. This is done by minimizing the overlap of tasks, adjusting the speed of processors and the number of backups of each task. The proposed scheme reduces energy consumption on average by 11% to 42% compared to the previous state-of-the-art techniques and keeps the reliability at a high level. [ABSTRACT FROM AUTHOR]

A novel phase frequency detector design is introduced in this study, which removes dead and blind zone issues by eliminating reset path, therefore accelerating the acquisition process. High speed, low power and minimal phase noise are all characteristics of the proposed circuit. The circuit is designed in the Cadence Virtuoso environment and is implemented in CMOS GPDK 180 nm library using a 1.8 V supply voltage. Post-layout simulations have been conducted to ensure that the findings are accurate. The circuit's robustness is tested over process, voltage and temperature fluctuations. The suggested PFD achieves a phase noise of − 1 5 9. 1 7 dBc/Hz, which is significantly lower than other published circuits. This PFD dissipates 10.25 μ W of power at its maximum operating frequency of 10 GHz. The PFD encompasses an area of 275 μ m2. The proposed PFD outperforms other PFD circuits in the literature, making it ideal for applications requiring minimal jitter, low power, etc. [ABSTRACT FROM AUTHOR]

This work illustrates the design of the cell-based variable-gain amplifier (VGA) with less power consumption and improved noise margin. The variable gain amplifier is incorporated into the current wireless front-end modules. The body-bias technique in the n channel MOSFET (n-MOS) devices greatly aided in the power reduction of the cells. The device characteristics were fine-tuned to get better gain and bandwidth and reduced the supply voltage. This technique ultimately reduced the number of cell stages required to meet the expectation. The reduction of the supply voltage and the technology upscaling helped to improve the noise margin. The presented unit cell achieved accurate dB-linear characteristics across a wide tuning range, based on a unique gain control method with a combination of sub-threshold n-MOS and saturation n-MOS transistors as active loads. A 7-cell reconfigurable VGA is simulated in 0.18- μ m Complementary MOSFET technology to verify the concept. The simulation results showed that the bandwidth of the VGA is greater than 2.5 GHz, while less than 0.78 mW is consumed from a 1.5-V supply. A noise figure of 23.7 dB is measured. Also, the VGA achieves a gain control range of 19 dB with a gain error less than ± 0. 5 dB or 26.3%. These results make the designed amplifier adequate for high-frequency applications. [ABSTRACT FROM AUTHOR]