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This paper puts forward a new vertical-tunneling-attributed dual-material double-gate heterojunction-TFET (VTDMDG-HTFET). The device structure of VTDMDG-HTFET includes Si 0. 7 Ge 0. 3 material for the designing of source region. The mechanism of vertical tunneling in VTDMDG-HTFET provides superior electric field at tunneling interface and leads to improved transfer characteristics. VTDMDG-HTFET also includes metal gate work-function engineering approach to facilitate high ON-current and small OFF-current. Application of high- k dielectric material HfO˙2 in the form of gate oxide enhances the capacitive-coupling at channel-source interface. Moreover, the work includes the comparison of proposed VTDMDG-HTFET with the conventional vertical-tunneling based dual-material double-gate-TFET (VTDMDG-TFET). It has been observed from the simulation results that SiGe source-based VTDMDG-HTFET offers better DC characteristics in terms of superior ON-current, smaller OFF-current, steeper subthreshold-slope, lower threshold voltage, higher transconductance along with smaller drain-induced barrier-lowering (DIBL) effects as compared to its counterpart silicon-source-based VTDMDG-TFET. In this work, reliability of VTDMDG-HTFET has also been examined and compared with VTDMDG-TFET in terms of temperature sensitivity and effect of different interface trap charges. The device simulation and investigations have been carried out using technology computer aided design (TCAD) tool. Moreover, device circuit mixed-mode simulation analysis is carried out for conventional and proposed device based resistive load inverters. A comparison is performed between both the inverters in terms of prorogation delay and switching threshold voltages. Further, the mixed mode simulation analysis is also performed for the proposed device based inverter under the influence of different interface trap charges (ITCs). Study shows that reliability performance of the proposed device is better as compared to its counterpart conventional device. Hence, vertical tunneling and SiGe source-based VTDMDG-HTFET can be a better choice for various applications such as analog/RF, analog and digital electronic circuits, energy harvesting, gas-sensing and memory devices. [ABSTRACT FROM AUTHOR]

This paper introduces a novel framework that automates and accelerates the development of embedded Field Programmable Gate Arrays (eFPGAs). The proposed solution is considered as the first environment for tree-based eFPGA implementation including software, hardware and loader. The developed framework allows users to generate eFPGA architecture in the form of hardware description language using Physical Design Flow (PDF) tool. It is a powerful tool that can produce a wide variety of designs ranging from small eFPGA to complex eFPGA. The bit file description of practical application is done in parallel, simultaneously and rapidly by the suggested Computer Aided Design (CAD) tools. The Loader, called Multi-Level Loader (MLL), is also provided to inject the bits into the corresponding SRAMs. Our framework is widely explored by modifying the data width. This research proves that data width equal to 17 has the best trade-off between performance, area and static power. However, it is penalized for buses having data length greater than 32. The experimentation demonstrates that a data width equal to 12 is the best for a 32-bit bus. Automation and significant acceleration of the eFPGA development cycle are also achieved in this study. A set of bench-marking applications with various multi-use purposes is mapped. The experimental results show the efficiency and flexibility of the proposed framework. [ABSTRACT FROM AUTHOR]