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In this paper, a new three-dimensional chaotic system with two exponential nonlinearities is presented. The analysis of fixed points of the proposed system suggests existence of one hyperbolic index-2 spiral saddle-type fixed point. The proposed system fulfils Shilnikov criterion and nature of the chaos is found to be dissipative. Bifurcation diagrams, maximum Lyapunov exponents and Kaplan–Yorke dimension are examined through numerical simulations to investigate dynamics of proposed system. The hardware feasibility of the proposed system is illustrated through current feedback operational amplifier (CFOA)-based circuit implementation. The proposed circuit uses six CFOAs, two diodes to establish nonlinearity, eleven resistors and three capacitors. The absence of analog multiplier in the proposed circuit makes it superior to the existing counterpart in the sense that it does not require area and power-consuming active building block. To confirm the chaotic nature of the proposed circuit, LTspice simulations are done to obtain phase portraits which are found to be strange attractors and are topologically different from the shape of the existing attractors. Moreover, we have investigated the synchronization of the proposed chaotic system using adaptive control scheme and proposed CFOA-based complete circuit design of the adaptively synchronized system. Also, the effect of the tolerance of passive components and temperature on the behavior of the proposed chaotic circuit and the complete synchronization circuit has also been studied. It is found that the circuit is sensitive to the value of resistors and temperature to an extent and can work properly within their limits. [ABSTRACT FROM AUTHOR]

Micro-Electro-Mechanical System (MEMS)-based pressure sensors operating on the principle of piezoresistivity have found profound application in various fields like automobile, aerospace, aviation, biomedical and consumer electronics. Various research studies have been conducted to optimize the design of MEMS-based pressure sensors to meet specific requirements of different fields. Modification in the structure of the piezoresistors placed on these sensors has shown great effect in this regard. However, most of these improvements have been validated through fabrication and measurement, but there has been a lack of significant studies developing analytical models to explain these improvements. This paper studies the performance of a single-turn piezoresistor design on a square silicon diaphragm. The analytical model relates the dimensions of the single-turn piezoresistor on a square diaphragm to the output voltage, and hence, sensor sensitivity is laid out. The correctness of the relation is also validated through Finite Element Analysis (FEA) performed using COMSOL Multiphysics software. Hence, an optimized single-turn design is presented which achieves a sensitivity of 203.57 mV/V/MPa over a pressure range of 0–1 MPa. These results are then compared to work from existing literature. The comparison shows an improved performance which was achieved by optimizing the design through its derived analytical model. The proposed sensor can be utilized in disposable blood pressure measurement system where high sensor sensitivity is required. [ABSTRACT FROM AUTHOR]

In this paper, a flux-controlled memristor with linear memductance is proposed. Compared with the memristor with piecewise linear memductance and the memristor with smooth continuous nonlinearity memductance which are widely used in the study of memristive chaotic system, the proposed memristor has simple mathematical model and is easy to implement. Multisim circuit simulation and breadboard experiment are realized, and the memristor can exhibit a pinched hysteresis loop in the voltage-current plane when driven by a periodic voltage. In addition, a new hyper-chaotic system is presented in this paper by adding the proposed memristor into the Lorenz system. The transient chaos and multiple attractors are observed in this memristive system. The dynamical behaviors of the proposed system are analyzed by equilibria, Lyapunov exponents, bifurcation diagram and phase portrait. Finally, an electronic circuit is designed to implement the hyper-chaotic memristive system. [ABSTRACT FROM AUTHOR]

An extended Neyman–Pearson detector based on the combination of a traditional matched and wavelet filter in pulsed monostatic radar was proposed in this paper. Its properties were compared with properties of the cell average constant false alarm radar detector in the presence of white noise. The properties of detectors were examined in the receiver operating characteristic curves, parameter space. It consisted of false detection rate and the rate of true positive detected targets. In order to investigate the influence of temperature, the new parameter space was constructed: the temperature versus the rate of true positive detected targets. The traditional Neyman–Pearson detector based on a matched filter was fully operational and superior in the temperature range between 290 K and 350 K. Below this temperature range, its performance is completely degraded. It has been shown that by adding a wavelet filter, it can extend this temperature range between 260 K and 350 K. In the temperature range, where all detectors are fully operational, extended and classic Neyman–Pearson detectors had better performance than constant false alarm radar detector in the receiver operating characteristic curves' parameter space. [ABSTRACT FROM AUTHOR]

The world is witnessing a sudden shift in the paradigm of technology moving from centralized to decentralized approach. Centralized approach leads to single point of failure if any fault occurs and hence a whole system comes to rest. Hence, a decentralized approach like Multi-Agent System is trending now-a-days. A MAS is a collection of a number software entities (agents) working together in pursuit of specified tasks. This paper presents a comprehensive review on various aspects of multi-agent system. The paper explains the basic concepts of MAS with various ways it has been defined in literature. A comparison has been made on the standards to be followed for applying MAS. Classification of MAS architecture has been investigated and compared. Application of MAS in various areas of optimization technique, software platform and real-time simulation are listed in the paper. The paper draws attentions toward benefits and limitations of using MAS based on the survey done. Finally, after visualizing the wide scope of research in the field of MAS, an attempt has been made to identify future research avenues. [ABSTRACT FROM AUTHOR]

In this paper, a systematic and hierarchical synthesis methodology is presented for nonlinear analog synthesis to meet the essential requirement for system automation. Behavior of nonlinear system, represented by polynomial expression, has been studied by decomposing it into linear and nonlinear sub-expression. Such sub-expressions are realized with basic building block like multiplier, adder, quadratic, etc., each of which can be represented as a network of the current mode device, operational transconductance amplifier (OTA). Polynomial series is used to represent various important functions in signal processing applications. Few nonlinear functions with their OTA representation are discussed as the applications of polynomial series. The response of all the circuits are studied through SPICE simulation validating the proposed methodology. [ABSTRACT FROM AUTHOR]

This paper presents a novel Nyquist SAR-VCO ADC architecture. To improve the dynamic performance, a 4-phase counter is introduced to the proposed architecture. Thanks to the employed 4-phase counter, requirements on both the counting time error and the nonlinearity of the VCO gain are relaxed. In addition, rather than adopting the oversampling strategy to realize the noise-shaping, the proposed Nyquist architecture can quantize signals at as high as the Nyquist frequency. Hence, the signal bandwidth is broadened successfully. Beyond these, influences of nonideal effects (such as linearity of the VCO gain, mismatch between the differential VCO gains, counting time error and clock jitter) from practical circuit implementations and layout designs are theoretically analyzed and modeled. Behavioral simulations show that, at the near Nyquist input frequency and 10MS/s sampling rate, an SNDR of 61.43dB, an SFDR of 78.08dB and an ENOB of 9.91 bit are achieved, respectively. [ABSTRACT FROM AUTHOR]

This paper presents an N-path filter with high out-of-band rejection using feed-forward technique. The structure utilizes two four-path filters, one as the main-path and the other as auxiliary-path, and two TIAs to increase the order of the filter from two to four. As a result of this, and due to using two series resistors in the main path, the out-of-band rejection is significantly improved. Analysis and simulations show that the series resistors can be chosen such that the NF degradation is below 2 dB while the out-of-band rejection is improved by about 20 dB. Therefore, the trade-off between the insertion-loss and out-of-band rejection is relaxed compared to conventional N-path filter. Also, it is shown that decreasing the size of baseband capacitors improves the NF of the filter. The effect of clock phase-noise on NF of the filter in the presence of strong out-of-band blocker is modeled and simulated. [ABSTRACT FROM AUTHOR]

This paper proposes a simple and passive harmonic reduction method at dc link of 20-pulse rectifier. The 20-pulse topology is obtained via two paralleled 10-pulse ac–dc converters, each of them consisting of a five-phase (five-leg) diode bridge rectifier. For independent operation of the paralleled diode-bridge rectifiers, a zero sequence blocking transformer (ZSBT) is designed and implemented. Connection of a tapped inter-phase transformer (IPT) at the output of the ZSBT results in doubling the number of the output voltage pulses. The application of the pulse doubling technique with a low power rating (2% of the load power rating) results in a simpler and more economical configuration of the whole system and increased number of pulses. The design is suitable for retrofit applications where a six-pulse diode bridge rectifier is being utilized. The proposed structure is simulated using Matlab/Simulink software under different loading conditions. The simulation results confirm the significant improvement of the power quality indices (IEEE-519 standard requirements) at the point of common coupling (PCC). Experimental results are obtained using the designed and constructed laboratory prototype of the proposed converter to validate the design procedure and the simulation results. The VA rating of the magnetic circuit is calculated to confirm the savings in space, volume, weight and cost of the proposed configuration. [ABSTRACT FROM AUTHOR]

Two new minimum passive component oscillators using inverting current conveyor (ICCII-) acting as a voltage negative impedance converter are generated from the Sallen Key low-pass and high-pass filters. It is also shown that the Sallen Key low-pass, high-pass, and band-pass filters are the origin of the three minimum component oscillators using the current conveyor acting as a current negative impedance converter. In addition, it is also shown that the Sallen Key high-pass and band-pass filters are the origin of the two minimum component oscillators using single input single output transconductance amplifier as the active element. Although this paper is considered partially a review paper it includes new generation methods and new minimum component oscillator circuit realizations. Simulation results for the new oscillators using ICCII- are included. [ABSTRACT FROM AUTHOR]

This paper proposes designing a precision rectification circuit by using a single operational transresistance amplifier (OTRA). The proposed circuit is a switch-controllable OTRA-based full-phase operation precision half-wave rectifier, which can rectify an input signal to yield four-phase half-wave rectified output signals. Compared with existing designs, the advantage of the proposed circuit is that all of the possible rectified outputs of a half-wave rectifier can be obtained in one configuration. This paper first reviews previously reported half-wave precision rectifiers consisting of various active devices and the proposed OTRA-based precision half-wave rectifier; subsequently, an analysis of non-ideal effects and design considerations are presented. Computer simulations of the proposed circuit were conducted for verifying the feasibility of the circuit by using the Taiwan Semiconductor Manufacturing Company (TSMC) 0.35-m CMOS process technology. For practical circuit measurements, a prototype circuit was implemented, and commercially integrated circuits (AD844ANs) and discrete passive components were used to conduct experimental tests. The simulation and experimental results exhibited satisfactory agreement with those of theoretical analyses. [ABSTRACT FROM AUTHOR]

Power gating (PG) is used to reduce leakage power by shutting down the power supply of the inactive block of the circuit. PG technique for finite state machine (FSM) is used to reduce not only leakage power but also the switching power of circuit. One FSM is partitioned into two sub-FSMs and encoded for minimizing total power for the power-gated design of the circuit. Depending on the state of the machine, at a time one sub-FSM is power gated by shutting off the power supply. There is a complete eradication of power in power-gated sub-FSM, but another one is in an active mode that continues to dissipate power. There is a scope to reduce leakage in active sub-FSM if the clock period is larger than the critical path delay of the combinational part of this sub-FSM. In this condition, there is a certain portion of the clock period which is idle and in this period PG may be used. The objective of this paper is to reduce power by applying PG at circuit level to the active sub-FSM, whereas, inactive sub-FSM is still power gated. This paper presents a new technique, called WCPG_IN_PG, which reduces the power of active sub-FSM (within the clock period) and power-gated FSM. By varying the frequency, power results are reported for different input combinations. [ABSTRACT FROM AUTHOR]

This paper presents a multi-output on-chip switched-capacitor (SC) DC-DC converter simultaneously providing two output voltages (2VDD/3 and VDD/3, in addition to the available full VDD) that enables the use of three different power modes for optimizing system power/performance trade-offs: super-threshold (full VDD), near-threshold (2VDD/3) and sub-threshold (VDD/3). Unlike some previously proposed multi-output SC converters, the multiple conversion ratios of the proposed converter are achieved without changing the topology of the circuit, thus fewer components being needed to support multiple voltages. The paper also presents an optimization method by using unequal flying capacitors for different regions of the circuit by taking advantage of the different levels of expected power consumption in the various power modes. Above 84% and 70% efficiencies are obtained in simulation over a range of load currents from 0.4 to 5 mA, and from 0.4 to 1 mA, with conversion ratios of 2/3 and 1/3, respectively. The target application for the proposed converter is for circuits with discrete power modes and for systems that use dithering to emulate a continuous range of voltages such as the panoptic dynamic voltage scaling (PDVS). [ABSTRACT FROM AUTHOR]

This paper exposes circuit design of linear congruential generator (LCG) and implementation in FPGA based on block reduction technique. The circuit is derived from LCG algorithm proposed by Lehmer. Block reduction technique has been used to simplify the circuit. Several net connections among the blocks of the circuit are ignored or disconnected and the multiplier is replaced by a shifter. Simulations of both behavior and timing have been done and the results confirm its algorithm. The Cyclone II EP2C8Q208C8N and Cyclone IV E EP4CE115F29C7N of Altera have been chosen to extract comparison data of speed and occupied area. Further comparison of shift technique and the wordlengths reduction technique has been made. In general, the proposed design is far simpler than the previous published LCG circuit. [ABSTRACT FROM AUTHOR]

This review paper describes different lumped circuitry realizations of the chaotic dynamical systems having equilibrium degeneration into a plane object with topological dimension of the equilibrium structure equals one. This property has limited amount (but still increasing, especially recently) of third-order autonomous deterministic dynamical systems. Mathematical models are generalized into classes to design analog networks as universal as possible, capable of modeling the rich scale of associated dynamics including the so-called chaos. Reference state trajectories for the chaotic attractors are generated via numerical analysis. Since used active devices can be precisely approximated by using third-level frequency dependent model, it is believed that computer simulations are close enough to capture real behavior. These simulations are included to demonstrate the existence of chaotic motion. [ABSTRACT FROM AUTHOR]

DNA computation is an emerging technology to perform complex information processing at the nanoscale era. Molecular programming with localized DNA hybridization is a systematic, parallel and scalable approach for DNA computation. Considerable methods are developed for the design of Localized DNA circuits. Due to significant theoretical and technological difference between this technology and conventional electronic system, a customized design flow for this technology is a real requirement. We proposed a customized DNA cell placement algorithm for localized DNA hybridization technology in this paper. The main objectives in the proposed placement algorithm are minimizing the die footprint and total signal propagation path. Our implementations and simulations show the feasibility and efficiency of the proposed placement algorithm. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the direction of arrival (DOA) estimation problem of noncircular signals for coprime linear array (CLA). From the perspective of the CLA as extracted from a filled uniform linear array (ULA), a noncircular root-MUSIC algorithm is proposed to estimate the DOA which can avoid the spectral peak search and lower the computational complexity. Due to the noncircular characteristic, the proposed algorithm enables to resolve more sources than sensors. Meanwhile, the proposed algorithm has better angle estimation performance than some conventional DOA estimation algorithms. Numerical simulation results illustrate the performance of the proposed method. [ABSTRACT FROM AUTHOR]

Wireless transmission compliant to IEEE 802.15.4 standard can be significantly affected by background noise, multipath fading and interference from other radio sources. The influence of such disturbances is most commonly expressed in a form of error probability statistics. Accurate analytical error probability model is hard to acquire, since IEEE 802.15.4 standard uses imperfect spreading sequences. Some prior works in this field tend to idealize these imperfect spreading sequences in order to simplify calculations for error probability parameters. This paper presents an analytical error probability model for IEEE 802.15.4 communication in Rician fading channel, which uses original imperfect spreading sequences without their idealization. Proposed error probability model consists of mutually dependent chip, symbol, bit and packet error probability models. Presented theoretical results are confirmed by independent numerical simulation of IEEE 802.15.4 transmission through Rician fading channel according to the Monte Carlo method. [ABSTRACT FROM AUTHOR]

This paper proposes a novel monostable multivibrator featuring compact topology and current-tunable property. The proposed circuit was composed of a single differential input single output operational transconductance amplifier (DISO-OTA) with a few passive components. It was operated by a negative-edge triggering signal to generate an output pulse. The pulse height and width were tunable by the bias current of DISO-OTA and the external resistors. The proposed scheme is more compact than the existing topologies. This paper presents the circuit operations and a discussion of the non-ideal issues and design considerations. To demonstrate the feasibility of the proposed circuit, a prototype circuit built with commercially available DISO-OTA IC was used to execute the experimental tests. Is-Spice simulation and experimental results were consistent with theoretical analysis. [ABSTRACT FROM AUTHOR]

This paper presents a simplified analysis of a generalized cycloconverter and suggests a new method for the estimation of the cycloconverter period as a function of the control mode. The paper presents generalized theoretical results supported by computer simulations and demonstrated by examples. [ABSTRACT FROM AUTHOR]

The major bottleneck of coarse-grained reconfigurable arrays (CGRAs) is the excessive configuration overhead; as a result, computing potential cannot be fully utilized. At run-time, the function of CGRAs can be fully and dynamically reconfigured by changing contexts. Therefore, the frequency of context switching on CGRAs is very high. On the other hand, the configuration time of CGRAs is very long. This paper proposes three configuration approaches to reduce interval latency when switching configuration contexts. These proposed approaches include input data relocation (IDR), line-based context switching (LCS), and loop interval minimization (LIM). IDR relocates input data to the first stage of the pipeline; as a result, the delay time for the input data of the next data flow graph (DFG) is reduced. LCS is a LCS mechanism for adjacent independent DFGs to reduce the interval of context switching, thereby expanding the depth of the pipeline. LIM is used to minimize the interval of loops. Simulations on a coarse-grained reconfigurable processor called reconfigurable multimedia system (REMUS) show that 1080 p@30 fps for H.264 high profile video decoding can be achieved under 200 MHz working frequency. As for AVS and MPEG2 decoding algorithms, much higher performance, i.e., 1080 p@39 fps and 1080 p@41 fps, can be achieved respectively. [ABSTRACT FROM AUTHOR]

Although parallel multipliers are optimal for speed, they occupy considerable chip area. For applications with lengthy operands as cryptography, the required area grows further. On the other hand, digit multipliers reduce chip area at the expense of the number of cycles required to complete the multiplication. In such multipliers, one-or-both inputs are received serially one digit per cycle. Digit multiplier designs are flexible with respect to the digit width enabling designers to select the most suitable compromise between area and cycle count for the application under consideration. This paper proposes a new digit serial-serial multiplier that is more area efficient compared to other functionally-similar multipliers. First, we propose a new unsigned digit serial-serial multiplier that is area efficient. The multiplier has the ability to handle unequal-width operands. That is, one operand can be of dynamic width (unlimited digit count) and the other operand is of fixed width. Moreover, with a small modification, the multiplier can operate on two's complement operands. Then, the design is extended to support bit-level pipelining: the critical path of the multiplier pipeline stage is independent of the operand width and the digit width. Simulation results show that the proposed multiplier reduces the area over similar multipliers by up to 28% and reduces power by up to 31%. [ABSTRACT FROM AUTHOR]

In this paper, an ultra-low-voltage gain-enhanced four-phase charge pump is proposed. The proposed charge pump is designed in 0.18 μm 1.8 V standard CMOS process with high voltage boosting efficiency when the supply voltage is between 0.5 V and 1.8 V. Moreover, it eliminates the body effect by means of adding two auxiliary substrate switching PMOS transistor. The simulation results show that the proposed charge pump has higher efficiency than the other two low voltage charge pumps when the resistive load is 100 M ohm and the supply voltage is between 0.5 and 1.8 V. A test chip has been realized in a 0.18 μm 1.8 V standard CMOS process. The test results show perfect performance when the supply voltage is between 0.7 and 1.8 V. The proposed charge pump is quite suitable for low power applications. [ABSTRACT FROM AUTHOR]

In this paper, a CMOS digital pixel sensor (DPS) with pixel-level ADC based on pulse width modulation (PWM) scheme is proposed to overcome the restriction of low supply voltage imposed by device scaling trend. The pixel operates with a dynamic current comparison scheme to avoid using complex in-pixel comparator and achieve a high dynamic range (DR). By adjusting clock frequency for different illumination, DR is further extended due to increasing the maximum detectable photocurrent and lowering the minimum detectable photocurrent. The pixel contains a photodiode (PD), an 11-bit in-pixel SRAM and other 11 transistors, and occupies an area of 7 μm × 7 μm, with a fill factor of 31.3% using a standard 65 nm CMOS technology. Simulation results show that this pixel can work at a supply voltage as low as 0.5 V with 120 dB DR and 80 dB linear DR (LDR). The properties of high DR and logarithmic response make the proposed digital pixel be capable of human eye. Frame rate achieves 246 fps with 640 × 480 pixel array by using in-pixel ADC and SRAM. This makes the digital pixel very suitable for high-speed snap shot digital camera application. [ABSTRACT FROM AUTHOR]

High-radix router based on the tile structure requires large amount of buffer resources. To reduce the buffer space requirement without degrading the throughput of the router, shared buffer management schemes like dynamically allocated multi-queue (DAMQ) can be used by improving the buffer utilization. Unfortunately, it is commonly regarded that DAMQ is slow in write and read. To address this issue, we propose a fast and fair DAMQ structure called F2DAMQ for high-radix routers in this paper. It uses a fast FIFO structure in the implementation of idle address list as well as data buffer and achieves some critical performance improvement such as continuous and concurrent write and read with zero-delay. Besides, F2DAMQ also uses a novel credit management mechanism which is efficient in avoiding one virtual channel (VC) monopolizing the shared part of the buffer and achieving fairness among competing VCs sharing the buffer. The analyses and simulations show that F2DAMQ perforins well in achieving low latency, high throughput and good fairness under different traffic patterns. [ABSTRACT FROM AUTHOR]

This paper considers the noise modeling of interconnections in on-chip communication. We present an approach to illustrate modeling and simulation of interconnections on chip microsystems that consist of electrical circuits connected to subsystems described by partial differential equations, which are solved independently. A model for energy dissipation in RLC mode is proposed for the switching current/voltage of such on-chip interconnections. The Waveform Relaxation (WR) algorithm is presented in this paper to address limiting in simulating NoCs due to the large number of coupled lines. We describe our approach to the modeling of on-chip interconnections. We present an applicative example of our approach with VHDL-AMS implementations and simulation results. This article analyzes the coupling noise, the bit error rate (BER) as well as the noise as a function of the rise/fall time of the signal source which can significantly limit the scalability of the NoCs. [ABSTRACT FROM AUTHOR]

This paper presents an efficient approach to design wideband, accurate, stable, and minimum-phase fractional-order digital differentiators (FODDs) in terms of the infinite impulse response (IIR) filters using an evolutionary optimization technique called flower pollination algorithm (FPA). The efficiency comparisons of FPA with real-coded genetic algorithm (RGA), particle swarm optimization (PSO), and differential evolution (DE)-based designs are conducted with respect to different magnitude and phase response error metrics, parametric and nonparametric statistical hypotheses tests, computational time, and fitness convergence. Exhaustive simulation results clearly demonstrate that FPA significantly outperforms RGA, PSO, and DE in attaining the best solution quality consistently. Extensive analysis is also conducted in order to determine the role of control parameters of FPA on the performance of the designed FODDs. The proposed FPA-based FODDs outperform all the designs published in the recent literature with respect to the magnitude responses and also achieve a competitive performance in terms of the phase response. [ABSTRACT FROM AUTHOR]

This paper presents ultra-low voltage transconductor using a new bulk-driven quasi-floating-gate technique (BD-QFG). This technique leads to significant increase in the transconductance and the bandwidth values of the MOS transistor (MOST) under ultra-low voltage condition. The proposed CMOS structure of the transconductor is capable to work with ultra-low supply voltage of ±300 mV and low power consumption of 18 μW. The transconductance value of the transconductor is tunable by external resistor with wide linear range. To prove the validation of the new described technique a second-order Gm-C multifunction filter is presented as one of the possible applications. The simulation results using 0.18 μm CMOS N-Well process from TSMC show the attractive features of the proposed circuit. [ABSTRACT FROM AUTHOR]

Technology scale leads to increasing the vulnerability of new integrated logic circuits. The high-energy neutrons (present in terrestrial cosmic radiation) and alpha particles (that originate from impurities in the packaging materials) play important role in occurrence of transient faults which are effective factor for designing reliable integrated circuits. Thus, a fast and scalable method to obtain accurate reliability value is an issue to have a dependable logic circuit design. In this paper, a new fast and scalable method is proposed to calculate the circuit reliability in which the effects of nested reconvergent paths, as a main source of inaccuracy, is considered. In the presence of reconverging signals a binary probability matrix is used to resolve signals correlation problem and increase the accuracy of the obtained reliability. Also a new mixed binary-decimal code allocation is proposed to increase the scalability of the method and reduce the complexity of calculation. Simulation results show that our proposed solution is a fast method with less complexity and also gives an accurate reliability value in comparison with other methods. [ABSTRACT FROM AUTHOR]

Nano-scale area-efficient MOS devices are employed in this article to stabilize high-speed operational amplifiers (opamps) for those applications that deal with negative feedback. As an alternative choice, metal-insulator-metal (MIM) capacitors cannot be integrated in every technology as they require additional process masks. Moreover, these components suffer from large silicon area. In this paper, considerations of a successful MOSFET-only amplifier design are highlighted and described. These considerations make it possible to fabricate these amplifiers for a nano-scale digital system-on-chip (SoC). Circuit-level simulations include comparison between MOS capacitors (MOSCAPs) with MIM capacitors (MIMCAPs) in two identical processes. The efficiency of the given design considerations are also validated through simulation in 90-nm CMOS technology. A MOSFET-only amplifier is designed as the main part of a 5 MS/s sample-and-hold. Using the proposed design techniques, the MOSFET-only amplifier with Miller compensation recovers 51% silicon die with respect to a MIMCAP amplifier for identical signal-to-noise-plus-distortion (SNDR) ratio. [ABSTRACT FROM AUTHOR]

A current source circuit for high-resolution CMOS image sensors is introduced in this paper, which can provide a stable current with immunity from IR-drop along the power and ground wires. In the circuit, two pre-charged floating capacitors controlled by two-phase non-overlap clock are connected between the gate and source of a MOS transistor alternately to maintain a constant VGS of the MOS transistor. In this way, the current flowing through the MOS transistor will be stable and has nothing to do with power level. The post simulation results show that the current supplied by the proposed circuit decreases only by 1.6% when the voltage of the power supply decreases by 30%. The simulations have proved that the proposed circuit can improve the performance of high-resolution CMOS image sensors. [ABSTRACT FROM AUTHOR]

In this paper, a new current-mode (CM) circuit for realizing all of the first-order filter responses is suggested. The proposed configuration contains low number of components, only two NMOS transistors both operating in saturation region, two capacitors and two resistors. Major advantages of the presented circuit are low voltage, low noise and high linearity. The proposed filter circuit can simultaneously provide both inverting and non-inverting first-order low-pass, high-pass and all-pass filter responses. Computer simulation results achieved through SPICE tool and experimental results are given as examples to demonstrate performance and effectiveness of the proposed topology. [ABSTRACT FROM AUTHOR]

Discrete global-sliding mode (SM) control of switching DC-DC converters is presented in this paper. The existence and stability conditions of quasi global-sliding mode are proposed. The design method for the discrete global SM controller is studied and applied to Buck converter with global-sliding mode control. Computer simulation and experimental results verify the validity of the theoretical analysis. [ABSTRACT FROM AUTHOR]

The cascade multilevel converter requires the least number of main components among traditional multilevel converter. In this paper, comparison of main components between proposed and traditional converter is shown. In addition, a generalized symmetrical multilevel inverter is proposed. The proposed multilevel inverter can generate DC voltage levels similar to other topologies with less number of components. The proposed topology results in reduction of installation area and cost and has simplicity of control system. This converter has been used in an AC drive system. The operation and performance of the proposed generalized multilevel converter has been verified by the simulation results using SIMULINK/MATLAB. The simulation results show its capability in voltage generation and speed control. [ABSTRACT FROM AUTHOR]

This paper presents a single-stage high-frequency full-bridge electronic ballast for high-pressure mercury lamps in high-luminance LCD projector systems. The studied electronic ballast is found to have high conversion efficiency due to its single-stage circuit with zero-voltage switching features. A high power factor can be achieved by using developed single-stage topology. The operation principles and design considerations are analyzed and discussed in detail. A laboratory prototype is designed and implemented for driving a 150 W projector lamp. The simulation and experimental waveforms are given to verify the feasibility of the proposed method. [ABSTRACT FROM AUTHOR]

In this paper, three dual-mode (mixed-mode) analog filters using only grounded capacitors and two to three second-generation current conveyors (CCIIs) are presented. The first proposed filter can provide a transimpedance-mode (TIM) second-order filter transfer function (TF), and is free from passive component matching constraints, which is advantageous in integrated circuit (IC) design. Other two mixed-mode filters having the property of tunability are derived from the first proposed filter. However, the developed filters in this work, like other active filters, suffer from nonidealities such as nonideal gain and parasitic impedance effects which increase the order of the filter TFs; accordingly, stability problem may arise. In this study, stability analysis using gain and phase margins is accomplished. To explain the claimed ideas, several computer simulations and an experimental test are performed. [ABSTRACT FROM AUTHOR]

In this paper, we describe a new algorithm for radar detection based on the Hough transform which employs the slope-intercept parameter space. Unlike the conventional Hough transform, we shift the parameter space cells to perform the transform. The computation burden is reduced. Another advantage is that those straight lines whose intercept are bigger than the radar maximum range can also be detected. In addition, we also investigate the performance of the algorithm we present and show its efficiency with some simulations. [ABSTRACT FROM AUTHOR]

In this paper, we propose a multi-objective optimization framework for SVM hyperparameters tuning. The key idea is to manage a population of classifiers optimizing both False Positive and True Positive rates rather than a single classifier optimizing a scalar criterion. Hence, each classifier in the population optimizes a particular trade-off between the objectives. Within the context of two-class classification problems, our work introduces "the receiver operating characteristics (ROC) front concept" depicting a population of SVM classifiers as an alternative to the receiver operating characteristics (ROC) curve representation. The proposed framework leads to a noncost sensitive SVM training relying on the pool of classifiers. The comparison with a traditional scalar optimization technique based on an AUC criterion shows promising results on UCI datasets. [ABSTRACT FROM AUTHOR]

As minimally invasive surgical techniques become widely known to patients, medical training systems based on virtual simulation are highly desired. These systems help surgeon trainees to acquire, practice and evaluate their surgical skills. A key component in a virtual training system is to simulate the dynamics that occur in surgical procedures. Tissue cutting, as a common phenomenon during surgery, has attracted many research efforts in computer simulation. In this paper, we propose an approach to endoscopic image cutting simulation which is based on both mass-spring model and Computational Geometry. In the cutting simulation model, the springs to be cut off are imagined into line segments. In the calculation of the elastic force on mass points, we have found that whether some adjacent springs of a mass point to be eliminated or not during a cutting is critical. If a spring intersects the cutting plane, we set the elastic force of this spring to zero. We adopted properties of cross product and related algorithms (the rapid exclusion test, the crossover test) in Computational Geometry to determine the springs that are intersected with the cutting plane. And then, we utilized the bilinear interpolation and OpenGL techniques to render the cutting procedure of the soft tissue. The experimental results show that our cutting simulation is effective and practical. [ABSTRACT FROM AUTHOR]

A new log-domain building block for log-domain filter design is proposed in this paper. This block realizes a positive impedance inverter (gyrator) by using the log-domain wave method. A simple procedure for log-domain filter development, using the proposed block, is outlined. This method results in circuits, which are simple in structure and very easy to design. An example of a second-order bandpass filter is given and its functionality is verified through simulations. [ABSTRACT FROM AUTHOR]

In this paper, the design of differential log-domain wave filters is outlined which is based on the log-domain wave technique. The differential configuration is achieved by introducing the differential log-domain wave equivalent. The resulting filters inherit the good characteristics of the wave active filters, are very modular and easy to design. The method is demonstrated by a design example and its validity is verified through simulations results. [ABSTRACT FROM AUTHOR]

This paper further investigates a basic issue that has received attention in the recent literature, namely, the robustness of complete stability of standard Cellular Neural Networks (CNNs) with respect to small perturbations of the nominal symmetric interconnections. More specifically, a class of third-order CNNs with a nominal symmetric interconnection matrix is considered, and the Harmonic Balance (HB) method is exploited for addressing the possible existence of period-doubling bifurcations, and complex dynamics, for small perturbations of the nominal interconnections. The main result is that there are indeed parameter sets close to symmetry for which period-doubling bifurcations are predicted by the HB method. Moreover, the predictions are found to be reliable and accurate by means of computer simulations. [ABSTRACT FROM AUTHOR]

Genetic Algorithm (GA) applications in analog design circuits play an important role with promising results. This paper introduces a proposed methodology based on the genetic algorithm and the symbolic representation to generate equivalent op-amp configurations for well-known filters. The proposed methodology is applied to the Tow-Thomas (TT) filter to generate 168 different configurations. Moreover, it is also applied on the KHN filter resulting in 30 equivalent circuits for each type. A part of the generated realizations is tested through simulations using PSPICE simulator and the simulation results determine the number of accepted circuits. A simulation comparison between the original filter configuration and some of the accepted configurations is done. Fortunately, a better performance compared to the original configuration is obtained from some generated circuits. [ABSTRACT FROM AUTHOR]

In this paper, a variable gain amplifier (VGA) designed in 130 nm CMOS technology is presented. The proposed amplifier is based on the bulk-driven (BD) design approach, which brings a possibility to operate with low supply voltage. Since the supply voltage of only 0.6 V is used for the amplifier to operate, there is no risk of latch-up event that usually represents the main drawback of the BD circuit systems. BD transistors are employed in the input differential stage, which makes it possible to operate in rail-to-rail input voltage range. Achieved simulation results indicate that gain of the proposed VGA can be varied in a wide scale, which together with the low supply voltage feature make the proposed amplifier useful for low-voltage and low-power applications. An additional circuit responsible for maintaining the linear-in-decibel gain dependency of the VGA is also addressed. The proposed circuit block avails arbitrary shaping of the curve characterizing the gain versus the controlling voltage dependency. [ABSTRACT FROM AUTHOR]

A novel method of nodal impedance calculation is presented in this paper. This method is capable of time-efficient calculation of arbitrary two-point complex impedance in an analog and mixed-signal circuit and could improve the development time of impedance-based tests both in DC and AC domain. A fault simulation methodology based on the proposed method is described in detail. Several experiments are provided that prove the time efficiency of the method. Experimental application showing the benefits of the method on a real circuit is provided as well. [ABSTRACT FROM AUTHOR]

It is well known that every sequential element may become metastable when provided with marginal inputs, such as input transitions occurring too close or input voltage not reaching a defined HI or LO level. In this case the sequential element requires extra time to decide which digital output level to finally present, which is perceived as an output delay. The amount of this delay depends on how close the element's state is to the balance point, at which the delay may, theoretically, become infinite. While metastability can be safely avoided within a closed timing domain, it cannot be completely ruled out at timing domain boundaries. Therefore it is important to quantify its effect. Traditionally this is done by means of a 'mean time between upsets' (MTBU) which gives the expected interval between two metastable upsets. The latter is defined as the event of latching the still undecided output of one sequential element by a subsequent one. However, such a definition only makes sense in a time-safe environment like a synchronous design. In this paper we will extend the scope to so-called value-safe environments, in which a sequential element can safely finalize its decision, since the subsequent one waits for completion before capturing its output. Here metastability is not a matter of 'failure' but a performance issue, and hence characterization by MTBU is not intuitive. Therefore we will put the focus on the delay aspect and derive a suitable model. This model extends existing approaches by also including the area of very weak metastability and thus providing complete coverage. We will show its validity through comparison with transistor-level simulation results for the most popular sequential elements in different implementations, point out its relation to the traditional MTBU model parameters, namely and , and show how to use it for calculating the performance penalty in a value-safe environment. [ABSTRACT FROM AUTHOR]

In this paper, a new grounded inductor simulator employing two current feedback operational amplifiers (CFOAs), three resistors and one grounded capacitor which is suitable for IC fabrication is proposed. Also, a new voltage-mode (VM) universal filter with three input and single output is given as application example of the grounded inductor simulator. The universal filter with low output impedance can be easily cascaded with other VM circuits. Both of the proposed circuits have the feature of improved low frequency performances, and can be easily constructed by two commercially available active devices such as AD844s. However, both inductor simulator and universal filter need a single passive component matching condition. Simulation and experimental test results are given to demonstrate the performance and workability of the proposed grounded inductor simulator and filter structure. [ABSTRACT FROM AUTHOR]

This paper describes the design of a novel cascode-grounded tunable active inductor and its application in an active band-pass filter (BPF) suitable for multi-band radio frequency (RF) front-end circuits. The proposed active inductor circuit uses feedback resistance to improve the equivalent inductance and the quality factor. The novelty of this work lies on the use of a few number of multi-finger transistors, which allows reducing strongly the power consumption and the silicon area. In other words, we demonstrate that the use of variable P-type Metal-Oxide-Semiconductor (PMOS) resistor and controllable current source have a good potential for wide tuning in terms of inductance value, quality factor and frequency operation. The RF BPF is realized using the proposed active inductor with suitable input and output buffer stages. The tuning of the center frequency for multi-band operation is achieved through control voltages. The designed active inductor and RF BPF have been implemented in a standard 0.13m Complementary Metal Oxide Semiconductor (CMOS) technology. The simulation results are compared between schematic and post-layout design for inductance value, quality factor, transmission coefficient S21 and noise. This design yields encouraging results: the inductance value can be tuned from 10.94 to 44.17nH with an optimal quality factor around 2,581. In addition, the center frequency of the BPF can be tuned between 2 and 4.84GHz with an average insertion loss of dB. Throughout this range, the noise figure is between 10.49 and 9.22dB with an input referred 1dB compression point of dBm and IIP3 of 7.36dBm. The filter occupies 25.43m of active area without pads and consumes between 2.38 and 2.84mW from a 1V supplying voltage. [ABSTRACT FROM AUTHOR]

Random numbers are highly used in applications like computer simulation, gambling, statistical sampling and cryptography. Only a high-entropy random source can produce a better quality of random data. In this paper, we work on the generation of high-quality random numbers based on cellular automata (CA). We propose three-dimensional (3D) CA to generate a random sequence. We also propose various enhancements to CA-based pseudorandom number generator (CA-PRNG) and discuss its five variants by using two-dimensional (2D) and 3D CA. We analyze the switching between 2D and 3D CA for the same sequence to achieve high-quality randomness. We provide the architectures, CA rules and the algorithms for all the proposed variants with respect to 2D and 3D cell structures. We have done a software implementation of all the proposed variants and tested their produced sequences by using the internationally accepted standard for random numbers known as DIEHARD. The analysis of our results is made as per the recommendations of ANSI standards. A very similar criteria are applied to compare all the methods. Based on our results we are able to find the best CA-PRNG for producing high-quality random sequence. [ABSTRACT FROM AUTHOR]

This paper presents two power models for an asynchronous processor, A8051. The first one is a pipeline accurate model which models power consumption at each pipeline stage. The other one is a micro-architectural model which models power consumption at micro-operation level. Then, we demonstrate the feasibility of the proposed approach on an A8051 processor case study. The experimental results based on applying the proposed pipeline-accurate and micro-architectural power models on an A8051 processor demonstrate that the proposed power models have high accuracy with simulation times much faster than the conventional low-level power simulator. It also shows similar results compared to the conventional power model for a synchronous processor. Even though the simulation speeds for the proposed power models are approximately 100-900 times faster than the low-level power simulator, the differences are less than 18% and 15%, respectively. Thus, the proposed power models can give a guide for SoC designers who want to integrate the asynchronous processor for low-power SoC design. [ABSTRACT FROM AUTHOR]