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First-order allpass filters are analog filters with a unit magnitude response, but they change the phase shift between input and output signals at various frequencies. This paper presents the transadmittance-mode first-order allpass filters based on the modified current-controlled current differencing transconductance amplifier (M-CCCDTA). The proposed filters utilize a single M-CCCDTA and a grounded capacitor with no external resistors, making them well suited for implementation in an integrated circuit. The gain and phase response of the proposed filters can be adjusted electronically and separately. Also, the high output impedance of the proposed filters at both the input voltage node and the output current node makes cascading easy without the need for buffer devices. A quadrature sinusoidal oscillator based on the proposed first-order allpass filter has been designed as an example of an application. The PSpice simulation and actual experiments are utilized to validate the functionality of the proposed filters. The simulation and experimental results are consistent with the idea of anticipation. [ABSTRACT FROM AUTHOR]

A simple circuit based on modified extra-X second-generation current conveyor (MEXCCII), which is capable of realizing the following grounded immittance functions: a lossless capacitor, a lossy capacitor, a lossy inductor and a lossy frequency-dependent negative conductance, is introduced in this paper. The circuit employs one MEXCCII and three passive components. The use of single active block makes the circuit structure simpler. No component's matching constraint is needed in the proposed circuit. The nonideal study of the proposed grounded immittance circuit is also included. The circuit's performance is examined using 0.18- μ m technology-based PSPICE simulations. Experimental results which are performed using off-the-shelf integrated circuits (ICs) and bread board are also included. The proposed circuit is negligibly affected by the temperature variation and process variation. A single pole high-pass filter as an application of the realized lossy capacitor and a band-pass filter as an application of the realized lossy inductor are also presented in this paper. The realized filters offer the feature of ease of cascadability. [ABSTRACT FROM AUTHOR]

The ancient Vedic mathematics is well known for quicker handy multiplications but its recognition as an integrated circuit core against existing hardware multipliers is not established. As optimized hardware implementation of binary multiplier is one of the prominent unsolved problems in computer architecture, this paper proposes efficient Urdhava Tiryakbhyam Vedic multiplier architecture and compares it with the set of hierarchical multiplication algorithms which generate multiplication result in a single clock cycle. Two innovative algorithms are proposed here, one with a compact structure and another for faster execution. Also, its optimized transistor level layout is designed and implemented. To maintain homogeneity for comparison, all the algorithms are programmed on a common HDL language platform and analyzed with the same tool and technology. Final results indicate that the proposed architecture delivers 15.5% less power delay product (PDP) compared to closest competitor algorithm. [ABSTRACT FROM AUTHOR]

In the analog and mixed-signal integrated circuits, voltage references that are independent of various factors such as temperature drift, noise, supply voltage, etc., and efficient in terms of power as well as area, are highly in demand to improve the efficiency of the overall circuits. Voltage references are one of those circuits that have applications in both high-power systems and low-power system-on-chip (SoC) designs for wireless connectivity like the internet of the things (IoT) or the internet of the medical things (IoMT). They are responsible for providing a stable bias or reference voltage. Thus, voltage reference influences directly or indirectly the performance of these systems. A comparative study between the techniques used in bandgap voltage references and CMOS voltage references, in terms of performance parameters such as line sensitivity, output noise, PSRR, temperature coefficient, etc., is presented in this paper so that we can choose the voltage references as per the applications and environment. [ABSTRACT FROM AUTHOR]

This paper suggests a new operational transconductance amplifier (OTA) based electronically tunable transimpedance-mode first-order universal filter (FOUF). The suggested FOUF produces all-pass (AP), high-pass (HP) and low-pass (LP) filter responses simultaneously. It employs three OTAs, two grounded resistors and only one grounded capacitor. Owing to use of grounded passive elements, the suggested FOUF is suitable for integrated circuit implementation. It operates at low power supply voltages. Additionally, the resonance frequency of the suggested AP filter can be adjusted in a wide frequency range. However, the suggested FOUF consists of only one matching condition. Moreover, a sinusoidal quadrature oscillator (QO) application that is derived from the suggested FOUF topology is given. The suggested FOUF and its QO application are simulated by using 0.18- μ m TSMC technology parameters in the SPICE program to validate the presented theory. Finally, an experimental test is performed to demonstrate workability of the suggested AP filter. [ABSTRACT FROM AUTHOR]

Full adders are a core component and play an essential role in the design of contemporary very-large-scale integration (VLSI) integrated circuits. Low-power, high-speed adder design has been the subject of numerous different sorts of research. The never-ending process is still in progress. The saturation point for MOS-based VLSI circuit design has been reached. As a consequence, many additional issues arise when MOS devices are scaled down to the nanoscale range, including an increase in leakage power and a vulnerability to PVT variation. Hence, MOSFET alternatives have been looked after by VLSI industries. Future nanoscale VLSI circuits would benefit greatly from the use of FINFETs in place of MOS transistors. In this paper, two diode-connected transistors-based low power, high speed, and low-power–delay product (PDP) adiabatic logic full adders are proposed using 7 nm technology. DCT TSAA-I, DCT TSAA-II, DCT TCAA-I, and DCT TCAA-II are the names of the proposed structures. Power, speed, and power–delay product (PDP) performance of the proposed adders are compared with those of traditional full adders. According to the simulation outcomes, the proposed adder architectures offer the least PDP in comparison to the adders taken into consideration. On power and delay, the impact of changing variables like temperature, supply voltage, load capacitance, and frequency is seen. A 7 nm FINFET model has been used in the simulations, which were conducted using the Hspice simulation tool. [ABSTRACT FROM AUTHOR]

Tunability of correlated color temperature (CCT) and dimmability are the two major sought after features of functional solid-state lighting. This paper presents a low-cost, efficient, single-inductor-dual-output buck driver that facilitates CCT-control and dimming of a light emitting diode (LED) module composed of cool-white and warm-white chips. The proposed driver is designed based on two familiar integrated circuits (ICs), namely LM2596 and NE556. LM2596 serves as the main switching regulator and amplitude modulation (AM) controller whereas NE556 serves as the constant-frequency, dual-output pulse-width-modulation (PWM) controller. The exponential model of LED is exploited for improved estimation of the design parameters of the LED module and the driver circuit. The developed driver prototype is tested for its electrical, photometric, and colorimetric performances. The driver offers a full-load efficiency of about 90% for a 12-W test LED module. Under different operating modes, the LED system can produce warm, cool, or neutral white light and at the same time, the produced illuminance can be varied over a wide range. Moreover, the light flicker is imperceptible since the PWM frequency is set according to IEEE-1789 guideline. [ABSTRACT FROM AUTHOR]

Side-channel attacks (SCAs) are powerful noninvasive attacks that can be used for leaking the secret key of integrated circuits (ICs). Numerous countermeasures were proposed to elevate the security level of ICs against SCAs. Unfortunately, it is quite inconvenient to predict the security levels of these countermeasures since no solid mathematical model exists in the literature. In this paper, neural network (NN)-based entropy is proposed to model the resilience of a system against SCAs. The NN-based entropy model well links the side-channel leakages and probabilities with the neurons and weights of NNs, respectively. In such a circumstance, the NN-based entropy can be used for modeling the robustness of countermeasures since a one-to-one relationship is established between the NN-based entropy and the measurement-to-disclose (MTD) enhancement ratio related with the countermeasures. As demonstrated in the result, the proposed NN-based entropy metric shows 100% consistency with the MTD enhancement ratio if multiple SCA countermeasures are employed into a system. [ABSTRACT FROM AUTHOR]

As the feature sizes of integrated circuits are reduced to the nanometer scale, the total soft error rate (SER) in memory and the proportion of multiple bit upsets (MBUs) are significantly increasing. In order to ensure the information reliability, many error correction codes with strong error correction ability were proposed, such as Reed–Somolon (RS) code and Bose–Chaudhuri–Hocquenghem (BCH) code. However, these error correction codes have limited error correction capability, high algorithm complexity and large data redundancy. In this paper, a novel fault tolerance method for locating and correcting multiple bit errors in memory is proposed based on data similarity. The proposed method uses the inner product as the metric to analyze the similarity of the pre-protected data from the vertical and horizontal dimensions, respectively, and to construct the model of error location and correction. This method performs encoding and decoding in units of blocks and detecting and correcting in units of words, so it can correct any number of bits in a corrupted word with low redundancy overhead. Finally, irradiation tests were conducted on a commercial SRAM, and the feasibility of the proposed method is verified by using heavy ion 8 6 Kr 2 6 + as irradiation source. [ABSTRACT FROM AUTHOR]

Improved speed, reduced delay, reduced size and reduced power are the most important requirements of integrated circuits. The carry select adder (CSA) is one of the most important adders in most data processors for performing arithmetic operations. The speed of parallel adders can be enhanced CSA, which widens the area to speed and eliminates propagation delays. The major problem faced in CSA is inefficient area due to the usage of multiple pairs of Ripple carry adders (RCAs) for generating the sums and carry. This research paper proposes the modified 32-bit square root carry select adder (MSCSLA) to improve the direct digital synthesizer's performance (DDS). DDS plays an effective role in the digital system due to its ability of broad frequency generation. Phase accumulator is the main component in the DDS synthesizer, where the speed of the adder is enhanced through MSCSLA. The general square root CSA still consumes more power due to the assembly of more RCAs. Hence, in the proposed approach, certain sets of RCAs are replaced with BEC1 (Binary to excess 1 convertor) to improve the speed and reduce the delay of the adder. Finally, the continuous sinusoidal waveform is attained by attenuating the high-frequency components by adopting a low pass filter. The entire structure of DDS is designed using Xilinx Verilog coding. The Simulation result shows better outcomes in terms of area, delay, power, and high performance in the DDS synthesizer compared to the existing CSAs. When compared to the existing adders, the area occupied by the proposed MSCSLA model is attained to be 636 μ m2, the power is achieved as 50.125 μ W and delay is attained to be 1.280 ns, which are comparatively less. When comparing delay and maximum frequency with the existing techniques, the proposed model obtained minimum delay and maximum frequency. The overall power consumption by the proposed model is also attained to be lower than the existing techniques. [ABSTRACT FROM AUTHOR]

In this paper, Pseudo-Boolean Satisfiability (PB-SAT)-based congestion reduction and overflow minimization techniques are introduced for constructing congestion-aware rectilinear Steiner trees for global routing in IC design. Since congestion in different routing channels is a big issue in routing nets, various congestion minimization approaches have been proposed by many researchers. However, the increasing complexity of integrated circuits and the reduction of their size make the congestion problem more complicated. The proposed method can produce a congestion-free routing solution by generating a suitable rectilinear Steiner tree for circuit nets. To reduce the complexity of the problem, the nets are solved individually using a Minimum Bounding Box (MBB)-based heuristic technique. The algorithm is validated by utilizing the well-known ISPD 98 global routing benchmarks. Experimental results prove that the methodology is capable of routing most of the nets within the given routing capacity satisfying all the routing parameters. The results also show that the algorithm can produce congestion-aware Steiner trees efficiently within a nominal time-bound. [ABSTRACT FROM AUTHOR]

The design complexity and outsourcing trend of modern integrated circuits (ICs) have increased the chance for adversaries to implant hardware Trojans (HTs) in the development process. To effectively defend against this hardware-based security threat, many solutions have been reported in the literature, including dynamic and static techniques. However, there is still a lack of methods that can simultaneously detect and diagnose HT circuits with high accuracy and low time complexity. Therefore, to overcome these limitations, this paper presents an HT detection and diagnosis method for gate-level netlists (GLNs) based on different machine learning (ML) algorithms. Given a GLN, the proposed method first partitions it into several circuit cones and extracts seven HT-related features from each cone. Then, we repeat this process for the sample GLN to construct a dataset for the next step. After that, we use K-Nearest Neighbor (KNN), Decision Tree (DT) and Naive Bayes (NB) to classify all circuit cones of the target GLN. Finally, we determine whether each circuit cone is HT-implanted through the label, completing the HT detection and diagnosis for target GLN. We have applied our method to 11 GLNs from ISCAS'85 and ISCAS'89 benchmark suites. As shown in experimental results of the three ML algorithms used in our method: (1) NB costs shortest time and achieves the highest average true positive rate (ATPR) of 100%; (2) DT costs longest time but achieve the highest average true negative rate (ATNR) of 98.61%; (3) Compared to NB and DT, KNN costs a slightly longer time than NB but the ATPR and ATNR values are approximately close to DT. Moreover, it can also report the possible implantation location of a Trojan instance according to the detecting results. [ABSTRACT FROM AUTHOR]

This paper presents a scalable Fully-digital differential analog voltage comparator designed in Semi-Conductor Laboratory (SCL) 180 nm complementary metal-oxide semiconductor technology. The proposed design is based on a digital design approach and is easily configurable to lower technology nodes. This design methodology makes the circuit less sensitive to process variations and takes fewer design efforts suitable for Systems-on-a-Chips (SOCs) application. The proposed circuit is designed and simulated in Cadence Virtuoso Analog Design Environment at the supply voltage ranging from 1 V to 1.8 V. The fully-digital analog voltage comparator has been synthesized using Synopsys Design Vision and auto-placed & auto-routed using Synopsys IC Compiler. This proposed comparator has a resolution of up to 7-bit at a supply voltage of 1.8 V and a worst-case operating frequency of about 750 MHz at the TT corner. The obtained value of the offset voltage and delay is 0.55 mV and 0.72 ns, respectively. The simulated results have shown that the power dissipation of the proposed scalable analog voltage comparator is 1 5 0 μ W @ 1 V and 3 1 2 μ W @ 1. 8 V supply voltage, respectively. Also, the RC extracted post-layout simulations have been implemented to verify the performance, which does not affect the results much. [ABSTRACT FROM AUTHOR]

In this research paper, a simple design of an ultra-wideband (UWB) multi-input multi-output (MIMO) antenna with low envelope correlation coefficient (ECC), high isolation, enhanced gain, radiation efficiency and reconfigurable band notching functionality is proposed. Two symmetrical slots are carefully integrated into the partial ground plane of the conventional monopole to provide a notched band at 5.8 GHz for the WLAN system. This notching method is simple and does not endure negative effect performance or any design complexity. The notched band is then controlled using PIN diodes. A complete biasing circuit is integrated on the same partial ground plane to bias the PIN diodes in forward and reverse directions. To reduce the complexity of the design that may be increased due to the reconfiguration circuit, isolation enhancement is accomplished by orthogonal placement of the elements rather than using any additional decoupling structures. A prototype of the MIMO UWB structure is fabricated and its performance parameters are experimentally tested. The captivating agreement between simulation and measurement demonstrates that the proposed antenna system is a good candidate for UWB applications with an operating band extending from 3 to 11 GHz, notch-band reconfiguration freedom, and isolation of more than 20 dB. [ABSTRACT FROM AUTHOR]

This paper introduces the experimental results obtained after processing an electrocardiographic signal by a full-custom, low-complexity, Sigma-Delta Modulator integrated circuit, designed and fabricated using the C5N CMOS technology available through MOSIS. By exploiting a large oversampling ratio, it was possible to obtain an effective number of bits equal to 11 at the proposed single-bit modulator's output. The resulting bitstream was captured with a logic-state analyzer and processed offline. After decimation and digital filtering, the electrocardiographic signal was reconstructed and plotted in the time domain. Commonly referred quality metrics over the retrieved signal were calculated. A total signal-to-noise and distortion ratio, superior to 66 dB, was achieved by analyzing the entire system. The proposed approach shows the feasibility of processing electrocardiographic signals using low-cost and straightforward CMOS technology circuits. Since the proposed converter uses a single voltage supply of 1.5 V, exhibits a power consumption of 38 μ W, and uses a silicon area of 0.052 mm2, it is suitable for single battery-operated systems on a chip. [ABSTRACT FROM AUTHOR]

Instead of boost/buck conversion processor, power supplies single-phase SEPIC conversion processor becomes widely used in computer motherboards and other integrated circuits as well as in photovoltaic solar cell systems. However, multiplier and multiphase interleaved conversion processors become preferred due to their identical advantages over traditional single-phase SEPIC from the possibility of current stress or ripple reduction in active or passive elements perspectives. This paper presents a new class of a double-phase SEPIC conversion processor that has a modified structure in order to maximize the dynamic performance of the previously mentioned topologies of SEPIC. An analytical comparative study was conducted for the multiplier and modified double-phase interleaved SEPIC processor with magnetically uncoupled inductive reactors to show the benefits of this new class of the double-phase connection of SEPIC when compared with the traditional and the multiplier connection. The proposed topologies of multiplier and modified SEPIC are simulated using the Simulink MATLAB, Excel and Simplorer 7. The experimental results and analysis have shown the improved characteristics of the proposed new class of the double-phase SEPIC, low harmonic distortion, sacredness to component tolerance, relief in overall current fluctuation reduction complexity, high power efficiency and a very high voltage gain. [ABSTRACT FROM AUTHOR]

A simple analog multiplier circuit employing one current-mode active building block (ABB) and two n-channel metal-oxide semiconductor (NMOS) transistors is presented in this paper. The used ABB is extra-X second generation current conveyor. The used NMOS transistors are operated in triode region. The circuit has appropriate impedance level at the input and output terminals. Some other key features of the proposed circuit are as follows: suitable to integrated circuit fabrication, good dynamic range and low operating power supplies. The nonideal effects of extra-X second generation current conveyor on the proposed circuit are studied. Additionally, the layout of the proposed circuit is developed using Cadence VIRTUOSO Analog Design Environment with gpdk 0.18 µm technology and post layout simulation results are given to verify the theoretical aspects. [ABSTRACT FROM AUTHOR]

Compared with the traditional copper material, carbon nanotube (CNT) has been identified as one of the most potential materials for interconnects in nanometer regime due to higher performance. However, for CNT interconnects, most of the researches focus on voltage-mode signaling (VMS) scheme, whereas current-mode signaling scheme (CMS) is meagerly investigated. The paper proposes an equivalent circuit model of two-line coupled single-walled CNT bundle interconnects, which is applicable to both CMS and VMS schemes. In addition, the model takes capacitive and inductive crosstalk into consideration. In CMS and VMS interconnects, the performance of victim line in the time domain is studied according to decoupling technique and ABCD parameter matrix approach at local, intermediate and global levels, respectively. The influence of aggressor line on victim line is discussed because of dynamic crosstalk and functional crosstalk. Furthermore, the paper comparatively analyzes the performance advantage between CMS interconnects and VMS interconnects. The results show that CMS interconnects have lower output voltage swing and propagation delay than VMS interconnects in the same condition. In terms of noise, CMS scheme has higher advantage for lesser noise peak, noise width and noise area. Moreover, it is found that the results obtained by ABCD parameter matrix approach have great consistency with Advanced Design System simulation results. [ABSTRACT FROM AUTHOR]

This paper deals with the experimental realization of square/triangular wave generator using commercially available ICs. A prototype of extra-X second generation current conveyor and five passive components are used in the experimental setup. The proposed generator provides both square and triangular waveforms simultaneously in voltage-mode. The circuit enjoys the feature of independent controllability of oscillation frequency via grounded resistor/grounded capacitor. A range of oscillation frequency from 3 Hz to 250 Hz is easily achieved via variation in one of the grounded resistors for a fixed value of capacitor. Moreover, a range of oscillation frequency from 19.8 Hz to 19.2 kHz can be achieved through the variation in grounded capacitor. The experimental results show that the performance of the proposed generator is good at operating frequency as low as at 19.8 Hz and as high as 19.2 kHz. Therefore, the proposed circuit can operate well from extra-low-frequency range to very-low-frequency range. Furthermore, the maximum nonlinearity of oscillation frequency is found to be 4% only. [ABSTRACT FROM AUTHOR]

This paper details an application-specific integrated circuit (ASIC) with an array of switched-resistor-based memristors (resistor with memory) and integrate & fire (I & F) neuron circuits for the development of memristor-based pattern recognition. Since real memristors are not commercially available, a compact memristor emulator is needed for device study. The designed ASIC has five memristor emulators with one having a conductance range from 4.88ns to 4.99s (200k to 204.8M) and other four having conductance ranging from 195ns to 190s (5.2k to 5.12M). Signal processing has been planned to be off-chip to get the freedom of programmability of a wide range of memristive behavior. This paper introduces the memristor emulator and the realization of synapse functionalities used in neuromorphic circuits such as long term potentiation (LTP), Long Term depression (LTD) and synaptic plasticity. The ASIC has two I & F neuron circuits which are intended to be used in conjunction with memristors in a multiple chip network for pattern recognition. This paper explains the memristor emulator, I & F neuron circuit and a respective neuromorphic system for pattern recognition simulated in LTspice. The ASIC has been fabricated in AMS 350nm process. [ABSTRACT FROM AUTHOR]

A novel electronically adjustable square/triangular waveform generator has been introduced in this paper. The proposed circuit employs one active element, the multi-output current-controlled current conveyor transconductance amplifier, and one passive component grounded capacitor only. The resistorless realization of the presented generator provides a good advantage in terms of integrated circuit fabrication. In the offered circuit, the frequency and amplitude of the output square wave are electronically tunable by means of relevant bias currents. Additionally, the upper and lower threshold levels are electronically controllable by the respective bias current. On the contrary, electronically adjusting of the duty cycle of output waveform is possible via the external DC current. The generator circuit is simulated with TSMC 0.18 μ m technology parameters and SPICE. Moreover, the introduced circuit is implemented by using commercially available active devices and thus it is also verified experimentally. [ABSTRACT FROM AUTHOR]

This paper introduces an electronically tunable mixed-mode universal biquad filter configuration employing four single output operational transconductance amplifiers (OTAs), one dual output OTA and two grounded capacitors (GCs) (ideal for integrated circuit implementation and absorbing shunt parasitic capacitances). The presented structure can realize all second-order filter functions, namely, low pass (LP), high pass (HP), band pass (BP), band reject (BR) and all pass (AP) responses in voltage mode (VM), current mode (CM), transresistance mode (TRM) and transconductance mode (TCM) using appropriate selection(s) of input signals. The cut-off frequency ( f o) and bandwidth (BW) of the realized filters can be tuned orthogonally through the transconductance (by varying the bias currents) of the OTAs. The proposed biquad configuration enjoys low active and passive sensitivities. The workability of this multifunctional biquad filter topology has been confirmed through simulations using MATLAB and Analog Design Environment (ADE) spectre tool provided by Cadence Virtuoso, using 0.18 μ m CMOS process parameter. The post-layout simulations have also been carried out to validate the theory. [ABSTRACT FROM AUTHOR]

This paper deals with the realization of current-mode first-order universal filter based on multiple output second generation current conveyor (MO-CCII). Two MO-CCIIs, one resistor and one capacitor are used in the circuit realization. The proposed work includes additional features such as ease of cascadability, easily implementable in modern integrated circuit technology and no requirement of passive components matching condition. The additional beauty of the proposed filter structure is that all three responses can also be realized by interchanging the positions of passive components as well. Moreover, a possible transformation of the proposed current-mode type universal filter into a voltage-mode type universal filter using network transpose method is also explored. The possibility of mode transformation further expands the scope of proposed idea. The theoretical aspects are verified using cadence VIRTUOSO simulation results. [ABSTRACT FROM AUTHOR]

Nowadays, Hardware Trojan threats have become inevitable due to the growing complexities of Integrated Circuits (ICs) as well as the current trend of Intellectual Property (IP)-based hardware designs. An adversary can insert a Hardware Trojan during any of its life cycle phases — the design, fabrication or even at manufacturing phase. Once a Trojan is inserted into a system, it can cause an unwanted modification to system functionality which may degrade system performance or sometimes Trojans are implanted with the target to leak secret information. Once Trojans are implanted, they are hard to detect and impossible to remove from the system as they are already fabricated into the chip. In this paper, we propose three stealthy Trojan models which affect the coherence mechanism of Chip Multiprocessors' (CMPs) cache system by arbitrarily modifying the cache block state which in turn may leave the cache line states as incoherent. We have evaluated the payload of such modeled Trojans and proposed a cellular automaton (CA)-based solution for detection of such Trojans. [ABSTRACT FROM AUTHOR]

In this paper, a new active element namely Dual-X current conveyor differential input transconductance amplifier (DXCCDITA) is proposed. The DXCCDITA is utilized in designing four minimum component fully cascadable all pass filter (APF) structures. The designed all pass filters require only single active element and one/two passive elements for realization thus making them a minimum component implementation. Two among the four presented all pass structures require only a single capacitor for implementation. A scheme for realizing nth order all pass filter is also suggested and a fourth order voltage mode (VM) filter is developed from the proposed scheme. The effect of non-idealities on the proposed all pass filters is also studied. A simple oscillator is also developed using one of the all pass filter structure. The oscillator required only one DXCCDITA, two capacitors and one resistor for implementation. The DXCCDITA is implemented in 0.35 μ m TSMC CMOS technology parameters and tested in Tanner EDA. Sufficient numbers of simulations are provided to establish the functionality of all pass structures. The experimental results using commercially available integrated circuits (ICs) are also provided. [ABSTRACT FROM AUTHOR]

Hardware Trojan has become a major threat to the security and trustworthiness of integrated circuit (IC) employed in critical applications. Due to the presence of process variations and measurement noises, all existing side-channel Trojan detection approaches suffer from low detection sensitivity or even false negatives with increasing circuit size and decreasing Trojan size. In this paper, we propose a statistical test generation approach based on mutation analysis, which generates a set of test vectors aiming at activating the hardware Trojan inserted into the low activity nodes. Such approach not only enhances the controllability of low activity nodes through increasing the switching activity of it, but also improves the observability by propagating the artificial designed errors introduced by the mutant to the outputs. Simulation results of a set of ISCAS'85 and ISCAS'89 benchmark circuits show that the proposed approach improves the activity of low activity nodes 463% at most compared with the Multiple Excitation of Rare Occurrence (MERO) approach and increases the Trojan coverage with 84.08% reduction in test length. Moreover, the test vectors generated by the proposed approach and the MERO approach, respectively, are exerted to the circuit under test. Experimental results demonstrate that the Mahalanobis distance margin of the proposed approach is much greater than the MERO approach, and thus provide a comparable robustness with decreasing Trojan size. [ABSTRACT FROM AUTHOR]

The complexity of any integrated circuit pushes the researchers to optimize the various parameters in the design process. Usually, the Nondeterministic Polynomial problems in the design process of Very Large Scale Integration (VLSI) are considered as a Single Objective Optimization Problem (SOOP). However, due to the increasing demand for the multi-criterion optimization, researchers delve up on Multi-Objective Optimization methodologies to solve a problem with multiple objectives. Moreover, it is evident from the literature that biologically inspired algorithm works very well in optimizing a Multi-Objective Optimization Problem (MOOP). This paper proposes a new Lion's pride inspired algorithm to solve any MOOP. The methodologies mimic the traits of a Lion which always strives to become the Pride Lion. The Algorithm was tested with VLSI floorplanning problem wherein the area and dead space are the objectives. The algorithm was also tested with several standard test problems. The tabulated results justify the ruggedness of the proposed algorithm in solving any MOOP. [ABSTRACT FROM AUTHOR]

From the nodal admittance matrix (NAM) expansion approach and 16 pathological patterns of the voltage differencing transconductance amplifier (VDTA), two different categories, namely sort A and sort B, of the quadrature sine-wave oscillators-employed VDTAs and grounded capacitors in the current mode are synthesized. In all, four quadrature sine-wave oscillators with two sets of quadrature current outputs are attained. Because canonic number is used for component quantity, the oscillators are appropriate to integrated circuit realization and also provide electronic, linear, and orthogonal adjustments between the oscillation criterion and frequency by means of tuning bias currents of the VDTAs. The paper-and-pencil and simulation analyses as well as experimental analysis have been carried out to check the utilized synthesis approach. [ABSTRACT FROM AUTHOR]

The characterization of interconnect delay metrics in terms of process variations is an important but complicated task for statistical timing analysis in today's integrated circuits (ICs). This paper presents a stochastic delay characterization framework for multicoupled interconnects in the presence of process variation. The proposed method starts with deriving the stochastic nodal equations for the RLC network that models multicoupled interconnects. By employing polynomial chaos (PC) expansion, a nonsampling-based stochastic prediction method, we further represent the voltage responses of network nodes as a series of orthogonal polynomials of random variables. During the expansion procedure, we use an adaptive approximation algorithm to reduce the number of required sampling points. We then use a stochastic collocation method to estimate the coefficients in the PC expansion model. With the voltage response determined as an expression of a multi-dimensional polynomial of random variables, the stochastic properties of the delay of multicoupled interconnects can be predicted. The proposed method not only takes into account the strong correlations among process variations, but also extracts an explicit delay representation for multicoupled interconnects in terms of process variations. Experimental results demonstrate that the delay characteristics predicted by the proposed method match well with the results by the brute-force Monte-Carlo method. Moreover, a significant speedup over the Monte-Carlo method has been achieved by the proposed delay characterization framework. [ABSTRACT FROM AUTHOR]

Simulation of inductors has been a very popular area of analog circuit research and the alternative choice for realizing inductor-based circuits in integrated circuits. In this paper, lossless, grounded and floating inductor topologies using current-controlled-current-feedback amplifier (CC-CFA) with single grounded capacitor are presented. The proposed topologies can be tuned electronically by changing the biasing current of the CC-CFA. Two topologies for grounded inductor simulator employ two CC-CFA and one grounded capacitor. One topology for floating inductor simulator employs three CC-CFA and one grounded capacitor. The performance of the grounded and floating inductor simulators are demonstrated on resonant circuits. The theoretical analysis is verified by PSPICE simulation results. [ABSTRACT FROM AUTHOR]

Process variations have continuously posed significant challenges to the performance and yield of integrated circuits (ICs). The performance modeling and robust optimization method considering process variations has become an important research task in today's IC design. Aiming at solving the problems of strong nonlinearity and high-dimensional problems in circuit design, this paper proposes a general robust optimization method for ICs by geometric programming. This method first employs regularization sparse models to model a specific performance metric as a posynomial function in terms of design parameters, in order to reduce parameter space dimensionality and to accurately capture the nonlinear relationship between performance perturbations and process variations. Based on the posynomial performance models, this method further uses an uncertainty set to represent the uncertainties of process variations, and formulates the problem of robust optimization under process variations as a general geometric programming model that can be efficiently solved. Experimental results demonstrate that, the proposed method not only enhances the accuracy and efficiency of circuit performance modeling, but also improves the performance yield significantly compared with traditional circuit design methods. [ABSTRACT FROM AUTHOR]

This paper presents a new electronically tunable voltage-mode universal filter with four-input one-output employing six simple operational transconductance amplifiers (OTAs), two grounded capacitors and two MOS resistors. The use of grounded passive components is beneficial for integrated circuit implementation. The proposed filter can realize low-pass, band-pass, high-pass, band-stop and all-pass filtering functions without active and passive component-matching conditions and inverting-type input signals requirements. The natural frequency and quality factor can be tuned independently and electronically by adjusting the bias currents. The voltage-mode filter offers the features of high-input impedance and low active and passive sensitivities. The characteristics of the proposed universal filter are verified using PSPICE simulators through 0.35 μ m CMOS process. Experimental results are used to confirm the workability of proposed circuit through LM13600 commercially available OTAs. Also a digitally programmable filter is shown to confirm the advantage of multiple-input universal filter. [ABSTRACT FROM AUTHOR]

Network-on-chip (NoC) mapping algorithms significantly affect NoC system performance in terms of communication cost and energy consumption. For a specific application represented by a task graph, this paper proposes an energy-efficient mapping algorithm that searches for the mapping decision with best communication locality and therefore lowest energy consumption. To this end, we formulate the concerned mapping problem as an optimization model, and propose an effective meta-heuristic algorithm to solve the formulated optimization model. During the mapping procedure, we employ a simulation-free, communication probability-based energy model to evaluate the quality of each candidate mapping. By iteratively updating the best explored mapping decision using a meta-heuristic search strategy, the mapping procedure can eventually identify an mapping decision with optimal energy efficiency in the search space. The proposed mapping algorithm has been verified on NoC systems of different sizes using a variety of benchmark applications. Simulation results demonstrate that the mapping decision produced by this algorithm achieves an up to 23% energy reduction compared with the traditional round-robin strategy. [ABSTRACT FROM AUTHOR]

In this paper, a half-elliptical disc ultra-wideband (UWB) monopole antenna integrated with a reconfigurable rectangular slot antenna is presented. It consists of a half-elliptical disc radiator to operate in the UWB mode whereas the etched rectangular slot on the half-elliptical patch is designed to operate as a reconfigurable narrowband slot antenna which is fed through a microstrip line from the back side of the patch. Both the antennas are placed in such a way that they are isolated to each other. Frequency reconfigurability has been achieved by inserting three lumped elements (two PIN diodes and a varactor diode) in the slot. An approximate transmission line model of the proposed slot antenna is derived to calculate the proper positioning of the diodes, and the design has been verified through numerical simulations. The simple compact proposed antenna covers a wide frequency range from 0.75 to 12 GHz. Additionally, a wide tuning range from 0.8 to 2.9 GHz (with the frequency ratio of 3.625:1) has been achieved. This compact integrated antenna is a good choice to be implemented in Cognitive Radio (CR) devices. [ABSTRACT FROM AUTHOR]

As the only nonlinear operation, masked S-box is the core to resist differential power attack (DPA) for advanced encryption standard (AES) cipher chips. In order to suit for the resource-constrained applications, a compact masked S-box based on composite field is proposed in this paper. Firstly, the architecture of masked S-box is designed with composite field masking method. Secondly, four masked S-boxes based on GF ((24)2), which are based on four basis methods with the optimal coefficient and the corresponding optimal root, are implemented and optimized by the delay-aware common subexpression elimination (DACSE) algorithm. Finally, experimental results show that, while maintaining the DPA-resistance performance, our best masked S-box achieves better area performance with the fastest speed compared with the existing works. Therefore, our masked S-box is suitable for resource-constrained applications with fast speed requirements. [ABSTRACT FROM AUTHOR]

This paper presents a low-power low-noise instrumentation amplifier (IA) for bio-potential recording. The proposed IA is based on a novel Gm-RSC structure, whose gain is determined by the transconductance (Gm) and the equivalent resistance (R) of the switched-capacitor (SC) load. The transconductance amplifier stage is based on the current-reuse telescope topology to achieve low noise at low-power dissipation. A resistor-controlled oscillator is designed to generate desirable operational frequency for SC load and to continuously tune the mid-band gain of the IA for different biomedical applications. Measurement results show that the input referred noise of the proposed IA is about 1.27μVRMS (BW=150Hz) and the noise efficiency factor is 3.3. The range of tunable gain is from 28 to 40dB. The common mode rejection ratio and power supply rejection ratio at 50Hz are 72 and 78dB, respectively. The IA consumes only 660nA current at 1.2V supply and the active area of the IA is only 0.035mm2. [ABSTRACT FROM AUTHOR]

Noise immunity is an important concern in deep nano-scale technologies, especially for high fan-in gates. In this paper, a new domino circuit technique is proposed by which the noise immunity of high fan-in gates increases while the power consumption reduces. The proposed technique is based on the comparison of two currents, which vary with respect to the voltage across the pull-down network (PDN). By comparing these currents, the voltage level of the dynamic node is pulled up or pulled down depending on the input voltages. Using this technique, the voltage swing on the PDN can be decreased to reduce the power consumption. Moreover, a diode-connected NMOS transistor is added in series with the PDN in the proposed technique. This will result in reducing the subthreshold leakage current due to the stacking effect and, as a result, the noise immunity will improve. To demonstrate the efficacy of the proposed domino design over the conventional techniques, high fan-in gates are designed and compared in 90nm CMOS technology. Simulation results exhibit at least 1.87X noise immunity improvement and 20% power consumption reduction in comparison to the standard footless domino (SFLD) circuits at the same delay. [ABSTRACT FROM AUTHOR]

Hardware Trojan Horses (HTHs) are malicious modifications inserted in Integrated Circuit during fabrication steps. The HTHs are very small and can cause damages in circuit function. They cannot be detected by conventional testing methods. Due to dangerous effects of them, Hardware Trojan Detection has become a major concern in hardware security. In this paper, a new HTH detection method is presented based on side-channel analysis that uses path delay measurement. In this method, we find and observe the paths that Trojans have most effect on them. Most of the previous works add some structures to the circuit and need a large overhead cost. But, in our method, there is no modification in the circuit and we can use it for testing the circuits received after fabrication. The proposed method is evaluated with Xilinx FPGA over a number of test circuits. The results show that measuring the delays on 20 paths with an accuracy of 0.01ns can detect more than 80% of Trojans. [ABSTRACT FROM AUTHOR]

As the performing ability of a silicon chip relies on the power supply voltage, it must be configured using genuine power and ground bond pads for mitigating power and ground noise (PGN), which is directly boosted by the increasing peaks of instantaneous current and current ramp . To address the same, a novel and compact clock gating (CG) scheme is unveiled in this paper to effectively control the peak of and , thereby subduing PGN. The new CG arrangement is simulated for 90nm Predictive Technology Model (PTM90), where it is observed that the scheme reduces 88.80% of and 84.19% of average in comparison to its no gating counterpart along with a reduction of 80.14% in average power dissipation. These results are found to be more prominent when the proposed circuit configuration is tested in 90nm Generic Process Design Kit (GPDK90), proclaiming 88.75% and 84.34% reduction in average and average power, respectively, to illustrate its capability of truncating PGN in silicon chips. [ABSTRACT FROM AUTHOR]

This paper proposes designing a precision rectification circuit by using a single operational transresistance amplifier (OTRA). The proposed circuit is a switch-controllable OTRA-based full-phase operation precision half-wave rectifier, which can rectify an input signal to yield four-phase half-wave rectified output signals. Compared with existing designs, the advantage of the proposed circuit is that all of the possible rectified outputs of a half-wave rectifier can be obtained in one configuration. This paper first reviews previously reported half-wave precision rectifiers consisting of various active devices and the proposed OTRA-based precision half-wave rectifier; subsequently, an analysis of non-ideal effects and design considerations are presented. Computer simulations of the proposed circuit were conducted for verifying the feasibility of the circuit by using the Taiwan Semiconductor Manufacturing Company (TSMC) 0.35-m CMOS process technology. For practical circuit measurements, a prototype circuit was implemented, and commercially integrated circuits (AD844ANs) and discrete passive components were used to conduct experimental tests. The simulation and experimental results exhibited satisfactory agreement with those of theoretical analyses. [ABSTRACT FROM AUTHOR]

Reduced part count multilevel inverters (RPC-MLIs), an emerging technology for grid interfacing applications of renewable energy sources. RPC-MLIs overcome the limitations of conventional two-level and classical multilevel inverters (NPC, FC and CHB) by the use of reduced part counts for generation of same number of levels in the output. Focus of this paper is on to present review of the RPC-MLIs for researchers and engineers and classification of all the topologies. RPC-MLIs are compared considering its circuit complexity and performance. The comparison exposes advantages and disadvantages of topologies, as well as a wide spectrum for future research. This paper also draws the most potential topology in the field of grid integrated applications. Promising topology is simulated here under the same load and input source condition using real time simulator. [ABSTRACT FROM AUTHOR]

It is important in digital signal processing (DSP) architectures to minimize the silicon area of the integrated circuits. This can be achieved by reducing the number of functional units such as adders and multipliers. In literature, folding technique is used to reduce the functional units by executing multiple algorithm operations on a single functional unit. Register minimization techniques are used to reduce the number of registers in a folded architecture. Retiming is a technique that needs to be performed before applying folding. In this paper, retiming is performed based on nature inspired evolutionary computation method. This technique generates the database of solutions from which best solution can be picked for folding further. As a part of this work, an efficient folded noise removal audio filter prototype is designed as an application example using evolutionary computation-based retiming and folding with register minimization. Folding technique will however increase the number of registers while multiplexing datapath adder and multiplier elements. Register minimization technique is used after folding to reduce the number of registers. After obtaining retimed, folded filter architecture, low level synthesis is performed which involves mapping of datapath adder and multiplier blocks to actual hardware. Various architectures of adders and multipliers are compared in area-power-performance space and depending on the user defined constraint, folded architecture with specific combination of data path elements is mapped on to hardware. A framework is designed in this paper to automate the entire process which reduces the design cycle time. All the designed filters are targeted for ASIC implementation. The results are compared and are provided as part of simulation results. [ABSTRACT FROM AUTHOR]

This paper presents a multi-output on-chip switched-capacitor (SC) DC-DC converter simultaneously providing two output voltages (2VDD/3 and VDD/3, in addition to the available full VDD) that enables the use of three different power modes for optimizing system power/performance trade-offs: super-threshold (full VDD), near-threshold (2VDD/3) and sub-threshold (VDD/3). Unlike some previously proposed multi-output SC converters, the multiple conversion ratios of the proposed converter are achieved without changing the topology of the circuit, thus fewer components being needed to support multiple voltages. The paper also presents an optimization method by using unequal flying capacitors for different regions of the circuit by taking advantage of the different levels of expected power consumption in the various power modes. Above 84% and 70% efficiencies are obtained in simulation over a range of load currents from 0.4 to 5 mA, and from 0.4 to 1 mA, with conversion ratios of 2/3 and 1/3, respectively. The target application for the proposed converter is for circuits with discrete power modes and for systems that use dithering to emulate a continuous range of voltages such as the panoptic dynamic voltage scaling (PDVS). [ABSTRACT FROM AUTHOR]

Chaotic systems with a curve of equilibria have attracted considerable interest in theoretical researches and engineering applications because they are categorized as systems with hidden attractors. In this paper, we introduce a new three-dimensional autonomous system with cubic equilibrium. Fundamental dynamical properties and complex dynamics of the system have been investigated. Of particular interest is the coexistence of chaotic attractors in the proposed system. Furthermore, we have designed and implemented an electronic circuit to verify the feasibility of such a system with cubic equilibrium. [ABSTRACT FROM AUTHOR]

This paper proposes a continuous-rate clock-data-recovery (CDR) circuit that covers a data rate range of 500Mbps to 1.7Gbps. The proposed CDR is based on the phase interpolation principle and implemented in 130nm CMOS. The design utilizes digital voter and phase control logic instead of analog charge pump and filter, which facilitates migration among different technologies. To avoid the phase interpolator (PI) getting into the nonlinear region, multiple modes are selected to limit the frequency range of the sampling clock within 500MHz to 1GHz. A 5mm2 test chip is fabricated, where the CDR core occupies 0.359mm2 of silicon area. The PI achieves a resolution of 7 bits and a good linearity of 0.9955. The proposed CDR also achieves a BER less than 10 and has a frequency tracking range of ppm. The power consumed by the proposed CDR is 32.6mW/Gbps. [ABSTRACT FROM AUTHOR]

The present methodology of clock distribution inside high-performance central processing unit chip offers current to ramp linearly or exponentially when the chip comes out of sleep mode to active mode or when the clock starts driving a chip to operate. This linear current ramp leads to power and ground noise due to d/d. In this paper, we have shown that for a given power delivery network (PDN), it is possible to generate a current profile (current versus time), by controlling the current on all the complementary metal oxide semiconductor gates of the clock generation circuits. In our methodology, the time for the chip to reach the maximum saturation current is same when compared with the present linear current ramp methodology. We have also developed a new 'optimizer program' to show the existence of a unique single current profile solution, which is different from the present methodology. The proposed method requires understanding of how the minimum value of the power supply voltage (supposed to be always 1V for the device) gets changed, when various gates in a clock tree are turned ON at different times (, parameters of the problem) with different values of current (, other parameters of the problem). Basically, an ensemble of '' number of transistors will be turned ON at time while it will pump the total current . This understanding generates the derivative function of the minimum noise point with respect to these said parameters, which in turn generates a new set of parameters to optimize the noise point. We have found that this optimizer program works and also converges for the generation of minimum power and ground noise, which is 40% lesser than the conventional approach. [ABSTRACT FROM AUTHOR]

Low-power consumption in three-dimensional integrated circuits (3D IC) design is becoming an important concern that cannot be neglected. The multiple layers/dies are stacked in 3D IC and communicate with each other through-silicon-vias (TSVs) to work as a single device in order to achieve high performance with minimum power dissipation. This paper demonstrates high-level power modeling approach for the power estimation of homogenous integration of Network-on-Chip (NoC)-based mesh architecture in 3D IC design. The preliminary experimental work of power model is divided into two major parts of the design. The first part estimates the power of NoC architecture on each stack separately and the second estimates the power dissipation of the uniformly distributed TSVs and input/output (I/O) pads. The model uses a linear function to estimate the average power dissipation. For an entire IC design, the average power is extracted by simple addition of all power estimation results of the model. The design is operated with multiple frequencies to find the most appropriate frequency to minimize power dissipation. In experiments, the average maximum error is estimated 18.03%. [ABSTRACT FROM AUTHOR]

Nowadays, power is a dominant factor that constrains highly integrated hardware-systems designs. The implied problems of high power density, causing chip overheating, or limited power source in modern Internet-of-Things devices are most commonly dealt with the use of the dynamic power management. This method enables to use power-reduction techniques, such as clock gating, power gating, or voltage and frequency scaling. Since the adoption of power management is quite difficult in modern complex systems, there are new approaches evolving intended to simplify power-constrained systems design. We have also proposed such an approach, utilizing the system level of design abstraction and increased automation in the design process. In this paper, the proposed hybrid verification approach is described that represents an integral part of the suggested design methodology. It consists of formal and informal techniques, enabling the verification process to begin at the very early specification stage of the system development. Our approach helps a designer to create correct and consistent power-management specification and verifies whether the specified power intent is preserved after design refinement. The continuous automated verification steps can quickly find errors at early design stages and thus reduce the amount of design re-spins, which speeds-up the overall development process. [ABSTRACT FROM AUTHOR]

This paper presents an innovative driver circuit for a new current regulator of the multilevel inverters. The proposed regulator has a PI controller to guarantee the optimum tracking for the reference current. This proposed regulator has the advantage of integration between the PI controller and the multicarrier switching operation. This regulator fits the operation of multi-level and cascaded converters. The suggested current regulator is compared with several existing current regulators of the multilevel and cascaded converters. The performance of the proposed regulator is verified using simulation results in comparison with the performance of the common existing current regulators for the multilevel inverter. Moreover, this paper shows the performance of the new regulator in power system applications. [ABSTRACT FROM AUTHOR]

New FPGA families can be reconfigured partially, meaning that only a certain portion of the chip area is reprogrammed. Partial reconfiguration makes possible to exchange function blocks on the FPGA and adapt it to a changing environment. It is used to have only a subset of necessary applications running on chip at each time, and replacing them by those needed. One of the challenging problems is the scheduling and the placement of modules on reconfigurable resources, this problem is called temporal placement. Several modules placement techniques have been introduced in the literature to solve the temporal placement problem. In this paper, we examine the temporal placement, showing how it can be decomposed into a number of distinct but not independent subtasks. Furthermore, in this paper, we have classified the temporal placement algorithms into the following classes: (1) Algorithms without design optimization (2) Routing cost optimization algorithms (3) Reconfiguration time optimization algorithms (4) Modules interfering optimization algorithms (5) Device resources optimization algorithms After that, experiments are conducted in order to evaluate the complexity and performances in term of traditional design metrics, like latency, area, etc., of each algorithm. [ABSTRACT FROM AUTHOR]