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First-order allpass filters are analog filters with a unit magnitude response, but they change the phase shift between input and output signals at various frequencies. This paper presents the transadmittance-mode first-order allpass filters based on the modified current-controlled current differencing transconductance amplifier (M-CCCDTA). The proposed filters utilize a single M-CCCDTA and a grounded capacitor with no external resistors, making them well suited for implementation in an integrated circuit. The gain and phase response of the proposed filters can be adjusted electronically and separately. Also, the high output impedance of the proposed filters at both the input voltage node and the output current node makes cascading easy without the need for buffer devices. A quadrature sinusoidal oscillator based on the proposed first-order allpass filter has been designed as an example of an application. The PSpice simulation and actual experiments are utilized to validate the functionality of the proposed filters. The simulation and experimental results are consistent with the idea of anticipation. [ABSTRACT FROM AUTHOR]

Tunability of correlated color temperature (CCT) and dimmability are the two major sought after features of functional solid-state lighting. This paper presents a low-cost, efficient, single-inductor-dual-output buck driver that facilitates CCT-control and dimming of a light emitting diode (LED) module composed of cool-white and warm-white chips. The proposed driver is designed based on two familiar integrated circuits (ICs), namely LM2596 and NE556. LM2596 serves as the main switching regulator and amplitude modulation (AM) controller whereas NE556 serves as the constant-frequency, dual-output pulse-width-modulation (PWM) controller. The exponential model of LED is exploited for improved estimation of the design parameters of the LED module and the driver circuit. The developed driver prototype is tested for its electrical, photometric, and colorimetric performances. The driver offers a full-load efficiency of about 90% for a 12-W test LED module. Under different operating modes, the LED system can produce warm, cool, or neutral white light and at the same time, the produced illuminance can be varied over a wide range. Moreover, the light flicker is imperceptible since the PWM frequency is set according to IEEE-1789 guideline. [ABSTRACT FROM AUTHOR]

The state-of-the-art development and subsequent miniaturization of technologies in e-systems such as computers and digital communication systems have led to densely and compactly placement of devices and interconnects in ICs. The incessant advancements of technologies have necessitated a rapid increase in operating frequencies. At nanometer dimensions and advanced technology nodes, the performance of the overall VLSI system is critically dominated by on-chip interconnects. Interconnects perpetuate several nonideal effects such as signal delay, power dissipation and cross-talk that limit the overall system performance. Owing to graving effect of interconnects on the performance parameters in ICs, research into interconnects has become meticulously very active in recent years, and concurrently much progress has been made. In this review paper, a literature review and contemporary advancements on conventional aluminum, copper and subsequent next generation graphene interconnects have been systematically presented. [ABSTRACT FROM AUTHOR]

The present methodology of clock distribution inside high-performance central processing unit chip offers current to ramp linearly or exponentially when the chip comes out of sleep mode to active mode or when the clock starts driving a chip to operate. This linear current ramp leads to power and ground noise due to d/d. In this paper, we have shown that for a given power delivery network (PDN), it is possible to generate a current profile (current versus time), by controlling the current on all the complementary metal oxide semiconductor gates of the clock generation circuits. In our methodology, the time for the chip to reach the maximum saturation current is same when compared with the present linear current ramp methodology. We have also developed a new 'optimizer program' to show the existence of a unique single current profile solution, which is different from the present methodology. The proposed method requires understanding of how the minimum value of the power supply voltage (supposed to be always 1V for the device) gets changed, when various gates in a clock tree are turned ON at different times (, parameters of the problem) with different values of current (, other parameters of the problem). Basically, an ensemble of '' number of transistors will be turned ON at time while it will pump the total current . This understanding generates the derivative function of the minimum noise point with respect to these said parameters, which in turn generates a new set of parameters to optimize the noise point. We have found that this optimizer program works and also converges for the generation of minimum power and ground noise, which is 40% lesser than the conventional approach. [ABSTRACT FROM AUTHOR]

This paper discusses a hybrid Digital-Analog Converter (DAC) architecture which is a combination of a binary-weighted resistor approach for eight bits in the least-significant-bit and thermometer coded approach for four bits in the most-significant-bit. The proposed design combines advantages of the binary-weighted resistor approach and thermometer coded approach. The final design is composed of two 12-bit DACs to achieve a pseudo differential output signal. The converter was designed with a Silterra 0.18 μm 1.8 V/3.3 V CMOS process technology. The post-layout simulation results show that this design achieves 12-bit resolution with INL and DNL of 0.375 LSB and 0.25 LSB, respectively. The power consumption is 6.291 mW when the designed DAC is biased with supply voltage equal to 3 V. The performance is accomplished with a design area of 230 μm × 255 μm. [ABSTRACT FROM AUTHOR]

An automated circuit analysis tool called SPICESoft, the main objective of which is to help designers in sensitivity computation and circuit analysis is presented. Three main features of SPICESoft are described, namely Sensitivity Analysis, Circuit Performance Analysis, and Inverse Circuit Performance Analysis. A new methodology called Binary Differential Expansion used for data interpolation is also described in this paper. The relationship between device and process parameters is covered. The simulation results obtained using the proposed automated tool are compared with those of conventional computation. [ABSTRACT FROM AUTHOR]