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First-order allpass filters are analog filters with a unit magnitude response, but they change the phase shift between input and output signals at various frequencies. This paper presents the transadmittance-mode first-order allpass filters based on the modified current-controlled current differencing transconductance amplifier (M-CCCDTA). The proposed filters utilize a single M-CCCDTA and a grounded capacitor with no external resistors, making them well suited for implementation in an integrated circuit. The gain and phase response of the proposed filters can be adjusted electronically and separately. Also, the high output impedance of the proposed filters at both the input voltage node and the output current node makes cascading easy without the need for buffer devices. A quadrature sinusoidal oscillator based on the proposed first-order allpass filter has been designed as an example of an application. The PSpice simulation and actual experiments are utilized to validate the functionality of the proposed filters. The simulation and experimental results are consistent with the idea of anticipation. [ABSTRACT FROM AUTHOR]

A simple circuit based on modified extra-X second-generation current conveyor (MEXCCII), which is capable of realizing the following grounded immittance functions: a lossless capacitor, a lossy capacitor, a lossy inductor and a lossy frequency-dependent negative conductance, is introduced in this paper. The circuit employs one MEXCCII and three passive components. The use of single active block makes the circuit structure simpler. No component's matching constraint is needed in the proposed circuit. The nonideal study of the proposed grounded immittance circuit is also included. The circuit's performance is examined using 0.18- μ m technology-based PSPICE simulations. Experimental results which are performed using off-the-shelf integrated circuits (ICs) and bread board are also included. The proposed circuit is negligibly affected by the temperature variation and process variation. A single pole high-pass filter as an application of the realized lossy capacitor and a band-pass filter as an application of the realized lossy inductor are also presented in this paper. The realized filters offer the feature of ease of cascadability. [ABSTRACT FROM AUTHOR]

The ancient Vedic mathematics is well known for quicker handy multiplications but its recognition as an integrated circuit core against existing hardware multipliers is not established. As optimized hardware implementation of binary multiplier is one of the prominent unsolved problems in computer architecture, this paper proposes efficient Urdhava Tiryakbhyam Vedic multiplier architecture and compares it with the set of hierarchical multiplication algorithms which generate multiplication result in a single clock cycle. Two innovative algorithms are proposed here, one with a compact structure and another for faster execution. Also, its optimized transistor level layout is designed and implemented. To maintain homogeneity for comparison, all the algorithms are programmed on a common HDL language platform and analyzed with the same tool and technology. Final results indicate that the proposed architecture delivers 15.5% less power delay product (PDP) compared to closest competitor algorithm. [ABSTRACT FROM AUTHOR]

In the analog and mixed-signal integrated circuits, voltage references that are independent of various factors such as temperature drift, noise, supply voltage, etc., and efficient in terms of power as well as area, are highly in demand to improve the efficiency of the overall circuits. Voltage references are one of those circuits that have applications in both high-power systems and low-power system-on-chip (SoC) designs for wireless connectivity like the internet of the things (IoT) or the internet of the medical things (IoMT). They are responsible for providing a stable bias or reference voltage. Thus, voltage reference influences directly or indirectly the performance of these systems. A comparative study between the techniques used in bandgap voltage references and CMOS voltage references, in terms of performance parameters such as line sensitivity, output noise, PSRR, temperature coefficient, etc., is presented in this paper so that we can choose the voltage references as per the applications and environment. [ABSTRACT FROM AUTHOR]

This paper suggests a new operational transconductance amplifier (OTA) based electronically tunable transimpedance-mode first-order universal filter (FOUF). The suggested FOUF produces all-pass (AP), high-pass (HP) and low-pass (LP) filter responses simultaneously. It employs three OTAs, two grounded resistors and only one grounded capacitor. Owing to use of grounded passive elements, the suggested FOUF is suitable for integrated circuit implementation. It operates at low power supply voltages. Additionally, the resonance frequency of the suggested AP filter can be adjusted in a wide frequency range. However, the suggested FOUF consists of only one matching condition. Moreover, a sinusoidal quadrature oscillator (QO) application that is derived from the suggested FOUF topology is given. The suggested FOUF and its QO application are simulated by using 0.18- μ m TSMC technology parameters in the SPICE program to validate the presented theory. Finally, an experimental test is performed to demonstrate workability of the suggested AP filter. [ABSTRACT FROM AUTHOR]

Full adders are a core component and play an essential role in the design of contemporary very-large-scale integration (VLSI) integrated circuits. Low-power, high-speed adder design has been the subject of numerous different sorts of research. The never-ending process is still in progress. The saturation point for MOS-based VLSI circuit design has been reached. As a consequence, many additional issues arise when MOS devices are scaled down to the nanoscale range, including an increase in leakage power and a vulnerability to PVT variation. Hence, MOSFET alternatives have been looked after by VLSI industries. Future nanoscale VLSI circuits would benefit greatly from the use of FINFETs in place of MOS transistors. In this paper, two diode-connected transistors-based low power, high speed, and low-power–delay product (PDP) adiabatic logic full adders are proposed using 7 nm technology. DCT TSAA-I, DCT TSAA-II, DCT TCAA-I, and DCT TCAA-II are the names of the proposed structures. Power, speed, and power–delay product (PDP) performance of the proposed adders are compared with those of traditional full adders. According to the simulation outcomes, the proposed adder architectures offer the least PDP in comparison to the adders taken into consideration. On power and delay, the impact of changing variables like temperature, supply voltage, load capacitance, and frequency is seen. A 7 nm FINFET model has been used in the simulations, which were conducted using the Hspice simulation tool. [ABSTRACT FROM AUTHOR]

Tunability of correlated color temperature (CCT) and dimmability are the two major sought after features of functional solid-state lighting. This paper presents a low-cost, efficient, single-inductor-dual-output buck driver that facilitates CCT-control and dimming of a light emitting diode (LED) module composed of cool-white and warm-white chips. The proposed driver is designed based on two familiar integrated circuits (ICs), namely LM2596 and NE556. LM2596 serves as the main switching regulator and amplitude modulation (AM) controller whereas NE556 serves as the constant-frequency, dual-output pulse-width-modulation (PWM) controller. The exponential model of LED is exploited for improved estimation of the design parameters of the LED module and the driver circuit. The developed driver prototype is tested for its electrical, photometric, and colorimetric performances. The driver offers a full-load efficiency of about 90% for a 12-W test LED module. Under different operating modes, the LED system can produce warm, cool, or neutral white light and at the same time, the produced illuminance can be varied over a wide range. Moreover, the light flicker is imperceptible since the PWM frequency is set according to IEEE-1789 guideline. [ABSTRACT FROM AUTHOR]

Side-channel attacks (SCAs) are powerful noninvasive attacks that can be used for leaking the secret key of integrated circuits (ICs). Numerous countermeasures were proposed to elevate the security level of ICs against SCAs. Unfortunately, it is quite inconvenient to predict the security levels of these countermeasures since no solid mathematical model exists in the literature. In this paper, neural network (NN)-based entropy is proposed to model the resilience of a system against SCAs. The NN-based entropy model well links the side-channel leakages and probabilities with the neurons and weights of NNs, respectively. In such a circumstance, the NN-based entropy can be used for modeling the robustness of countermeasures since a one-to-one relationship is established between the NN-based entropy and the measurement-to-disclose (MTD) enhancement ratio related with the countermeasures. As demonstrated in the result, the proposed NN-based entropy metric shows 100% consistency with the MTD enhancement ratio if multiple SCA countermeasures are employed into a system. [ABSTRACT FROM AUTHOR]

As the feature sizes of integrated circuits are reduced to the nanometer scale, the total soft error rate (SER) in memory and the proportion of multiple bit upsets (MBUs) are significantly increasing. In order to ensure the information reliability, many error correction codes with strong error correction ability were proposed, such as Reed–Somolon (RS) code and Bose–Chaudhuri–Hocquenghem (BCH) code. However, these error correction codes have limited error correction capability, high algorithm complexity and large data redundancy. In this paper, a novel fault tolerance method for locating and correcting multiple bit errors in memory is proposed based on data similarity. The proposed method uses the inner product as the metric to analyze the similarity of the pre-protected data from the vertical and horizontal dimensions, respectively, and to construct the model of error location and correction. This method performs encoding and decoding in units of blocks and detecting and correcting in units of words, so it can correct any number of bits in a corrupted word with low redundancy overhead. Finally, irradiation tests were conducted on a commercial SRAM, and the feasibility of the proposed method is verified by using heavy ion 8 6 Kr 2 6 + as irradiation source. [ABSTRACT FROM AUTHOR]

Improved speed, reduced delay, reduced size and reduced power are the most important requirements of integrated circuits. The carry select adder (CSA) is one of the most important adders in most data processors for performing arithmetic operations. The speed of parallel adders can be enhanced CSA, which widens the area to speed and eliminates propagation delays. The major problem faced in CSA is inefficient area due to the usage of multiple pairs of Ripple carry adders (RCAs) for generating the sums and carry. This research paper proposes the modified 32-bit square root carry select adder (MSCSLA) to improve the direct digital synthesizer's performance (DDS). DDS plays an effective role in the digital system due to its ability of broad frequency generation. Phase accumulator is the main component in the DDS synthesizer, where the speed of the adder is enhanced through MSCSLA. The general square root CSA still consumes more power due to the assembly of more RCAs. Hence, in the proposed approach, certain sets of RCAs are replaced with BEC1 (Binary to excess 1 convertor) to improve the speed and reduce the delay of the adder. Finally, the continuous sinusoidal waveform is attained by attenuating the high-frequency components by adopting a low pass filter. The entire structure of DDS is designed using Xilinx Verilog coding. The Simulation result shows better outcomes in terms of area, delay, power, and high performance in the DDS synthesizer compared to the existing CSAs. When compared to the existing adders, the area occupied by the proposed MSCSLA model is attained to be 636 μ m2, the power is achieved as 50.125 μ W and delay is attained to be 1.280 ns, which are comparatively less. When comparing delay and maximum frequency with the existing techniques, the proposed model obtained minimum delay and maximum frequency. The overall power consumption by the proposed model is also attained to be lower than the existing techniques. [ABSTRACT FROM AUTHOR]

In this paper, Pseudo-Boolean Satisfiability (PB-SAT)-based congestion reduction and overflow minimization techniques are introduced for constructing congestion-aware rectilinear Steiner trees for global routing in IC design. Since congestion in different routing channels is a big issue in routing nets, various congestion minimization approaches have been proposed by many researchers. However, the increasing complexity of integrated circuits and the reduction of their size make the congestion problem more complicated. The proposed method can produce a congestion-free routing solution by generating a suitable rectilinear Steiner tree for circuit nets. To reduce the complexity of the problem, the nets are solved individually using a Minimum Bounding Box (MBB)-based heuristic technique. The algorithm is validated by utilizing the well-known ISPD 98 global routing benchmarks. Experimental results prove that the methodology is capable of routing most of the nets within the given routing capacity satisfying all the routing parameters. The results also show that the algorithm can produce congestion-aware Steiner trees efficiently within a nominal time-bound. [ABSTRACT FROM AUTHOR]

The design complexity and outsourcing trend of modern integrated circuits (ICs) have increased the chance for adversaries to implant hardware Trojans (HTs) in the development process. To effectively defend against this hardware-based security threat, many solutions have been reported in the literature, including dynamic and static techniques. However, there is still a lack of methods that can simultaneously detect and diagnose HT circuits with high accuracy and low time complexity. Therefore, to overcome these limitations, this paper presents an HT detection and diagnosis method for gate-level netlists (GLNs) based on different machine learning (ML) algorithms. Given a GLN, the proposed method first partitions it into several circuit cones and extracts seven HT-related features from each cone. Then, we repeat this process for the sample GLN to construct a dataset for the next step. After that, we use K-Nearest Neighbor (KNN), Decision Tree (DT) and Naive Bayes (NB) to classify all circuit cones of the target GLN. Finally, we determine whether each circuit cone is HT-implanted through the label, completing the HT detection and diagnosis for target GLN. We have applied our method to 11 GLNs from ISCAS'85 and ISCAS'89 benchmark suites. As shown in experimental results of the three ML algorithms used in our method: (1) NB costs shortest time and achieves the highest average true positive rate (ATPR) of 100%; (2) DT costs longest time but achieve the highest average true negative rate (ATNR) of 98.61%; (3) Compared to NB and DT, KNN costs a slightly longer time than NB but the ATPR and ATNR values are approximately close to DT. Moreover, it can also report the possible implantation location of a Trojan instance according to the detecting results. [ABSTRACT FROM AUTHOR]

This paper presents a scalable Fully-digital differential analog voltage comparator designed in Semi-Conductor Laboratory (SCL) 180 nm complementary metal-oxide semiconductor technology. The proposed design is based on a digital design approach and is easily configurable to lower technology nodes. This design methodology makes the circuit less sensitive to process variations and takes fewer design efforts suitable for Systems-on-a-Chips (SOCs) application. The proposed circuit is designed and simulated in Cadence Virtuoso Analog Design Environment at the supply voltage ranging from 1 V to 1.8 V. The fully-digital analog voltage comparator has been synthesized using Synopsys Design Vision and auto-placed & auto-routed using Synopsys IC Compiler. This proposed comparator has a resolution of up to 7-bit at a supply voltage of 1.8 V and a worst-case operating frequency of about 750 MHz at the TT corner. The obtained value of the offset voltage and delay is 0.55 mV and 0.72 ns, respectively. The simulated results have shown that the power dissipation of the proposed scalable analog voltage comparator is 1 5 0 μ W @ 1 V and 3 1 2 μ W @ 1. 8 V supply voltage, respectively. Also, the RC extracted post-layout simulations have been implemented to verify the performance, which does not affect the results much. [ABSTRACT FROM AUTHOR]

In this research paper, a simple design of an ultra-wideband (UWB) multi-input multi-output (MIMO) antenna with low envelope correlation coefficient (ECC), high isolation, enhanced gain, radiation efficiency and reconfigurable band notching functionality is proposed. Two symmetrical slots are carefully integrated into the partial ground plane of the conventional monopole to provide a notched band at 5.8 GHz for the WLAN system. This notching method is simple and does not endure negative effect performance or any design complexity. The notched band is then controlled using PIN diodes. A complete biasing circuit is integrated on the same partial ground plane to bias the PIN diodes in forward and reverse directions. To reduce the complexity of the design that may be increased due to the reconfiguration circuit, isolation enhancement is accomplished by orthogonal placement of the elements rather than using any additional decoupling structures. A prototype of the MIMO UWB structure is fabricated and its performance parameters are experimentally tested. The captivating agreement between simulation and measurement demonstrates that the proposed antenna system is a good candidate for UWB applications with an operating band extending from 3 to 11 GHz, notch-band reconfiguration freedom, and isolation of more than 20 dB. [ABSTRACT FROM AUTHOR]

This paper introduces the experimental results obtained after processing an electrocardiographic signal by a full-custom, low-complexity, Sigma-Delta Modulator integrated circuit, designed and fabricated using the C5N CMOS technology available through MOSIS. By exploiting a large oversampling ratio, it was possible to obtain an effective number of bits equal to 11 at the proposed single-bit modulator's output. The resulting bitstream was captured with a logic-state analyzer and processed offline. After decimation and digital filtering, the electrocardiographic signal was reconstructed and plotted in the time domain. Commonly referred quality metrics over the retrieved signal were calculated. A total signal-to-noise and distortion ratio, superior to 66 dB, was achieved by analyzing the entire system. The proposed approach shows the feasibility of processing electrocardiographic signals using low-cost and straightforward CMOS technology circuits. Since the proposed converter uses a single voltage supply of 1.5 V, exhibits a power consumption of 38 μ W, and uses a silicon area of 0.052 mm2, it is suitable for single battery-operated systems on a chip. [ABSTRACT FROM AUTHOR]

Instead of boost/buck conversion processor, power supplies single-phase SEPIC conversion processor becomes widely used in computer motherboards and other integrated circuits as well as in photovoltaic solar cell systems. However, multiplier and multiphase interleaved conversion processors become preferred due to their identical advantages over traditional single-phase SEPIC from the possibility of current stress or ripple reduction in active or passive elements perspectives. This paper presents a new class of a double-phase SEPIC conversion processor that has a modified structure in order to maximize the dynamic performance of the previously mentioned topologies of SEPIC. An analytical comparative study was conducted for the multiplier and modified double-phase interleaved SEPIC processor with magnetically uncoupled inductive reactors to show the benefits of this new class of the double-phase connection of SEPIC when compared with the traditional and the multiplier connection. The proposed topologies of multiplier and modified SEPIC are simulated using the Simulink MATLAB, Excel and Simplorer 7. The experimental results and analysis have shown the improved characteristics of the proposed new class of the double-phase SEPIC, low harmonic distortion, sacredness to component tolerance, relief in overall current fluctuation reduction complexity, high power efficiency and a very high voltage gain. [ABSTRACT FROM AUTHOR]