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Micro-Electro-Mechanical System (MEMS) capacitive accelerometers have received extensive attention in recent years due to their excellent performance indicators; especially in the fields of noise, power consumption, and bias instability, great development and progress have been made. In the field of noise, effective noise reduction is achieved by introducing oversampling modulation technology combined with digital noise reduction technology. In power consumption, the power consumption of the accelerometer is effectively reduced by using the successive approximation structure in the interface circuit and using the finite state machine for precise control. In bias instability, the effects of temperature offset and zero-point drift are suppressed by using a hybrid topology connection structure in the interface circuit, and an effective reduction of bias instability is achieved. In this paper, the research and progress of MEMS capacitive accelerometer in the field of noise, power consumption and bias instability are reviewed, and the articles published in recent years are listed and summarized and prospected. [ABSTRACT FROM AUTHOR]

Reliability and energy efficiency are two hostile objectives considered in designing task scheduling in most real-time multiprocessor systems on chip (MPSoC). Addressing and improving one of them may affect and degrade the efficiency of the other one and vice versa. In this paper, we intend to examine these challenges and ultimately achieve an optimal energy consumption and reliability state. This paper presents a novel scheduling technique that can adapt to the limitations of real-time systems and have optimal energy consumption and reliability. This is done by minimizing the overlap of tasks, adjusting the speed of processors and the number of backups of each task. The proposed scheme reduces energy consumption on average by 11% to 42% compared to the previous state-of-the-art techniques and keeps the reliability at a high level. [ABSTRACT FROM AUTHOR]

In this paper, a fine-grained scheduling approach to enhance lifetime reliability of multiprocessor systems is presented. Lifetime reliability is an important and emerging concern arising with advances in technology due to the increase in power density. As a result, temperature variation accelerates wear-out, leading to system failures. The antagonistic relation of lifetime reliability with other design parameters of multiprocessor systems, such as power consumption and temperature, makes its improvement more challenging. Lifetime reliability enhancement approaches are considered at different levels of abstractions and for various system components. Our proposed scheduling method extracts the precise low-level information of lifetime reliability from determined blocks of processing cores and utilizes them at system-level to study the system state criticality at a low-performance cost. Based on the online periodic monitoring, our proposed scheduling approach applies control actions to improve lifetime reliability of the system according to its effective parameters. To demonstrate the effectiveness of our proposed scheduling approach in improving lifetime reliability and compare it to the previous related research, several experiments are considered. To simulate the target multiprocessor system and the proposed approach, the Enhanced Super ESCalar (ESESC) simulator for computer architecture tool is utilized. The experimental results show that employing our proposed scheduling method improves lifetime reliability at about 54 %. Moreover, it causes 14% and 12% enhancement in temperature and power consumption. Furthermore, we perform a Monte Carlo-based simulation to validate the proposed scheduling approach and generalize it to other applications at very low-performance overhead. Experimental results show that Monte Carlo simulation extremely decreases the execution time rather than ESESC which makes utilizing our scheduling approach reasonable in large applications. [ABSTRACT FROM AUTHOR]

With more cores integrated into a single chip and the fast growth of main memory capacity, the DRAM memory design faces ever increasing challenges. Previous studies have shown that DRAM can consume up to 40% of the system power, which makes DRAM a major factor constraining the whole system's growth in performance. Moreover, memory accesses from different applications are usually interleaved and interfere with each other, which further exacerbates the situation in memory system management. Therefore, reducing memory power consumption has become an urgent problem to be solved in both academia and industry. In this paper, we first proposed a novel strategy called Dynamic Bank Partitioning (DBP), which allocates banks to different applications based on their memory access characteristics. DBP not only effectively eliminates the interference among applications, but also fully takes advantage of bank level parallelism. Secondly, to further reduce power consumption, we propose an adaptive method to dynamically select an optimal page policy for each bank according to the characteristics of memory accesses that each bank receives. Our experimental results show that our strategy not only improves the system performance but also reduces the memory power consumption at the same time. Our proposed scheme can reduce memory power consumption up to 21.2% (10% on average across all workloads) and improve the performance to some extent. In the case that workloads are built with mixed applications, our scheme reduces the power consumption by 14% on average and improves the performance up to 12.5% (3% on average). [ABSTRACT FROM AUTHOR]

The conventional readout of one-transistor-one-capacitor dynamic random-access memories (1T-1C DRAMs) depends on using a sense amplifier to develop the bitline voltage and settle it to the voltage of the power supply, , or to 0V depending on whether the stored data is '1' or '0,' respectively. However, using the sense amplifier makes the reading process sluggish. In this paper, a capacitive-voltage divider-based readout scheme is proposed. According to this scheme, the developed bitline voltage is converted into a pulse with a certain starting time. Specifically, this pulse appears at a later time in case of '0' storage than that if a '1' is stored, thus the proposed scheme is aptly called 'time-domain readout.' The effects of parameter and component mismatches and technology scaling on the proposed scheme are investigated. The proposed scheme is analyzed quantitatively with a suggestion given to widen the time gap between the starting times of the pulses corresponding to the '0' and '1' states. The proposed scheme is verified by simulation adopting the 45 nm CMOS technology with V. According to the simulation results, percentage savings of 68.8%, 56.8%, and 32% in the read-access time, the read-cycle time, and the average power-delay product, respectively, are shown. The proposed scheme requires approximately 40% extra area overhead for the reading circuitry. Also, a noise analysis is performed and it is found that the device noise does not affect the proposed scheme significantly. [ABSTRACT FROM AUTHOR]

Dynamic frequency scaling (DFS) is a feature commonly found in modern processors. It lowers the clock frequency of a core according to the load level and reduces the power consumption. In this paper, we present a case study of tuning DFS parameters on a platform with an AMD Phenom II X6 using the SPECjEnterprise2010 (jEnt10) and SPECjbb2005 (jbb05) as the workload. In jEnt10, a longer sampling period of core utilization (up to 1.5s) reduced the power by 6Watt at 25% load level. At 50% load level, combining it with an increased threshold level (98%) to switch the clock frequency further reduced the power consumption by up to 10Watt. In jbb05, stretching the sampling period was only effective up to 0.5s. The maximum reduction was observed at around 60% load level. Raising the threshold level was not effective for jbb05. [ABSTRACT FROM AUTHOR]

In this paper, an energy efficiency (EE) analysis for elastic optical networks (EONs) considering the adaptive allocation of the transmitted power, spectrum bandwidth, modulation format and forward error correction (FEC) type has been proposed. The trade-off between the FEC coding types and the optical layer EE (OL-EE) was investigated considering the capacity of information transmission and power consumption. The power consumption model considers elements involved in the lightpath establishment, namely transmitter, receiver, bandwidth-variable optical crossconnect (BV-OXC), optical amplifiers and network control. Numerical examples have demonstrated EE increasing for the lightpaths when adaptive FEC coding is deployed; furthermore, the EE varies with the distance of the optical network nodes and hop count. In this sense, it is observed that the EE decreases with the increasing of FEC energy per bit consumption; however, an operation region is verified in which the overall EE network with FEC is superior to the system without FEC coding. After this point, the increases in the FEC energy per bit consumption will affect negatively the EE metric. For instance, with the proposed OL-EE model it is possible to determinate the maximum energy consumption allowed to the FEC codes without OL-EE system degradation. [ABSTRACT FROM AUTHOR]

This paper presents a new power efficient single ended sense amplifier (SA). The proposed circuit is based on the direct current voltage conversion technique. It has been simulated using Microwind3 and DSCH3 tools (advanced BSIM 4 level) for 90 nm CMOS technology in terms of power consumption, sense time and results were compared to other circuits. The proposed SA circuit consumes more than 50% less power and gives 90% faster sensing speed compared to other circuits. The lower power consumption is due to lower leakage current, lower voltage drop on bit-line and faster speed is due to positive feedback of the circuit. The proposed circuit is more robust against any process and temperature variation. [ABSTRACT FROM AUTHOR]

The increasing power consumption levels of integrated circuits (ICs) have become a major concern of the semiconductor industry. Excessive power dissipation causes overheating, which can lead to soft errors or permanent damage. It also limits battery life in portable equipment. High power consumption can be reduced by properly increasing area. However, arbitrarily large area, namely high number of functional units (FU) in high-level view, dramatically increases IC cost. This paper describes a new dynamic-power aware High Level Synthesis data path approach that considers dynamic FU allocation while attempting to minimize area, power, or make a trade-off between them. The experimental results have shown that when the area is nearly the same, our approach delivers a 5.99% reduction in power consumption. And when the power consumption is nearly the same, a 11.81% reduction in total FU area occurs. And we can obtain different optimal power-area trade-off values by adjusting power and area ratios. [ABSTRACT FROM AUTHOR]

In this paper, we present a bisection-based power reduction design for CMOS flash analog-to-digital converters (ADCs). A comparator-based inverter is employed along with two switches of an NMOS and a PMOS, the bisection method can let only half of comparators in a flash ADC work in every clock cycle for reducing power consumption. A practical example of 6-bit flash ADC operates at 200 MHz sampling rate and 3.3 V supply voltage is demonstrated. The power consumption of proposed circuit is only 40.75 mW with HSPICE simulation. Compared with the traditional flash ADC, our bisection method can reduce up to 43.18% in terms of power dissipation. [ABSTRACT FROM AUTHOR]

Computer-aided design (CAD) tools are frequently employed to verify the design objectives before the fabrication of an integrated circuit. An important circuit parameter that requires accurate characterization is the power consumption due to the strict constraints on the acceptable power envelope of integrated systems. Circuit simulators typically provide built-in functions to measure the power consumption. However, the accuracy of the measured power is mostly overlooked since the approximations and the methodologies used by the existing built-in power estimation tools are not well documented. The research community tends to assume that the built-in functions provide accurate power figures. This blind-trust in the CAD tools, however, may lead to gross errors in power estimation. A generic methodology to accurately measure the power and energy consumption with the circuit simulators is described in this paper. An equation to calculate the device power consumption based on the different current conduction paths in a MOSFET is presented. An expression for the total power consumption of a complex circuit is derived by explicitly considering the different circuit terminals including the inputs, the outputs, and the body-contacts. Results indicate that the power measurements with the built-in functions of widely used commercial circuit simulators can introduce significant errors in a 65 nm CMOS technology. For deeply scaled nano-CMOS circuits, a conscious power and energy measurement with the proposed explicit methodology is recommended for an accurate pre-fabrication circuit characterization. [ABSTRACT FROM AUTHOR]

Power consumption of multimedia applications executing on embedded cores is heavily dependent on data transfers between system memory and processing units. The purpose of this paper is to extend an existing power optimizing methodology based on data-reuse decisions, in order to determine the optimal solution in a rapid and reliable way. An analytical approach is proposed by extracting expressions for the number of accesses to each memory layer. Moreover, the design space is further reduced since these analytical expressions are calculated only for a subset of all transformations. The results concerning the power efficiency of data-reuse transformations are in agreement to those in previous studies. However, the exploration time of the design space is significantly reduced. The proposed methodology is also applied to the case of multiple parallel processing cores, proving that the relative effect of each transformation is independent on the number of processors and the applied memory architecture. [ABSTRACT FROM AUTHOR]