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In this paper, Pseudo-Boolean Satisfiability (PB-SAT)-based congestion reduction and overflow minimization techniques are introduced for constructing congestion-aware rectilinear Steiner trees for global routing in IC design. Since congestion in different routing channels is a big issue in routing nets, various congestion minimization approaches have been proposed by many researchers. However, the increasing complexity of integrated circuits and the reduction of their size make the congestion problem more complicated. The proposed method can produce a congestion-free routing solution by generating a suitable rectilinear Steiner tree for circuit nets. To reduce the complexity of the problem, the nets are solved individually using a Minimum Bounding Box (MBB)-based heuristic technique. The algorithm is validated by utilizing the well-known ISPD 98 global routing benchmarks. Experimental results prove that the methodology is capable of routing most of the nets within the given routing capacity satisfying all the routing parameters. The results also show that the algorithm can produce congestion-aware Steiner trees efficiently within a nominal time-bound. [ABSTRACT FROM AUTHOR]